AMC to PCIe Adaptor Schematic

Transcription

1 M to PIe daptor Schematic SHEMTI PGE ESRIPTION : 0 : OVER SHEET 0 : LOK IGRM 0 : INTERFES 0 : REVISION HISTORY & UMMY PRTS MJOR REVISION HISTORY : P REV. SH. REV. ESRIPTION TE.0.0 Proto uild -March-0.0. Release For Production of 0-May-0.. Release For Production of -July-0 P Mechanical etails : P LYER STK-UP ETILS :. P SIZE:." x.". P MTERIL: FR0. MER OF LYERS: 0. IMPENE ONTROL: YES NOTES, UNLESS OTHERWISE SPEIFIE :. RESISTNE VLUES RE IN OHMS.. PITNE VLUES RE IN MIROFRS.. PRTS NOT INSTLLE RE INITE WITH ''.. SIGNL NET NMES WITH "#" SUFFIX, RE TIVE LOW SIGNLS. M to PIe daptor OVER SHEET esigned for TI by ocument Number ate: Thursday, July, 0 of

2 LOK IGRM M to PIe daptor LOK IGRM esigned for TI by ocument Number ate: Thursday, July, 0 of

3 V TP V_PIe V R.K T + 0uF,0V V._PIe 0--F V. V. V J TSW-0-07-S-S Green LE SML-LX0GW-TR PIe x Edge Fingers V._PIe PIe_RX0P PIe_RX0N PIe_RXP PIe_RXN PIe_RXP PIe_RXN PIe_RXP PIe_RXN V_PIe J PIe x V. PRSNT# +V +V JTG JTG JTG JTG +.V +.V REFLK+ REFLK- PERP0 PERN0 RSV PERP PERN PERP PERN PERP PERN RSV R KEY +V +V RSV SMLK SMT +.V JTG.VUX WKE# RSV PETP0 PETN0 PRSNT# PETP PETN PETP PETN PETP PETN RSV PRSNT# m 00LW-7-F V_PIe V._PIe R0 R R7 ENLE# R R PIe_TX0P PIe_TX0N PIe_TXP PIe_TXN PIe_TXP PIe_TXN PIe_TXP PIe_TXN SM_SL_IPML SM_S_IPML TP T + 00uF,0V R SML-LX0GW-TR R.K Green LE PS# M Socket onnector J FLK TLK / PORT 7 PORT PORT PORT PORT PORT PORT PORT 0 JTG PORT 0 PORT PORT PORT 7 TLK / PORT PORT PORT PORT PORT PORT 0 PORT PORT PS# G0 M0_SGMII0_TX_P M0_SGMII0_TX_N M0_SGMII0_RX_P M0_SGMII0_RX_N G G ENLE# SM_SL_IPML SM_S_IPML TM_LK_P TM_LK_N TM_LK_P TM_LK_N PS0# TP V. V M Edge Fingers J M Edge Fingers Rx+ Rx- _ PWR_V_ PS MP G0 RSRV _ RSRV PWR_V Tx0+ Tx0- _ Rx0+ Rx0- _ G PWR_V Tx+ Tx- _7 Rx+ Rx- _ G PWR_V Tx+ Tx- _0 Rx+ Rx- _ Tx+ Tx- _ Rx+ Rx- _ ENLE PWR_V Tx+ Tx- _ Rx+ Rx- _ Tx+ Tx- _7 Rx+ Rx- _ SL_L PWR_V Tx+ Tx- _0 Rx+ Rx- _ Tx7+ Tx7- _ Rx7+ Rx7- _ S_L PWR_V_7 _ TLK+ TLK- _ TLK+ TLK- _ FLK+ FLK- _7 PS0 PWR_V 70 _ TI TO 7 TRST TMS TK _ Tx0+ Tx0- _ Rx0+ Rx0- _ 7 Tx+ Tx- _ Rx+ Rx- _ Tx+ 0 Tx- _0 Rx+ 7 Rx- _ Tx7+ Tx7- _ Rx7+ Rx7-0 _7 TLK+ TLK- 7 _ TLK+ TLK- _ Tx+ Tx- _ 0 Rx+ Rx- _ 7 Tx+ Tx- _ Rx+ Rx- _ Tx+ 0 Tx- _0 Rx+ 7 Rx- _ Tx+ Tx- _ Rx+ Rx- 0 _7 0 Tx+ 0 Tx- 07 _ 0 Rx+ 0 Rx- 0 _ 0 Tx0+ 0 Tx0-0 _ 00 Rx0+ Rx0- _ Tx+ Tx- _ Rx+ Rx- _ Tx+ Tx- _0 Rx+ Rx- _ JTG_TI JTG_TO JTG_TRST# JTG_TMS JTG_TK Rx7+ Rx7- Tx0+ Tx0- Rx0+ Rx0- Tx+ Tx- Rx+ Rx- Tx+ Tx- Rx+ Rx- Tx7+ Tx7- Rx+ Rx- TM_LK_P TM_LK_N TM_LK_P TM_LK_N Tx+ Tx- PIe_LK+ PIe_LK JTG_TI JTG_TO 7 JTG_TRST# 7 JTG_TMS JTG_TK Tx0+ Tx0- Rx0+ Rx0-7 Tx+ 7 Tx- Rx+ Rx- Tx+ 0 Tx- 0 Rx+ 7 Rx- 7 Tx7+ Tx7- Rx7+ Rx7-0 0 TM_LK_P TM_LK_N 7 7 TM_LK_P TM_LK_N Tx+ Tx- 0 Rx+ 0 Rx- 7 Tx+ 7 Tx- Rx+ Rx- M_P_TM_TX 0 M_P_TM_TX 0 M_P_TM_TX 7 M_P_TM_TX0 7 M_P_TM0_TX M_P_TM0_TX M_P_TM0_TX M_P_TM0_TX M_P_SRIO_TXP 0 0 M_P_SRIO_TXN M_P_SRIO_RXP 0 0 M_P_SRIO_RXN M_P0_SRIO_TXP 0 0 M_P0_SRIO_TXN M_P0_SRIO_RXP 00 M_P0_SRIO_RXN M_P_SRIO_TXP M_P_SRIO_TXN M_P_SRIO_RXP M_P_SRIO_RXN M_P_SRIO_TXP M_P_SRIO_TXN M_P_SRIO_RXP M_P_SRIO_RXN G0 M0_SGMII0_TX_P M0_SGMII0_TX_N M0_SGMII0_RX_P M0_SGMII0_RX_N G Tx+ Tx- Rx+ Rx- G Tx+ Tx- Rx+ Rx- Tx+ Tx- Rx+ Rx- ENLE# PIe_RX0P PIe_RX0N PIe_TX0P PIe_TX0N PIe_RXP PIe_RXN PIe_TXP PIe_TXN SM_SL_IPML PIe_RXP PIe_RXN PIe_TXP PIe_TXN PIe_RXP PIe_RXN PIe_TXP PIe_TXN SM_S_IPML TM_LK_P TM_LK_N TM_LK_P TM_LK_N PIe_LK+ PIe_LK- PS0# Tx+ Tx- Rx+ Rx- Tx+ Tx- Rx+ Rx- Tx+ Tx- Rx+ Rx- Tx+ Tx- M_P_TM_TX M_P_TM_TX M_P_TM_TX M_P_TM_TX0 M_P_TM0_TX M_P_TM0_TX M_P_TM0_TX M_P_TM0_TX0 M_P_SRIO_TXP M_P_SRIO_TXN M_P_SRIO_RXP M_P_SRIO_RXN M_P0_SRIO_TXP M_P0_SRIO_TXN M_P0_SRIO_RXP M_P0_SRIO_RXN M_P_SRIO_TXP M_P_SRIO_TXN M_P_SRIO_RXP M_P_SRIO_RXN M_P_SRIO_TXP M_P_SRIO_TXN M_P_SRIO_RXP M_P_SRIO_RXN G S Q N700 00m/V R 0K % NOTE: When = 0; Q = OFF; MM in Reset When = ; Q = ON; MM out of Reset MM (MSP0) in EVM shall assert POR (MM_POR_IN_M#) each time it is out of Reset. TP TP MT MT MT MT MT MT M to PIe daptor INTERFES ocument Number esigned for TI by. F F F ate: Thursday, July, 0 of

4 REVISION HISTORY P REV. SH. REV. HNGE ESRIPTION TE UTHOR 0. Initial raft March 0, R and R are removed, now single net of V. March, 0 0. Two Power diodes and are added on PIe powers. Shunt-post J added. Extra cap T removed. M Ports,,,,7,,,0 and JTG from socket connector connected with M edge fingers. I bus of PIe is connected to IPM bus of M Port used as SERES port March 0, 0 Issue.0 Released for P Fabrication March, onnection provision added for J.7 to connect with net M ENLE# connected to through Open rain Inverter May, 0. Resistor connected on Pin J. (PRESNT#) May 0, 0 Issue. Released for P Fabrication May, 0. Issue. Layer stack-up changed from layer to layer. ielectric material changed from FR to ISOL FR0HR. V. UX isolated from V. power plane using resistor. Released for P Fabrication. July, 0 UMMY OMPONENTS M I/O racket M oard Spacer M oard Spacer M oard Screw M M M M7 oard Screw oard Screw oard Screw M M0 M M to PIe daptor REVISION HISTORY ocument Number esigned for TI by. oard Stud oard Stud oard Stud oard Stud ate: Thursday, July, 0 of

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