Platform-based SW/HW Synthesis

Transcription

1 Platform-based SW/HW Synthesis Zhong Chen, Ph.D. (Visiting Prof. from Peking University) SOC Group,UCLA Led by Jason Cong ICSOC Workshop Taiwan 03/28/2002

2 Contents Overview HW/SW Co-design Flow System Data Model Capability SIR MOC SDM-API Jpeg Example Further Research Topics

3 Overview Platform-based Synthesis Start from system level design description Target to FPSoC platform Automate the process as much as possible System Data Model MOC Model of Computation System-Level Synthesis Algorithms Incorporate models such as Funstate model etc. Internal Representation cover whole life-cycle of the flow SDM-API supports inter-operatability of CAD tools

4 Proposed Platform-based HW/SW Synthesis System Design Specification Platform Information Profiling Spec& Implementation Simulation System Data Model Hardware Estimation Software Estimation Partitioning Scheduling SW Code Gen VHDL HW Code Gen System Synthesis System P.E. Interface Synthesis HW synthesis C Code VHDL SW synthesis Target SW Target PLD

5 System Level Description to FPSoC Platform SLD: Support of concepts needed in system design Structural and behavioral hierarchy Concurrency State transitions Communication Exception handling Timing Select SpecC Language as an Input Superset of ANSI-C ANSI-C plus Extensions for HW-design Leverage of large set of existing program Software requirements are fully covered SpecC model PSM MOC Separation of communication and computation Hierarchical network of behaviors and channels Plug-and-play Source: System Design: A Practical Guide with SpecC, Andreas Gerstlauer etc.,kluwer Academic Publishers

6 Our Sample Target FPSoC Platform Excalibur TM Platform High-Performance Embedded Processor Nios CPU Up to 150K Gates Available for Customization EP20K200E Programmable Logic Device

7 Other optional version of Excalibur Nios CPU 75K Gates Available for Customization Nios Nios EP20K 100E Embedded System Blocks(ESBs) ESB Nios ESB Nios 500K Gates Available for Customization ESB ESB Multi-Processor Micro-Coded System

8 Components in our FPSoC Platform PLD: APEX TM20K200E (8320 LEs) Processor: Nios 16-bit or 32-bit Configurable 5-stage pipeline architecture One instruction per cycle Optimized for APEX PLD efficiency 20% of APEX EP20K200E device in 32-bit configuration Up to 50MIPS and 50MHz Memory: on-chip 256K Supports on-chip and off-chip memories I/O: Customizable, on-chip peripherals JTAG, PCI user-definable

9 JPEG Encoder An example BMP BMP Image Image File File Image Image Fragmentation Fragmentation DCT DCT JPEG: JPEG: an an standard standard for for image image compression compression DCT: DCT: Discrete Discrete Cosine Cosine Transform(ChenDCT) Transform(ChenDCT) Four Four mode mode of of the the operations operations in in JPEG JPEG standard standard Sequential Sequential DCT-based DCT-based mode mode Progressive Progressive DCT-based DCT-based mode mode Lossless Lossless mode mode Hierarchical Hierarchical mode mode Quantization Quantization Entropy Entropy Coding Coding JPG JPG Image Image File File

10 Jpeg in SpecC Source Code Files Global Global Chann Chann Adapter+ Adapter+ Header Header Huff+ Huff+ Dct++# Dct++# Quant+ Quant+ Handle+ Handle+ Default+ Default+ Encode+- Encode+- Jpeg+- Jpeg+- Io Io Design+- Design+- Tb Tb SpecC: Specification Language and Methodology Daniel D. Gajski etc., CECS, UC Irvine

11 Jpeg in SpecC Program Structure

12 SDM MoC : FunState-based MoC F SW c1 b F S b b F R b c1 F HW M1 M2 CE(M 1 )/F S /F R CE (M 2 )/F HW FunState An Internal Design Representation for Codesign, Karsten Strehl etc. IEEE Transactions on VLSI System, VOL. 9, No.4 AUGUST 2001

13 Jpeg : From SpecC to SDM representation Header Input Jpeg Output Data Pixel Input Jpeg Output Tb.sc with fixed control flow

14 Jpeg: Its MoC Representation in SDM Jpeg.sc JpegInit ImageWidth ImageHeight DCEhuff ACEhuff Jpeg Encode JpegEnd Data JpegInit JpegEncode JpegEnd JpegInit, JpegEnd are functions, JpegEncode is InnerComponent

15 Jpeg: Its MoC Representation in SDM JpegEncode.sc Receive Data stripe MDUWide JpegEncodeS tripe ImageWidth ImageHeight mduhigh DCEhuff ACEhuff MDUHigh mduhigh=0, MDUHigh= (ImageHeight+7)>>3 ~Cond Cond/ ReceiveData JpegEncode Stripe mduhigh+ + Cond is (mduhigh < MDUHigh)

16 Jpeg: Its MoC Representation in SDM JpegEncodeStripe.sc Handle Data A dct Quantiza B tion C Huffman Encode mduhigh stripe MDUWide DCEhuff ACEhuff mduwide ~Cond mduwide = 0 Cond/ HandleData dct quantization huffmancode mduwide ++

17 Partitioning and Scheduling - (now manually) SW Recv Send HW Input JPEG Receivedata JpegEncodeStripe Data Output DCT Send Recv Input Jpeg Output

18 Current flow where are we today Designer Simulate Simulate act act Profile Profile rpt rpt (7) (9) Simulator.exe Simulator.exe Profiling.exe Profiling.exe (6) (8) Design.cc Design.cc (5) Design.c Design.c (1) MyDesign.sc MyDesign.sc (2) Design.sc Design.sc (3) Design.sir Design.sir (4) Design.sdm Design.sdm (12) (10) Design.vhdl Design.vhdl (13) (11) 1) A System Designer Write a System-level design app in SpecC; 2) Rewrite it in order to go through our flow; Using a SubSet format of SpecC and modified semantics 3) Using scc to create.sir 4) Using psm2fs to convert.sir to.sdm 5) Using simgen to generate.cc for simulator 6) Compile the simulator using CC compiler; 7) Execute the simulator; 8) Compile to Profiling.exe using CC with profile options; 9) Execute it to generate Profile report; 10) Using hwcgen to generate.vhdl 11) Using Altara s tools to generate circuit.srec 12) Using sccgen to generate.c 13) Using target C compiler to generate executable code Design.exe Design.exe HW.srec HW.srec

19 Intermediate Research Achievements SDM- Converter SDM- Simulator SDM- C Code Generation tool SDM- SW Profiling tool SDM- HW Code Generation tool (partial)

20 Jpeg Implementation on Excalibur TM Platform Jpeg Software Nios CPU DCT Circuit EP20K200E Programmable Logic Device

21 Jpeg Compression Results 116x96x8 image in bmp format (12214 Bytes) 116x96x8 image in jpeg format (1704 Bytes)

22 JPEG Encoder Profiling BMP BMP Image Image File File Image Image Fragmentation Fragmentation 1.72% DCT DCT 77.47% Quantization Quantization 4.84% Entropy Entropy Coding Coding 15.97% JPG JPG Image Image File File

23 Run-time Profiling of Jpeg Program Module Name PC(PIII 650MHz) NIOS(SW) NIOS(SW+HW) HandleData /s* 2.56 µs /s µs /s µs 1.72% 1.22% 4.45% DCT /s µs 316.4/s µs 6328/s µs 77.47% 76.46% 13.97% Quantization /s 7.22 µs /s µs /s µs 4.84% 4.27% 15.60% HuffmanEncode /s 23.8 µs /s µs /s µs 15.97% 18.05% 65.98% *Unit: execution times per second; time in micro-second(µs) of one time execution; rate among one time execution for processing one 8x8 image block of 256 colors.

24 Run-time Results of Jpeg Example Module Name PC(PIII 650MHz) NIOS(SW) NIOS(SW+HW) 1 NIOS(SW+HW) 2 time (10-6 s) rate(%) time (10-6 s) rate(%) time (10-6 s) rate(%) time (10-6 s) rate(%) HandleData DCT Quantization HuffmanEncode % 77.47% 4.84% 15.97% % 76.46% 4.27% 18.05% % 62.78% 6.75% 28.55% % 13.97% 15.60% 65.98% ( ) ( ) ( ) ( ) ( ) (316.4) ( ) ( ) ( ) (609.37) ( ) ( ) ( ) ( ) ( ) ( ) Total % % % % *Notes: one time execution for processing one 8x8 image block of 256 colors. 1: with half DCT implementation in order to fit in the area; Nios 1.1 work at 33Mhz 2: optimized DCT full implementation with simulation only ( by modulesim)

25 Research Topics Sytem-Level Synthesis Algorithm Partitioning and Scheduling Performance Estimation Architecture Exploration Hardware Interface Synthesis Architecture Exploration Platform Resource Information Software Synthesis Code Optimization with Resource Constraints Support Polymorphism Description of Channel and Interface(?)

26 HW implementations of DCT Performance LEs Rate PINs Rate ESBs Rate Clock Frequency EP20K200EFC 484-2X % % % Max. 33M (1)Nios+H_dc t+recv+send /s % % % Half_dct only (recv+send) % 30 7% (2)NIOS+dct +Memory /s % % % (Dct only) % 30 7% (1) Half-Dct implementation + Interface with PIO of Nios (through send + recv) (2) Full-Dct implementation + Memory as Interface

27 Open Discussion