The Lekha 3GPP LTE Turbo Decoder IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1].

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Alvin Barnett
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Lekha IP Core: LW RI 1002 3GPP LTE Turbo Decoder IP Core V1.0 The Lekha 3GPP LTE Turbo Decoder IP Core meets 3GPP LTE specification 3GPP TS 36.212 V 10.5.0 Release 10[1].

1 Lekha IP Core: LW RI GPP LTE Turbo Decoder IP Core V1.0 The Lekha 3GPP LTE Turbo Decoder IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1]. Introduction The Lekha IP 3GPP LTE Turbo Decoder IP Core V1.0 addresses the decoder implementation for the turbo coded transport channel compliant to 3GPP TS V The Lekha Turbo Decoder IP is a highly parallel and hardware efficient architecture to meet high throughputs demanded by the LTE and LTE Advanced standards and next generation large MIMO systems. The decoder exploits algebraic properties of the quadratic permutation polynomial (QPP) interleaver, to avoid memory contention issues when several MAP decoders are used in parallel. Lekha Turbo Decoder Features 3GPP LTE/ LTE Advanced (LTE A) specification complaint Implements decoder for requirements as defined in Section of the specification [1] Highly parallel and hardware efficient architecture Supports all code block sizes i.e., Programmable number of iterations in half iteration step Support for Rate 1/3 coded output Programmable parallelism. Option for 1,2,4,8 MAP decoders in parallel. De-rate matching block can be optionally included Employs state metric propagation to improve performance of the decoder for high coding rates Easy interface definition. Customization to AXI or Avalon bus interface supported. Bit accurate C and MATLAB models available for RTL test vector generation. HARQ feature support Device Support Supports several devices across Xilinx, Altera and Lattice device families. Test Environment HDL IP models have been verified to be bit exact with the Matlab/ ANSI C models. These are fully compliant to the LTE/ LTE A specification. 1

2 General Description In recent years, Turbo codes have gained wide popularity across multiple wireless technologies and standards. They are a class of high performance forward error correction (FEC) codes which closely approach the channel capacity (Shannon limit - theoretical maximum code rate) at which reliable communication is still possible given a specific noise level. Long term evolution (LTE) is a 3GPP initiative for next generation wireless technology which is gaining fast ground as a technology of choice to provide reliable communication and data rates for broadband mobile communications. LTE advanced (LTE-A) packs more features to extend the data rates even further. Turbo codes form the core part of forward error correction coding in 3GPP LTE and LTE advanced standards. A high level functional block diagram of the Turbo Decoder IP Core is shown in Fig.1 below. decoder_en sob K[12:0] N[3:0] S[7:0] P1[7:0] P2[7:0] De-Rate Matching P1 S P2 D MAP1 E1 A1-1 A2 E2 MAP2 D CRC computation rdy_nb dec_out_valid d_out decoder_done Soft Bits HARQ Support Rate Matching Turbo Decoder IP Core Fig.1 High level Block diagram of Turbo Decoder IP Core Decoder Algorithm The basic turbo decoder (TD) consists of two maximum aposteriori (MAP) decoders, separated by an interleaver that permutes the input sequence. The iterative decoding process exchanges extrinsic information between MAP decoders every iteration. Each iteration is divided into two half iterations. During the first half iteration, MAP decoder 1 receives systematic (S) and parity (P1) bits or LLRs (soft representation of bits) along with apriori (A1) information from the other MAP decoder (MAP decoder 2) via deinterleaving and generates the extrinsic information (E1). In the second half iteration, MAP decoder 2 receives the interleaved systematic bit (S_i), parity bit (P2) and a priori information (A2) and 2

3 generates extrinsic information (E2). The iterative process repeats until the decoder converges or the maximum number of iterations has been reached. Deliverables Licensable in Netlist or Verilog or VHDL source format Target technology Xilinx, Altera, Lattice devices Test bench MATLAB, C, VHDL, Verilog simulation models available Detailed technical documentation. Turbo Decoder Port Description The basic Decoder IP Core block diagram with the port list is as shown in fig. 2 below. decoder_en sob K [12:0] N [3:0] rdy_nb User Logic S [7:0] P1 [7:0] Lekha Turbo Decoder IP Core dec_out_valid d_out P2 [7:0] decoder_done rst clk Fig. 2 Turbo Decoder Block diagram Ports Directi Size Description on clk Input 1 Clock input to the decoder. Rising edge is used. rst Input 1 Asynchronous reset. Active high decoder_en Input 1 Active high enable for turbo decoder operation sob Input 1 Start of block K Input 13 Block size of the input data N Input 4 Number of iterations (in half iteration steps) 3

4 S Input 8 8-bit Systematic soft bit input data P1 Input 8 8-bit Parity1 soft bit input data P2 Input 8 8-bit Parity2 soft bit input data decoder_out_ Output 1 Indicates that a valid output is available on d_out valid d_out Output 1 Decoded output bit(s) decoder_done Output 1 Indicates Input Interface All block sizes from are supported by the IP core. For a given block size of K, the input soft bits are ordered in the format S, P1, P2. Each of the S, P1, P2 inputs can be either 6 bit or 8 bit wide. The input data path is double-buffered to enable processing of one block of data while one block is being written into the decoder core buffer. The input interface has well defined control and status signals. decoder_en is an active high signal that is required to enable the Turbo decoder operation. rdy_nb indicates that a block of data is processed through the decoder and the core is ready to accept another block of data. The user logic or the host then signals sob indicating the start of block. The number of iterations N and the block length K are sampled on the rising edge of next clock. Once sob is sampled by the core, the rdy_nb signal is de-asserted indicating that the decoder cannot accept next block of data. From the next rising edge after the K and N values are sampled, the input data is read by the core and the decoding begins. Fig. 3 Turbo Decoder Input interface timing diagram Output Interface The output is the decoded bit stream d_out. The signal decoder_out_valid is asserted when the decoder is ready to output the decoded bit stream and from the next rising edge of the clock, the d_out is available. 4

Fig. 4 Turbo Decoder Output interface timing diagram Bit Error Rate (BER) Performance The Matlab simulation model used alongwith a test vector generator and a AWGN channel model.

5 Fig. 4 Turbo Decoder Output interface timing diagram Bit Error Rate (BER) Performance The Matlab simulation model used alongwith a test vector generator and a AWGN channel model. The output vectors from the IP core are validated to be consistent with the output from the simulation model used with the test bed for BER curve generation. The turbo decoder core performance for Rate 1/3 soft bits input, with AWGN channel for few block sizes is as shown in Fig. 5 below. Fig. 5 BER curve for 6 iterations for various block sizes Latency Calculation and Early Termination (ET) option The log likelihood ratios for a block of size K is computed in K clocks. From the instance, a block of size K being available in input buffer to the first Le output available K clocks are consumed. This is for one level of parallelism. The latency is approximately cut down by half for every level of parallelism 5

6 introduced (say 2,4,8). For a parallel option of 2, the latency becomes K/2 for the half iteration explained above. Early termination option is available to be enabled. This option significantly reduces the decoder latency based on the SNR of the input bits. The turbo decoder core performance with early termination (ET) option enabled for Rate 1/3 soft bits input, with AWGN channel for few block sizes is as shown in Fig. 6 below. Fig. 6 BER curve for various block sizes with ET option enabled Resource Usage The following table provides guide values for resource usage of the Turbo Decoder IP Block. The target FPGA device was taken as Xilinx 6vlx240tff1156 Number of Slice Registers 16841/ Number of Slice LUT s 25094/ The above resource numbers are for the decoder IP Core instance including the input dual buffer, control logic, interleaver and de-interleaver logic etc., The exact utilization of memory and the logic resources depends on the configuration such as the parallelism used, configuration for speed optimization and several other factors. The numbers are to be used as guidance values only. For further information please write to us. 6

7 The above numbers can vary based on minor modifications in design, the exact part chosen and the tools used. The numbers are to be used as guidance values only. References [1] 3GPP TS version Release 10 Ordering Information Part # LW RI 1002 Other Related Cores Core/ Technology LTE/ LTE A WCDMA CC Encoder Available Available CTC Encoder Available Available Rate Matching Available Available soon Viterbi Decoder Available Available Turbo Decoder Available Available soon Scrambling, Modulation and Soft-slicing blocks will be available soon to enable our customers to have the complete bit processing block. For further information, enquiry or a demo, send a request to ipbiz.rtl@lekhawireless.com The Above IP can be licensed either as a completely integrated core or separately as Turbo, Convolution and rate matching blocks for LTE/ LTE A/ WCDMA technologies. Lekha also offers customization services for these IP cores, and can also support in FPGA prototyping, board design, system software development and integration. 7

The Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS V Release 10[1].

Lekha IP 3GPP LTE FEC Encoder IP Core V1.0 The Lekha 3GPP LTE FEC IP Core meets 3GPP LTE specification 3GPP TS 36.212 V 10.5.0 Release 10[1]. 1.0 Introduction The Lekha IP 3GPP LTE FEC Encoder IP Core