David Merodio Codinachs Filomena Decuzzi (Until Dec 2010), Javier Galindo Guarch TEC EDM

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1 David Merodio Codinachs Filomena Decuzzi (Until Dec 2010), Javier Galindo Guarch TEC EDM

2 Radiation hardness assessment and optimization tools: SUSANNA and JONATHAN ALREADY PRESENTED in the previous Atmel User s Group edition Expected and real capacity compared to Actel Tools: let s get closer to the silicon capabilities Placement impact on the performance Update from the previous edition First ATF280 in house design experiences

3 Placement impact on the performance PURPLE VPR ATF280F first In house design experiences In house evaluation of ATMEL FPGA Development Kit and Tools through small designs: new Atmel FPGA user learning curve Study the suitability of ESA IP Cores within the ATMEL ATF280 FPGA and its Tools (HurriCANe)

4 Placement impact on the performance PURPLE VPR ATF280F first In house design experiences In house evaluation of ATMEL FPGA Development Kit and Tools through small designs: new Atmel FPGA user learning curve Study the suitability of ESA IP Cores within the ATMEL ATF280 FPGA and its Tools (HurriCANe)

5 Router can only work as good as the place Figaro doesn t always achieve fulfilling solution Feedback from industries 5

6 Atmel Figaro tool supports manual placement: to improve timing on a path to squeeze a design that automatic placement can t make it fit in the device to resolving contention to make easier to route a net to reserve a particular area for an instance Only optimize placement manually if you are familiar with the device architecture and know how your design should us it. Figaro Help 6

7 Atmel s P&R Manual Placement Gain Time Max frequency Device utilization Max frequency Device utilization Frequency Device utilization [h] Memory elaboration 7.1 MHz 11.4% 10.4 MHz 12% 32% 5% 8h 10.5 MHz 11.8% +2h Scruble string 10.9 MHz 6% 15 MHz 8.5% 27% 29% 6h 1 player game 11.5 MHz 15% 15.3 MHz 20.3% 25% 26% 5h memory 7 elaboration design

8 Placement engine Front-end Placement engine Back-end Netlist description Logic position design.fgd 8 design_replace.fgd

9 Versatile Place Route FPGA placement and routing tool; Copyright University of Toronto Timing driven placement Optimization engine based on simulated annealing It claims (seems suitable for Atmel FPGA arch.): VPR was written to allow circuits to be placed and routed on a wide variety of FPGAs to facilitate comparisons of different architectures. It takes two input files, a netlist describing the circuit to be placed and routed, and a description of the FPGA architecture. 9

10 VPR main placement factors: 10 Timing: The closer the logic is placed the better timing will be achieved. Main reason to drive the placement towards keeping the logic as close as possible. Wiring (including Congestion factor) The logic has to be able to be routed given the available resources. Main reason to drive the placement towards keeping the logic enough apart in order to be able to be routed. Timing Logic FPGA Congestion 10

11 The Atmel Architecture is finally not well suited for VPR: 11 Intra cluster routing Absence of fully connected cluster in Atmel architecture Inter cluster routing Absence of switch box in Atmel architecture Direct connection Partially supported by VPR VPR as is produces a very dense placement non routable The congestion factor in the cost function used in VPR has been modified (Annex for details) 11

12 Net IO instance Core Cell netlist instance for routing Macros with RAM Register Buses Local Express

13 VPR VPR_congestion final 714 route contention final 332 route contention 13

14 Net IO instance Core Cell netlist instance for routing Macros with RAM Register Buses Local Express % respect Figaro 20% 20% 29% 18% 11% final 119 route contention 14

15 VPR usage is not as generic as initially estimated adaptation to Atmel architecture not trivial VPR improvement with partial routability estimation PURPLE is finished and enables the use of any Placement end Routing Engines Close collaboration with Atmel to keep compatibility with future versions FUTURE: Post doc (NPI) is planned to continue on the issue 15 15

16 Placement impact on the performance PURPLE VPR ATF280F first In house design experiences In house evaluation of ATMEL FPGA Development Kit and Tools through small designs: new Atmel FPGA user learning curve Study the suitability of ESA IP Cores within the ATMEL ATF280 FPGA and its Tools (HurriCANe)

17 First time Atmel FPGA user experience: Study the suitability of ESA IP Cores within the ATMEL ATF280 FPGA and its Tools. In house evaluation of ATMEL FPGA Development Kit and Tools Comparison of the results with other technologies.

18 1. Review of ATMEL Architecture and General ATF280 Features Expertise and work already done by ESA with ATMEL FPGAs 2. Review of work already done with ATF280 Analysis of developed designs Tricks, bugs and problems found which are not well explained in ATMEL documentation. At first glance, promising device ESA UNCLASSIFIED For Official Use

19 3. Understanding of ATMEL Tool flow Non trivial; Compilation of different applications. Lack of good documentation and EXAMPLES!!! (Available under request) In house Know How; thanks to Mrs F. Decuzzi 4. Implementation of test designs Start with simple designs to become familiar with tool flow Use of CAN (Data Link Layer); new and interesting IP core Future; CANOpen, Space Wire, Small processor or LEON 5. Results analysis and comparison with other technologies Validation and verification of the designs Problem analysis and results Comparison and conclusions ESA UNCLASSIFIED For Official Use

20 Initial Prototype ATF280 Silicon Revision F Compact PCI mother board EEPROM, SDRAM, SRAM memories AT17LV040 configuration memory is used instead of AT69170E. Configurable clock generator LEDs, buttons and a LCD display Serial RS232 and LVDS drivers Final Development Kit ATF280 Silicon Revision F Compact PCI mother board EEPROM, SRAM memories 4 x AT17LV010 configuration memory is used instead of AT69170E Configurable clock generator and external clock inputs LEDs and buttons Serial RS232 and LVDS drivers

21 Test of simple designs to become familiar with the tools. Simple combinational circuits Up and Down Counters (annex) Frequency Dividers Hard Macros with dummy State Machines Simple UART access to On Chip RAM

22 Synthesis Technology comparisons purpose: Check consistency of the results obtained with the Atmel design flow and other FPGA technologies The purpose is not to have a full benchmark Important note: The technologies compared belong to different technology nodes and some (Altera Cyclone 2 and Xilinx Virtex 4) are commercial Altera Cyclone: 90 nm TSCM, commercial Xilinx Virtex 4: 90 nm UMC, commercial Microsemi RTAX : 150 nm, rad tolerant

23 Frequency Divider; Technology Comparison; AREA ATMEL ATF280 ALTERA Cyclone II ACTEL RTAX1000 XILINX Virtex 4 FIGARO Report Correlation among technologies

24 Frequency Divider; Technology Comparison: Timing ATMEL ATF280 ALTERA Cyclone II ACTEL RTAX1000 XILINX Virtex 4 FIGARO Report ATMEL Shows slower performance

25 Hierarchy Flattening Mandatory. Problems routing different clock domains in same die area (congestion of the clock resources) Using the 8 DKit LEDs with different clock domains almost impossible. Solution: use not registered outputs not always feasible though

26 Placement impact on the performance PURPLE VPR ATF280F first In house design experiences In house evaluation of ATMEL FPGA Development Kit and Tools through small designs: new Atmel FPGA user learning curve Study the suitability of ESA IP Cores within the ATMEL ATF280 FPGA and its Tools (HurriCANe)

27 HurryCANe ESA IP Core implementing the DATA LINK LAYER of BOSCH 2.0 A and B CAN standard. Well spread controller Includes an AMBA APB wrapper, not used in these test.

28 ESA HurryCANe IP Core Two test setups used: Single CAN Node (SCN): Simple CAN node which sends packets when board push buttons are pressed and switch on and off LEDs depending on the received packet. CAN UART Bridge (CUB): Bridge with a CAN interface and a Serial UART interface. LCD to monitor traffic. Enables more extensive testing. More details in the Annex

29 Physical Layer Driver for CAN Voltage levels in protoboard. Used 65HVD251 from TI (CAN V levels, not RS485) Up to 1Mbp Vector CANoe software package to simulate CAN network nodes and monitor traffic. PCMCIA Card with optocoupled physical layer drivers.

30 Design fits and works in ATF280 (1 Mbps) Very Low design frequency due to long combinatorial paths of the IP core (Specially expensive in timing for ATMEL FPGAs). Not functional problem but detailed analysis needed. IP core works without big issues

31 Bridge Functionality: HurryCANe ESA IP Core implementing the DATA LINK LATER of BOSCH 2.0 A and B CAN standard interfacing OpenCores simple serial UART 96008N1. Dummy LCD display controlled with state machine to monitor traffic.

32 Equivalent to the Single Node including: Serial port on computer with Putty as terminal Packets can be send from the PC through the Serial Interface, CAN, and back to the PC. Also in the opposite direction. Preliminary tests successfully performed Design validated and verified

33 ATMEL ATF280 ALTERA Cyclone II ACTEL RTAX1000 XILINX Virtex 4 FIGARO Report (FANOUT = 100)

34 FANOUT impact: not too large for this design ATMEL ATF280 ALTERA Cyclone II FANOUT = 100 FANOUT = 30 ACTEL RTAX1000 XILINX Virtex 4 FANOUT = 100 FIGARO Report FANOUT = 30

35 FIGARO Report Where are the FGEN2 in the precision report?? (in the lpms?) PRECISION Report

36 Delay in the nets: very high for ATF280 (for many 4 ns) ATMEL ATF280 XILINX Virtex4

37 Atmel tools: not trivial tool flow self learning the software will not give the same results as experimented users could get, help needed. Lack of application examples and some documentation. Only self test bit stream with the FPGA, need to ask for samples. Lack of centralized document with tips and tricks for new users. Fast and good support from ATMEL RadHard Hotline; efficient and fast solutions answers and help.

38 HurriCANe ESA IP has been successfully implemented, verified and validated on the ATF280F FPGA. Full validation pending Potential optimization of the internal long combinatorial paths seems feasible (future investigation if required) AFT280 timing ( performance GAP ) with other FPGAs Ongoing internal work Space Programmer drivers of 64 bits needed

39 Final conclusions from a new Atmel FPGA user: Atmel on the good path. ATF280 still valid for many designs. Improvements on the tools would give more usability. More work need to be done. Atmel Users Group Forum is a very good information source. It needs to be stimulated.

40 QUESTIONS?

41

42 VPR routing architecture Atmel routing architecture 42

43 VPR switch box Atmel direct connection 43

44 Cost Timing cost Wiring cost 44 previous timing cost number of nets in the circuit previous wiring cost compensation factor constant [0,1] horizontal span weight critical connection vertical span [1,max(default 8)]

45 Yue Zhuo, Hao Li and Saraju P. Mohanty A congestion driven placement algorithm for fpga synthesis,in proceeding of the International Conference on Field Programmable Logic and Application,2006 Always 1 When close to 1 the placement is balanced When greater than 1 the placement is congested number of bouding boxes covering small positive integer horizontal size chip vertical size chip 45

46 Down Counter; AREA Precision Vs IDS ATMEL IDS MENTOR PRECISION Similar Results

47 Down Counter; TIMING Precision Vs IDS MENTOR PRECISION ATMEL IDS Not So Accurate Correlation

48 Down Counter; AREA and TIMING VHDL Vs IDS Hard Macros VHDL HARD MACROS HardMacros Perform much better

49 Only Data Link Layer implemented controlled with dummy state machines. Computer emulated CAN network to send packets to the node and monitor packet received from the node. LEDs and push buttons to control node. 1Mbps CAN link speed. Internal or external PCB clock. Synthesis performed with Precision RTL 2010a U2. Place & route performed with Figaro IDS ATMEL Development Kit used.

50 Design fits and works in ATF280 Most complicated step; learning of Vector CANoe software package. Powerful tool but time consuming to be learnt. Internal and external clock tested up to 20 Mhz. No need for higher speeds, max CAN speed is 1Mbps, achievable with less than 20 Mhz. Extremely low design frequency shows coding problems of the IP core with ATMEL devices. Not functional problem but detailed analysis needed. IP core works without big issues

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