Accelerating MIPI Interface Development and Validation

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1 Accelerating MIPI Interface Development and Validation 1

2 Mobile Industry Processor Interface 2

3 The Standard for Mobile 3

4 The Standard for Mobile & Mobile Influenced Industry 4

5 Influenced by Highly Accomplished Ecosystem Automotive Internet Appliances Medical 5

6 Origins: Modular PHY and Protocol Specifications Display (Protocol) Higher Level Protocol Camera (Protocol) Physical Medium RF (Protocol) D-PHY 6

7 Link Rate (Gbps) Flexibility: Variable Data Rate Unlike Other Standards Evolution of Image Sensor Capabilities C-PHY 3 x 2.5 Gsps D-PHY 4 x 4.5 Gbps D-PHY 4 x 2.5 Gbps D-PHY 4 x 1.5 Gbps 10MP 20MP 30MP 40MP 50MP Sensor Resolution Source: MIPI Alliance 7

8 Key Takeaways Modular construction of protocol and physical layers Any rate operation Challenge and Opportunity! 8

9 Rapid PHY Evolution (High Speed Links) Three different high-speed PHYs supporting up to 7 protocols (including non-mipi) M-PHY V0.80 M-PHY V1.00 M-PHY V2.00 D-PHY V1.10 M-PHY V3.00 M-PHY V3.10 D-PHY V1.20 C-PHY V1.00 M-PHY V4.00 D-PHY V2.00 C-PHY V1.10 M-PHY V4.10 D-PHY V2.10 C-PHY V1.20 Chartered D-PHY V0.65 D-PHY V0.90 D-PHY V0.92 D-PHY V

10 Unified Theme: Low Power, Burst-Mode Operation a Preparation for HS Data Start of HS HS Data (Packet Transmission) End of HS HS Data Low Power State (very long duration) Low Power State (very long duration) LP state is included to conserve power Different PHY layers define the transmission states differently 10

11 D-PHY is Source Synchronous CLK DATA D Q LP consists of LVCMOS single-ended signals HS prep. consists of LP11-LP01-LP00 transition followed by differential zero signal Start of HS data is signified by SOT word HS data is source synchronous with CLK End of HS data is signified by constant value followed by LP11 LP is singleended again 11

12 C-PHY is Three-Phase Encoded (Embedded Clock) See Our Pres at LP consists of LVCMOS single-ended signals HS prep. consists of LP111-LP011-LP000 transition followed by constant 3,3,3,.. sequence Start of HS data is signified by SYNC word HS data is threephase specially encoded (no clock) End of HS data is signified by constant 4,4,4 sequence LP is singleended again 12

13 M-PHY is Differential with Embedded Clock D Q DATA CDR LP consists of differential pulse-widthmodulated stream (very slow) HS prep. consists of transition from diff-0 to diff-1 followed by high-frequency SYNC pattern Start of HS data is signified by MK0 word HS data is differential with CDR (no clock lane) End of HS data is signified by MKn word LP is differential low frequency again 13

14 HS Data: Packet Based Transmissions Header Payload Footer Build packet as list of bytes Bytes 0x 24 0x 80 0x 07 0x 03 0x 00 0x 01 0x 02 0x 03 0x 04 0x 05 0x B5 0x C1 a Preparation for HS Data Start of HS HS Data (Packet Transmission) End of HS HS Data Low Power State (very long duration) Low Power State (very long duration) 14

15 Visualizing Transmissions Camera & Display RGB = 0x(00, 00, FF) RGB = 0x(FF, FF, FF) RGB = 0x(FF, 00, 00) 0xFF 0x00 0x00 0xFF 0xFF 0xFF 0x00 0x00 0xFF HEADER CRC 15

16 Visualizing Transmissions Camera & Display (C-PHY) RGB = 0x(00, 00, FF) RGB = 0x(FF, FF, FF) RGB = 0x(FF, 00, 00) 0xFF 0x00 0x00 0xFF 0xFF 0xFF 0x00 0x00 0xFF Always Toggling! HEADER 0x00 0xFF 0x00 0xFF 0x00 0xFF 0x00 0xFF 0xFF 0xFF 0xFF CRC

17 Video Streaming CSI-2 On D-PHY / C-PHY LP11 Stop State D-PHY Held in LP11 During Frame Blanking One Packet for One Line (after FS) One Packet for One Line One Packet for One Line Time 17

18 Key Takeaways Display and camera systems leverage packet-based transmission technology through MIPI standards Signal transmission mechanisms vary slightly at the physical layer, but they always strive for low power dissipation 18

19 A Complete Specifications Framework 19

20 In Other Words Ultra Low Power IoT Always-On Multi-Touch Sensor High Performance ADAS Video Storage RF MIPI 20

21 Practical Realities Display Display ecosystem is heavily invested in MIPI DSI/DSI-2 protocol Pervasive presence of D-PHY 1.1, 1.2 Strong growth in C-PHY 1.1 due to reduction in number of wires Trends: Higher speeds! Scrambling 30 bpp color depth VESA v1.2 compression 21

22 Practical Realities Camera D-PHY protocol is simple, and it is here to stay for image sensors: User-facing camera Medical imaging Infrared Result of the test can be a photo! C-PHY addresses new trends: High performance imaging (SLR quality) Amenable to vision technologies (LRTE, ROI, fast BTA) 22

23 Practical Realities Storage M-PHY protocol complexity limits its use to more advanced interfaces Flash memory High-speed chip to chip or networking Source: Samsung 23

24 Design & Validation Challenges 24

25 Unidirectional Links Unidirectional Link HS DP/DN (Differential) D Q LP DP LP DN LP DP LP DN HS CP/CN (Differential) LP CP LP CN LP CP LP CN 25

26 Feedback Through Software (No Loopback) MIPI Input Port Device Under Test Only HW connection to APU Under Test is through MIPI Pattern Generator 26

27 Feedback Through Software (No Loopback) 4 Pass/Fail Checking Stimulus Design 1 3 Data detection Traffic Generation 2 27

28 Pattern Generator Waveforms Single-Ended LP Waveforms High-Fidelity Differential Waveforms Deterministic Alignment 28

29 HS Signal Calibrated Using Conventional Methods 29

30 Two Categories of Test Requirements Global Timers Test Stress components related to state transitions from Low Power to High Speed Receiver Eye Test Stress components related to the High Speed receiver itself HS-ZERO SoT HS-TRAIL LP11 LP01 LP Inverse of last bit LP11 (0xB8) (0x24) (0xC1) 30

31 Example CTS Test HS-ZERO SoT False Leader False Leader 31

32 Results in Need for Protocol Level Patterns! Input picture file from Windows File System Regardless of test pattern, all frame parameters are configurable Sample photo being transmitted 32

33 While Controlling Analog Parameters Global timing parameters are included in units of UI and nanoseconds. SOT bits need to be configurable dphypattern component shown here as a color bar generator. Frame height & width are included as well as selection of Pixel format (CSI-RGB888 shown) Standard test color bar included by default Regardless of test pattern, all frame parameters need to be configurable 33

34 Signal Calibration Very Similar to Other SerDes Voltage Amplitude Common Voltage Jitter Injection Timing Stress 34

35 Real World Tips When things really need to get done 35

36 Avoid Long Cables LP signals are unterminated Reflections LP to HS transition includes switching termination Charge injection, ringing 36

37 Passive Probes Do not Always Work Well Loading the HS lines means that load seen by Tx is no longer 50 Ohm 37

38 Beware of the Discontinuities 38

39 Beyond Mobile Beyond 1 Lane Beyond 1 Protocol 39

40 Key Takeaways Limit cable lengths Avoid probing with passive signal taps Ensure all-lane testing, but avoid discontinuities 40

41 Design Validation Receiver Characterization Production Test Introspect s Complete Tool Coverage FPGA-based design validation At-speed system-level testing Full-link receiver stress generation Automated receiver conformance At-speed final test on ATE Functional system-level test on ATE 41

42 Learn More! October 27, 3:45pm C-PHY and How it Enables Next Generation Display and Camera Implementations October 31, 11:45 Practical Experiences in MIPI D-PHY & C-PHY Receiver Testing 42

43 Thank You! 43

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