Timers and Pulse Accumulator

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Allen Clifton Bell
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1 7 7.1 Objectives: Tiva is equipped with six General Purpose Timer Modules named TIMERn. Additionally, each TIMERn consists of two 16 bit timers (A and B). Most GPIO pins can be assigned a TIMERn as an alternate function allowing the GPIO pin to act as a port for the TIMER. This lab will focus on using the TIMER0. While doing this lab, you will learn The key components of the GPTM system. How to program the input capture features of the GPTM system. How to program the output compare features of the GPTM system. How to program the Edge Count features of the GPTM system. 7.2 Related material to read: Text, Chapter 15, pp The module described in the text is NOT the same as on our processor, but it is similar and the concepts are the same. TM4C123GH6PM Data Sheet, Chapter 11, pp Very technical, very detailed, and very accurate, but not focused on accomplishing user tasks. Embedded Systems: Real Time Interfacing to ARM Cortex-M Microcontrollers, Jonathan Valvano, Chapter 6, pp This chapter explains exactly our GPTM, and shows how measurements are made using this module. This book is on reserve in Morgan Library

2 7.3 The Tivatimer module (TIMERn): Each timer module, TIMERn, of Tiva performs three main functions, viz., Input Capture, Output Compare and Edge Count. The input capture feature measures the characteristics of a periodic input signal such as period, duty cycle, and frequency of the signal. The output compare feature allows the generation of an output signal to user specifications. The edge count feature is used to count pulses (external events) on a line connected to Tiva. Each TIMERn module (TIMER0, 1, 2, etc) consists of two individual timers A and B. Each timer (A or B) is 16 bits and can be used individually, or configured to concatenate timers A and B to form a 32 bit timer. Figure 7.1 shows the base addresses for each 16/32 bit timer module. Figure 7.1: TIMER base addresses Each TIMER can be physically accessed through one of the GPIO pins, in which case, the GPIO ports will have to be configured accordingly. Each TIMER has already been assigned a GPIO pin, but you will have to enable its function via software using the GPIOAFSEL and GPIOPCTL registers. Figure 7.2 shows each TIMERn and its associated pins. Each of these channels is software configurable to be either, One-Shot, Periodic, Edge Count, Edge Time, or PWM. 7.4 One Shot / Periodic mode: In One Shot / Periodic mode, the timer will start counting up to a specified value, or down from a specified value to 0x00. Counting starts once the timer is enabled using the TnEN bit inside the Control register (GPTMCTL). If configured to count up, the timer starts at 0x00 and counts up to the value stored in the Timer n Interval Load Register (GPTMTnILR). When the value in GPTMTnILR is reached, a Time-Out event is triggered which sets a flag in the Raw Interrupt Status register (GPTMRIS). Then, the timer starts over its count at 0x00 if in Periodic mode. If the timer is set for One Shot, the timer is disabled after the value in the Interval Load Register is reached and the interrupt flag is set. If the timer is configured to count down, the actions are similar to counting up, but instead the timer starts at the value stored in the Interval Load Register and counts down. A timeout event is triggered when 0x00 is reached. In this mode, the timer can also be configured to set a flag in the GPTMRIS register when the current count matches the value loaded into the GPTMTnMATCHR register. In each case the interrupt flag will need to be cleared after each timeout event using the appropriate bit inside the Interrupt Clear Register (GPTMICR)

3 Figure 7.2: TIMER pin assignments 7.5 Edge Time / Edge Count mode: In Edge Time mode the timer starts counting once the timer is enabled, but stores the current count into the GPTMTnR register when an edge of a pulse signal is detected. The timer can be configured to detect a rising edge, falling edge, or either. When the selected edge is detected, a flag in the Raw Interrupt Status register (GPTMRIS) and will need to be cleared using the Interrupt Clear Register (GPTMICR). Edge Count mode is used to count the number of edge types (rising, falling, both) detected, and stores them in the GPTMTnR register. When the count equals the value stared in the GPTMTnMATCHR register, a Capture Mode Match interrupt is triggered. 7.6 Timer Setup: Similar to the GPIO, in order to use the timer peripheral, we must first power it up by staring its clock using the General-Purpose Timer Run Mode Clock Gating Control - 3 -

Each timer A and B can be enabled / disabled by setting or clearing the TnEN bit of the Control register (GPTMCTL, offset 0x00C).

4 (RCGCTIMER) at address 0x400F.E604. Setting bits 5:0 enables the associated TIMERn module. Figure 7.2: General-Purpose Timer Run Mode Clock Gating Control (RCGCTIMER) The timer must first be disabled before configuring the timer! Each timer A and B can be enabled / disabled by setting or clearing the TnEN bit of the Control register (GPTMCTL, offset 0x00C). Note the difference between enable bits for timer A and B (TAEN, TBEN) inside each TIMERn. The TnSTALL bit allows the timer count to freeze while in debugging mode. Setting this bit allows more efficient debugging of your code. Figure 7.3: GPTM Control register (GPTMCTL)

Next set the Configuration register (GPTMCFG, offset 0x000) to specify the 16 bit timer by setting bits 2:0 to 0x4. With this setting, Timer A and B will be used individually as two 16 bit timers.

Since we are using Timer0A after setting the Timer0 CFG register to 16 bit, we need to select which mode Timer A will be running in.

5 Next set the Configuration register (GPTMCFG, offset 0x000) to specify the 16 bit timer by setting bits 2:0 to 0x4. With this setting, Timer A and B will be used individually as two 16 bit timers. For this lab we will use Timer0A. Note that this register is the base address for the module. Figure 7.4: GPTM Configuration register (GPTMCFG). Since we are using Timer0A after setting the Timer0 CFG register to 16 bit, we need to select which mode Timer A will be running in. The mode is specified using the TAMR bits (bits 1:0) of the Timer A Mode register (GPTMTAMR, offset 0x004). TAMR settings: 0x00 0x01 0x02 0x03 Reserved One Shot Periodic Capture Edge Time and Edge Count modes can be thought of as sub modes of Capture. If either Edge Time or Edge Count modes are desired, TAMR must be set to 0x03 for Capture. Then the Capture Mode bit (TACMR, bit 2) must be set to to specify Edge Time mode or cleared to specify Edge Count mode. The Timer Direction bit (TACDIR, bit 4) selects whether the timer counts up (set bit) or counts down (clear bit). Figure 7.5: GPTM Timer A mode register (GPTMTAMR)

If using One-Shot or Periodic, load the 16 bit value that the timer will count up to, or down from, into the GPTM Timer A Interval Load register (GPTMTAILR, offset 0x028). Figure 7.

6 If using One-Shot or Periodic, load the 16 bit value that the timer will count up to, or down from, into the GPTM Timer A Interval Load register (GPTMTAILR, offset 0x028). Figure 7.6: GPTM Interval Load Register (GPTMTAILR). If using Edge Count Mode, or using a Match value in One-Shot or Periodic mode, load the match value into the GPTM Timer A Match register (GPTMTAMATCHR, offset 0x030). Figure 7.7: GPTM Timer A Match Register (GPTMTAMATCHR). In order to receive a flag in the RIS register when a particular event happens, the appropriate interrupt will need to be set in the GPTM Interrupt Mask register (GPTMIMR, offset 0x018). The TnTOIM bit enables the Time-Out Interrupt Mask, which is used in One-Shot or Periodic modes. The CnMIM bit enables the Capture Mode Match Interrupt Mask, which is used when Capture mode with Edge Count mode enabled. The CnEIM bit enables the Capture Mode Event Interrupt Mask, which is used when Capture Edge Time mode is enabled. The RTCIM bit enables the Real Time Clock Interrupt Mask, which is used in Real Time Clock mode. The TnMIM bit enables the Match Interrupt Mask, which sets a flag in One-Shot or Periodic modes when using the GPTMTAMATCHR register. Figure 7.8: GPTM Interrupt Mask Register (GPTMIMR)

Figure 7.9: GPTM Raw Interrupt Status register (GPTMRIS). With the Timer using the bus clock of 16 Mhz, each clock cycle (each increment of the Timer) is 62.5ns long.

If a larger delay is needed, the timer has the ability to increase the time between each increment.

7 Figure 7.9: GPTM Raw Interrupt Status register (GPTMRIS). With the Timer using the bus clock of 16 Mhz, each clock cycle (each increment of the Timer) is 62.5ns long. When the 16/32 bit Timer is in 16-bit mode, loading TnILR with a maximum value of 0xFFFF would result in a 4.096ms delay (65536*62.5*10-9 ). If a larger delay is needed, the timer has the ability to increase the time between each increment. When the timer is used individually, the GPTM Timer n Prescale register (GPTMTnPR, offset 0x038 for A, 0x03C for B) becomes available. Loading a value into the Prescale register makes the timer first count down the Prescale register to 0x00 before incrementing the timer count. For example, if the Prescale register had a value of 0x03, the timer would use 3 clock cycles to count down to 0x00, then a 4 th to increment the counter. This effectively increased your delay by a factor of 4. When the timer is in 16-bit mode the GPTMTnPR register is 8- bits long, so the delay can be increased by a maximum factor of 256. Figure 7.10 shows prescale values and the equivalent maximum delay. Figure 7.10: Max delay time and equivalent prescale value. Figure 7.11: GPTM Timer n Prescale register

8 The following program shows how to use Timer0A in periodic mode to obtain a 10-second delay. ;16/32 bit Timer Registers TIMER0_CFG EQU 0x TIMER0_TAMR EQU 0x TIMER0_CTL EQU 0x C TIMER0_IMR EQU 0x TIMER0_RIS EQU 0x C TIMER0_ICR EQU 0x TIMER0_TAILR EQU 0x TIMER0_TAMATCHR EQU 0x TIMER0_TAPR EQU 0x TIMER0_TAPMR EQU 0x SYSCTL_RCGCTIMER EQU 0x400FE604 ; 16/32 Gate Control EXPORT main ;*************************************************************** ; Program Area ;*************************************************************** ;LABEL DIRECTIVE VALUE COMMENT main MOV R0, #ms LDR R1, =count STRB R0, [R1] LDR R1, =SYSCTL_RCGCTIMER ; Start Timer clock ORR R2, R2, #0x01 ; start timer 0 ; allow clock to settle LDR R1, =TIMER0_CTL ; disable timer during setup BIC R2, R2, #0x01 ; clear bit0 to disable TimerA LDR R1, =TIMER0_CFG MOV R2, #0x04 ; 16 bit mode LDR R1, =TIMER0_TAMR MOV R2, #0x02 ; periodic, count down LDR R1, =TIMER0_TAILR ; load time-out clocks into TAIL MOV R0, #16000 ; 1ms delay LDR R1, =TIMER0_TAPR ; divide clock by 100 MOV R2, #99 LDR R1, =TIMER0_IMR MOV R2, #0x01 ; enable Time Out Interrupt ; LDR R1, =TIMER0_CTL ; enable timer - 8 -

9 ORR R2, R2, #0x03 ; set bit0 to enable ; and bit1 to stall on debug pole LDR R1,=TIMER0_RIS ; check interrupt flag LDR R2,[R1] CMP R2,#0x01 BNE pole LDR R1, =TIMER0_ICR ; clear interrupt flag MOV R0, #0x01 LDR R1, =count ; check/reduce count LDRB R0, [R1] SUBS R0, R0, #1 STRB R0, [R1] BNE pole LDR R1, =TIMER0_CTL ; stop timer BIC R2, R2, #0x01 done B done ;*************************************************************** ; Data Area ;*************************************************************** ;LABEL DIRECTIVE VALUE COMMENT AREA DATA, READWRITE ALIGN ms EQU 100 count SPACE 1 ALIGN ; END ; Figure 7.12: Program to generate a 10-second delay using Periodic mode

10 7.7 Procedure: 1. Before lab, draw a flowchart for the 3 rd part of this procedure, create two programs that include code in Figures 7.12 and 7.13, run them and test if they are working properly. Describe in writing how these codes are working. How is the delay of 10 seconds created using initial 1ms interrupt setup? Note the changes in TIMER0A initialization between poling and interrupt methods in two programs. Understanding two codes will be very helpful for the second part of Procedures. Show prelab work to your TA at the beginning of lab. 2. Change the program from Maskable Interrupts lab (digital alarm clock) to work with General Purpose Timer Module in Periodic mode. You need to exchange routines that are specific to System Timer (SysTick). Copy the program you have created in previous lab experiment, replace systick_ini by routine that initializes TIMER0A and exchange Interrupt Service Routine (ISR) to service the interrupt created by TIMER0A (i.e. create appropriate Timer0A_Handler). No change is needed for setme, cdisp, almon, led_ini and clock routines. Note that routine initializing TIMER0A needs to enable 1s interrupt in order for digital alarm clock to work properly. 3. Write a program that uses the Edge Time feature of the TIMER to find the duty cycle, period and frequency of a periodic pulse train. For an input signal, you have two choices: a. Connect the function generator signal to one of the pins of Timer0 and configure the corresponding GPIO as an input channel. You may refer Lecture 14 for an example of how to set this up. or b. Using the interrupt based pulse generator shown in Figure 7.13, create a pulse train on a GPIO pin of your choice. Your program should set the R0 register to the number of 1 µsecond high counts and the R1 register to the number of 1 µsecond low counts, For a total period of R0+R1 µseconds. Feel free to modify the subroutine PGstart or ISR PGISR to achieve other TIMER goals you might have. Connect the output pin of the PulseGen to your chosen input capture pin. Write your program such that the period of any periodic pulse train can be measured, i.e., the measured period can be more than the 65,536 counts of the free-running counter. Display the measured characteristics of the signal on the terminal window. Show the working program to the TA. 4. For 40% extra credit, write a program that uses the Edge Count and Periodic modes of the TIMER to count the number of rising or falling edges in the pulse train from the function generator in 10 seconds. Configure one of the channels as an output channel and connect the LED circuit to its output. At time, t = 0, the LED should be off and the Edge Count system should be enabled to count the rising or falling edges in the pulse train from the function generator. After time t = 10 sec., the LED should turn on and the pulse accumulator should stop counting the number of specified edges. Display the counter value on the terminal window at the end of the program. Show the working program to the TA

11 7.8 Questions: 1. Give at least 2 applications each of the Edge Time, Edge Count, and Periodic modes of the TIMER. 2. Is it possible to generate a square wave (50% duty cycle) of period 10 hours using the Periodic mode of the 16 bit TIMER If yes, explain how and if not, explain why not. You do not need to write a program or flow chart to justify your answer. 7.9 Lab report: For the lab write-up, include 1. Your flowcharts and programs that you wrote before the lab. 2. A copy of your working.s files. 3. A brief discussion of the objectives of the lab and the procedures performed in the lab. 4. Answers to any questions in the discussion, procedure, or question sections of the lab

12 ; Routine for creating a pulse train using interrupts ; This uses Channel 0, and a 1MHz Timer Clock ; Be sure to us the Startup.s file ; Use Timer0A to create square wave pulses on PF2 ;Nested Vector Interrupt Controller registers NVIC_EN0_INT19 EQU 0x ; Interrupt 19 enable NVIC_EN0 EQU 0xE000E100 ; IRQ 0 to 31 Set Enable Register NVIC_PRI4 EQU 0xE000E410 ; IRQ 16 to 19 Priority Register ; 16/32 Timer Registers TIMER0_CFG EQU 0x TIMER0_TAMR EQU 0x TIMER0_CTL EQU 0x C TIMER0_IMR EQU 0x TIMER0_RIS EQU 0x C ; Timer Interrupt Status TIMER0_ICR EQU 0x ; Timer Interrupt Clear TIMER0_TAILR EQU 0x ; Timer interval TIMER0_TAPR EQU 0x ;GPIO Registers GPIO_PORTF_IM EQU 0x ; Interrupt Mask GPIO_PORTF_DIR EQU 0x ; Port Direction GPIO_PORTF_AFSEL EQU 0x ; Alt Function enable GPIO_PORTF_DEN EQU 0x C ; Digital Enable GPIO_PORTF_AMSEL EQU 0x ; Analog enable GPIO_PORTF_PCTL EQU 0x C ; Alternate Functions ;System Registers SYSCTL_RCGCGPIO EQU 0x400FE608 ; GPIO Gate Control SYSCTL_RCGCTIMER EQU 0x400FE604 ; GPTM Gate Control AREA THUMB EXPORT EXPORT timer, CODE, READONLY Timer0A_Init Timer0A_Handler Timer0A_Handler LDR R1, =TIMER0_ICR ; clear interrupt flag MOV R0, #0x01 LDR R1, =GPIO_PORTF_IM ; toggle output LDR R0, [R1] EOR R0, R0, #0x04 CMP R0,#0x04 ; check current state BEQ high LDR R1,=TIMER0_TAILR ; load low time LDR R2,=LowClocks LDR R0,[R2] STR R0,[R1] B doneisr high LDR R1,=TIMER0_TAILR ;load high time LDR R2,=HighClocks LDR R0,[R2]

13 STR R0,[R1] doneisr BX LR ; return Timer0A_Init LDR R2, =HighClocks ; store high clocks STR R0, [R2] LDR R2, =LowClocks ; store low clocks STR R1, [R2] LDR R1, =SYSCTL_RCGCGPIO ; start GPIO clock LDR R0, [R1] ORR R0, R0, #0x20 ; set bit 5 for port F ; allow clock to settle LDR R1, =GPIO_PORTF_DIR ; set direction of PF2 LDR R0, [R1] ORR R0, R0, #0x04 ; set bit2 for output LDR R1, =GPIO_PORTF_AFSEL ; regular port function LDR R0, [R1] BIC R0, R0, #0x04 LDR R1, =GPIO_PORTF_DEN ; make port digital LDR R0, [R1] ORR R0, R0, #0x04 LDR R1, =GPIO_PORTF_PCTL ; no alternate function LDR R0, [R1] BIC R0, R0, #0x00000F00 LDR R1, =GPIO_PORTF_AMSEL ; disable analog MOV R0, #0 LDR R1, =SYSCTL_RCGCTIMER ; Start Timer0 ORR R2, R2, #0x01 ; allow clock to settle LDR R1, =TIMER0_CTL ; disable timer during setup BIC R2, R2, #0x01 LDR R1, =TIMER0_CFG ; set 16 bit mode MOV R2, #0x04 LDR R1, =TIMER0_TAMR MOV R2, #0x02 ; set to periodic, count down LDR R1, =TIMER0_TAILR ; initialize match clocks LDR R2, =LowClocks LDR R0, [R2] LDR R1, =TIMER0_TAPR

14 MOV R2, #15 ; divide clock by 16 to ; get 1us clocks LDR R1, =TIMER0_IMR ; enable timeout interrupt MOV R2, #0x01 ; Configure interrupt priorities ; Timer0A is interrupt #19. ; Interrupts are handled by NVIC register PRI4. ; Interrupt 19 is controlled by bits 31:29 of PRI4. ; set NVIC interrupt 19 to priority 2 LDR R1, =NVIC_PRI4 AND R2, R2, #0x00FFFFFF ; clear interrupt 19 priority ORR R2, R2, #0x ; set interrupt 19 priority to 2 ; NVIC has to be enabled ; Interrupts 0-31 are handled by NVIC register EN0 ; Interrupt 19 is controlled by bit 19 ; enable interrupt 19 in NVIC LDR R1, =NVIC_EN0 MOVT R2, #0x08 ; set bit 19 to enable interrupt 19 ; Enable timer LDR R1, =TIMER0_CTL ORR R2, R2, #0x03 ; set bit0 to enable ; and bit 1 to stall on debug BX LR ; return ;*************************************************************** ; Data Area ;*************************************************************** ;LABEL DIRECTIVE VALUE COMMENT AREA DATA, READWRITE ALIGN HighClocks SPACE 4 LowClocks SPACE 4 ALIGN END Figure 7.13: Pulse Generator Subroutine and Interrupt Service Routine

Parallel I/O and Keyboard Scanning

Parallel I/O and Keyboard Scanning 4 4.1 Objectives: Microprocessors can monitor the outside world using input ports. They can also control it using output ports. The TM4C123G (Tiva) performs I/O using 6 ports. Computer keyboards are typically