Ultra Low Power (ULP) Challenge in System Architecture Level
|
|
- Priscilla Joseph
- 6 years ago
- Views:
Transcription
1 Ultra Low Power (ULP) Challenge in System Architecture Level - New architectures for 45-nm, 32-nm era ASP-DAC 2007 Designers' Forum 9D: Panel Discussion: Top 10 Design Issues Toshinori Sato (Kyushu U)
2 Global View Helps ULP Design Only to reduce power is not enough Variation tolerance, Soft error tolerance, and still High performance High-level consideration of power reduction is required Software optimization increases flexibilities of design Speculation can create new frontiers for optimizations Architecture selection can change characteristics of circuits Variation-aware (VA) ULP design examples
3 VA ULP Cache Architecture Process variations create ultra leaky transistors Fortunately, leakage current of an SRAM cell depends on the logic value stored Store leakage-safe values on entering into standby mode Power saving with negligible performance penalty 1 transistor out of 512K-bit SRAM Large Leak Mean Large Delay 5σ Vth =0.3V 100 tr. Threshold Voltage Delay is 2x of the average Leakage is 1,400x higher than average! 330x ±σ: 68.3% ±2σ: 95.4% ±3σ: 99.7% ±4σ: % 1.8x ±5σ: % M. Goudarzi: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation, Session , just NOW.
4 VA ULP Cache Architecture Process variations create ultra leaky transistors Fortunately, leakage current of an SRAM cell depends on the logic value stored Store leakage-safe values on entering into standby mode Power saving with negligible performance penalty way set-associative cache memory tag0 data0 tag1 data1 tag2 data2 tag3 data leaky cells 0-leaky cells M. Goudarzi: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation, Session , just NOW.
5 VA ULP Cache Architecture Process variations create ultra leaky transistors Fortunately, leakage current of an SRAM cell depends on the logic value stored Store leakage-safe values on entering into standby mode Power saving with negligible performance penalty 1500 Power saving (nw) ARM920 M32R Performance loss (ns) M. Goudarzi: A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation, Session , just NOW.
6 VA ULP Logic Architecture Typical-case design Optimizing not for worst cases but for typical cases Combination of two circuits Examples Main for power reduction Checker for correctness Razor FF Canary FF Potential of over 30% of energy reduction Ltd. soft error tolerance clk logic stage delayed clk Razor FF logic stage error comparator D. Ernst: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, MICRO, T. Sato: A Simple Flip-Flop Circuit for Typical-Case Designs for DFM, ISQED, 2007.
7 VA ULP Logic Architecture Typical-case design Optimizing not for worst cases but for typical cases Combination of two circuits Examples Main for power reduction Checker for correctness Razor FF Canary FF Potential of over 30% of energy reduction Ltd. soft error tolerance 40% 30% 20% 10% 0% clk logic stage clk delay Canary FF logic stage trigger comparator gzip vpr gcc parser vortex bzip2 D. Ernst: Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation, MICRO, T. Sato: A Simple Flip-Flop Circuit for Typical-Case Designs for DFM, ISQED, 2007.
8 VA ULP CMP Architecture Statistical characteristics of circuit delay As the number of critical paths increases, the mean delay increases and the standard deviation decreases CMP with simple CPU cores reduces critical path delay, and increases the number of critical paths is more variation-tolerant x M. Hashimoto: Increase in Delay Uncertainty by Performance Optimization, ISCAS, T. Sato: Architectures Study beyond Physical Limitations, NGArch Forum, July 2006.
OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions
OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 1 Introduction: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism
More informationCentip3De: A 64-Core, 3D Stacked, Near-Threshold System
1 1 1 Centip3De: A 64-Core, 3D Stacked, Near-Threshold System Ronald G. Dreslinski David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman
More informationNear-Threshold Computing: Reclaiming Moore s Law
1 Near-Threshold Computing: Reclaiming Moore s Law Dr. Ronald G. Dreslinski Research Fellow Ann Arbor 1 1 Motivation 1000000 Transistors (100,000's) 100000 10000 Power (W) Performance (GOPS) Efficiency (GOPS/W)
More information6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1
6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,
More informationUltra Low-Cost Defect Protection for Microprocessor Pipelines
Ultra Low-Cost Defect Protection for Microprocessor Pipelines Smitha Shyam Kypros Constantinides Sujay Phadke Valeria Bertacco Todd Austin Advanced Computer Architecture Lab University of Michigan Key
More informationCOMPARITIVE ANALYSIS OF SRAM CELL TOPOLOGIES AT 65nm TECHNOLOGY
COMPARITIVE ANALYSIS OF SRAM CELL TOPOLOGIES AT 65nm TECHNOLOGY Manish Verma 1, Shubham Yadav 2, Manish Kurre 3 1,2,3,Assistant professor, Department of Electrical Engineering, Kalinga University, Naya
More informationDesign of Low Power Wide Gates used in Register File and Tag Comparator
www..org 1 Design of Low Power Wide Gates used in Register File and Tag Comparator Isac Daimary 1, Mohammed Aneesh 2 1,2 Department of Electronics Engineering, Pondicherry University Pondicherry, 605014,
More informationChapter 8. Coping with Physical Failures, Soft Errors, and Reliability Issues. System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P.
Chapter 8 Coping with Physical Failures, Soft Errors, and Reliability Issues System-on-Chip EE141 Test Architectures Ch. 8 Physical Failures - P. 1 1 What is this chapter about? Gives an Overview of and
More informationCMP annual meeting, January 23 rd, 2014
J.P.Nozières, G.Prenat, B.Dieny and G.Di Pendina Spintec, UMR-8191, CEA-INAC/CNRS/UJF-Grenoble1/Grenoble-INP, Grenoble, France CMP annual meeting, January 23 rd, 2014 ReRAM V wr0 ~-0.9V V wr1 V ~0.9V@5ns
More informationEmbedded SRAM Technology for High-End Processors
Embedded SRAM Technology for High-End Processors Hiroshi Nakadai Gaku Ito Toshiyuki Uetake Fujitsu is the only company in Japan that develops its own processors for use in server products that support
More informationA 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and V MIN Tracking Canary Sensors
A 256kb 6T Self-Tuning SRAM with Extended 0.38V-1.2V Operating Range using Multiple Read/Write Assists and V MIN Tracking Canary Sensors *Arijit Banerjee, *Ningxi Liu, *Harsh N. Patel, *Benton H. Calhoun
More informationPushPull: Short Path Padding for Timing Error Resilient Circuits YU-MING YANG IRIS HUI-RU JIANG SUNG-TING HO. IRIS Lab National Chiao Tung University
PushPull: Short Path Padding for Timing Error Resilient Circuits YU-MING YANG IRIS HUI-RU JIANG SUNG-TING HO IRIS Lab National Chiao Tung University Outline Introduction Problem Formulation Algorithm -
More informationOrganization. 5.1 Semiconductor Main Memory. William Stallings Computer Organization and Architecture 6th Edition
William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory 5.1 Semiconductor Main Memory 5.2 Error Correction 5.3 Advanced DRAM Organization 5.1 Semiconductor Main Memory
More informationDesign and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology
Vol. 3, Issue. 3, May.-June. 2013 pp-1475-1481 ISSN: 2249-6645 Design and Simulation of Low Power 6TSRAM and Control its Leakage Current Using Sleepy Keeper Approach in different Topology Bikash Khandal,
More informationPower Reduction Techniques in the Memory System. Typical Memory Hierarchy
Power Reduction Techniques in the Memory System Low Power Design for SoCs ASIC Tutorial Memories.1 Typical Memory Hierarchy On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data Cache
More informationWilliam Stallings Computer Organization and Architecture 6th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 6th Edition Chapter 5 Internal Memory Semiconductor Memory Types Semiconductor Memory RAM Misnamed as all semiconductor memory is random access
More informationA 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS
A 65nm LEVEL-1 CACHE FOR MOBILE APPLICATIONS ABSTRACT We describe L1 cache designed for digital signal processor (DSP) core. The cache is 32KB with variable associativity (4 to 16 ways) and is pseudo-dual-ported.
More informationPARE: A Power-Aware Hardware Data Prefetching Engine
PARE: A Power-Aware Hardware Data Prefetching Engine Yao Guo Mahmoud Ben Naser Csaba Andras Moritz Department of Electrical and Computer Engineering University of Massachusetts, Amherst, MA 01003 {yaoguo,
More informationExecution-based Prediction Using Speculative Slices
Execution-based Prediction Using Speculative Slices Craig Zilles and Guri Sohi University of Wisconsin - Madison International Symposium on Computer Architecture July, 2001 The Problem Two major barriers
More informationLow-Power Technology for Image-Processing LSIs
Low- Technology for Image-Processing LSIs Yoshimi Asada The conventional LSI design assumed power would be supplied uniformly to all parts of an LSI. For a design with multiple supply voltages and a power
More informationVdd Programmable and Variation Tolerant FPGA Circuits and Architectures
Vdd Programmable and Variation Tolerant FPGA Circuits and Architectures Prof. Lei He EE Department, UCLA LHE@ee.ucla.edu Partially supported by NSF. Pathway to Power Efficiency and Variation Tolerance
More informationChip-Multithreading Systems Need A New Operating Systems Scheduler
Chip-Multithreading Systems Need A New Operating Systems Scheduler Alexandra Fedorova Christopher Small Daniel Nussbaum Margo Seltzer Harvard University, Sun Microsystems Sun Microsystems Sun Microsystems
More informationRegularity for Reduced Variability
Regularity for Reduced Variability Larry Pileggi Carnegie Mellon pileggi@ece.cmu.edu 28 July 2006 CMU Collaborators Andrzej Strojwas Slava Rovner Tejas Jhaveri Thiago Hersan Kim Yaw Tong Sandeep Gupta
More informationDESIGN METHODS IN SUB-MICRON TECHNOLOGIES
Chapter 1 DESIGN METHODS IN SUB-MICRON TECHNOLOGIES Yan Lin and Lei He Electrical Engineering Department University of California, Los Angeles, CA 90095 Field Programmable Gate Arrays (FPGA) provides an
More informationArchitecture at the end of Moore
Architecture at the end of Moore Stefanos Kaxiras Uppsala University IT Uppsala universitet Conclusions There s a power problem and it seems bad Nothing works really well (e.g., multicores) Heterogeous
More informationContinuing Moore s law
Continuing Moore s law MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017 Legal Disclaimer DISCLOSURES China Tech and Manufacturing
More informationGigascale Integration Design Challenges & Opportunities. Shekhar Borkar Circuit Research, Intel Labs October 24, 2004
Gigascale Integration Design Challenges & Opportunities Shekhar Borkar Circuit Research, Intel Labs October 24, 2004 Outline CMOS technology challenges Technology, circuit and μarchitecture solutions Integration
More information15-740/ Computer Architecture Lecture 19: Main Memory. Prof. Onur Mutlu Carnegie Mellon University
15-740/18-740 Computer Architecture Lecture 19: Main Memory Prof. Onur Mutlu Carnegie Mellon University Last Time Multi-core issues in caching OS-based cache partitioning (using page coloring) Handling
More informationComputing to the Energy and Performance Limits with Heterogeneous CPU-FPGA Devices. Dr Jose Luis Nunez-Yanez University of Bristol
Computing to the Energy and Performance Limits with Heterogeneous CPU-FPGA Devices Dr Jose Luis Nunez-Yanez University of Bristol Power and energy savings at run-time Power = α.c.v 2.f+g1.V 3 Energy =
More informationChip, Heal Thyself. The BulletProof Project
Chip, Heal Thyself Todd Austin Advanced Computer Architecture Lab University of Michigan With Prof. Valeria Bertacco, Prof. Scott Mahlke Kypros Constantinides, Smitha Shyam Mojtaba Mehrara, Mona Attariyan,
More informationAdvanced Digital Integrated Circuits. Lecture 9: SRAM. Announcements. Homework 1 due on Wednesday Quiz #1 next Monday, March 7
EE24 - Spring 20 Advanced Digital Integrated Circuits Lecture 9: SRAM Announcements Homework due on Wednesday Quiz # next Monday, March 7 2 Outline Last lecture Variability This lecture SRAM 3 Practical
More information250nm Technology Based Low Power SRAM Memory
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 1, Ver. I (Jan - Feb. 2015), PP 01-10 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org 250nm Technology Based Low Power
More informationDesigning for Low Power with Programmable System Solutions Dr. Yankin Tanurhan, Vice President, System Solutions and Advanced Applications
Designing for Low Power with Programmable System Solutions Dr. Yankin Tanurhan, Vice President, System Solutions and Advanced Applications Overview Why is power a problem? What can FPGAs do? Are we safe
More informationA novel low overhead fault tolerant Kogge-Stone adder using adaptive clocking
Purdue University Purdue e-pubs Department of Electrical and Computer Engineering Faculty Publications Department of Electrical and Computer Engineering January 8 A novel low overhead fault tolerant Kogge-Stone
More informationAdvanced Digital Integrated Circuits. Lecture 9: SRAM. Announcements. Homework 1 due on Wednesday Quiz #1 next Monday, March 7
EE241 - Spring 2011 Advanced Digital Integrated Circuits Lecture 9: SRAM Announcements Homework 1 due on Wednesday Quiz #1 next Monday, March 7 2 1 Outline Last lecture Variability This lecture SRAM 3
More informationCircuit and Microarchitectural Techniques for Reducing Cache Leakage Power
Circuit and Microarchitectural Techniques for Reducing Cache Leakage Power Nam Sung Kim, Krisztián Flautner, David Blaauw, and Trevor Mudge Abstract On-chip caches represent a sizable fraction of the total
More informationINTERNATIONAL JOURNAL OF PROFESSIONAL ENGINEERING STUDIES Volume 9 /Issue 3 / OCT 2017
Design of Low Power Adder in ALU Using Flexible Charge Recycling Dynamic Circuit Pallavi Mamidala 1 K. Anil kumar 2 mamidalapallavi@gmail.com 1 anilkumar10436@gmail.com 2 1 Assistant Professor, Dept of
More informationMemory memories memory
Memory Organization Memory Hierarchy Memory is used for storing programs and data that are required to perform a specific task. For CPU to operate at its maximum speed, it required an uninterrupted and
More informationDual-Core Execution: Building A Highly Scalable Single-Thread Instruction Window
Dual-Core Execution: Building A Highly Scalable Single-Thread Instruction Window Huiyang Zhou School of Computer Science University of Central Florida New Challenges in Billion-Transistor Processor Era
More informationBasic Sample and Hold Element. Prof. Paul Hasler Georgia Institute of Technology
Basic Sample and Hold Element Prof. Paul Hasler Georgia Institute of Technology Sample and Hold Elements Sample and Hold Elements Amplitude (Hold) (Sample) (Hold) Time Sample and Hold Elements Amplitude
More informationEE241 - Spring 2007 Advanced Digital Integrated Circuits. Announcements
EE241 - Spring 2007 Advanced Digital Integrated Circuits Lecture 22: SRAM Announcements Homework #4 due today Final exam on May 8 in class Project presentations on May 3, 1-5pm 2 1 Class Material Last
More informationPower-Efficient Approaches to Reliability. Abstract
Power-Efficient Approaches to Reliability Niti Madan, Rajeev Balasubramonian UUCS-05-010 School of Computing University of Utah Salt Lake City, UT 84112 USA December 2, 2005 Abstract Radiation-induced
More informationA Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement
A Case for Exploiting Complex Arithmetic Circuits towards Performance Yield Enhancement Shingo Watanabe 1, Masanori Hashimoto 2, Toshinori Sato 3 1 Kyushu Institute of Technology, 680-4 Kawazu, Iizuka,
More informationMicroprocessor Trends and Implications for the Future
Microprocessor Trends and Implications for the Future John Mellor-Crummey Department of Computer Science Rice University johnmc@rice.edu COMP 522 Lecture 4 1 September 2016 Context Last two classes: from
More informationSH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power SoC Design Platform
SH-Mobile3: Application Processor for 3G Cellular Phones on a Low-Power SoC Design Platform H. Mizuno, N. Irie, K. Uchiyama, Y. Yanagisawa 1, S. Yoshioka 1, I. Kawasaki 1, and T. Hattori 2 Hitachi Ltd.,
More informationBloom Filtering Cache Misses for Accurate Data Speculation and Prefetching
Bloom Filtering Cache Misses for Accurate Data Speculation and Prefetching Jih-Kwon Peir, Shih-Chang Lai, Shih-Lien Lu, Jared Stark, Konrad Lai peir@cise.ufl.edu Computer & Information Science and Engineering
More informationtechnology Leadership
technology Leadership MARK BOHR INTEL SENIOR FELLOW, TECHNOLOGY AND MANUFACTURING GROUP DIRECTOR, PROCESS ARCHITECTURE AND INTEGRATION SEPTEMBER 19, 2017 Legal Disclaimer DISCLOSURES China Tech and Manufacturing
More informationA Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion
A Non-Uniform Cache Architecture on Networks-on-Chip: A Fully Associative Approach with Pre-Promotion Akio Kodama Systems Research & Development Center NS Solutions Corporation Toshinori Sato Department
More informationSummer 2003 Lecture 18 07/09/03
Summer 2003 Lecture 18 07/09/03 NEW HOMEWORK Instruction Execution Times: The 8088 CPU is a synchronous machine that operates at a particular clock frequency. In the case of the original IBM PC, that clock
More informationDelay Modeling and Static Timing Analysis for MTCMOS Circuits
Delay Modeling and Static Timing Analysis for MTCMOS Circuits Naoaki Ohkubo Kimiyoshi Usami Graduate School of Engineering, Shibaura Institute of Technology 307 Fukasaku, Munuma-ku, Saitama, 337-8570 Japan
More informationComputer Organization. 8th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory Types Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM)
More informationPhysical Design of Digital Integrated Circuits (EN0291 S40) Sherief Reda Division of Engineering, Brown University Fall 2006
Physical Design of Digital Integrated Circuits (EN029 S40) Sherief Reda Division of Engineering, Brown University Fall 2006 Lecture 08: Interconnect Trees Introduction to Graphs and Trees Minimum Spanning
More informationConcept of Memory. The memory of computer is broadly categories into two categories:
Concept of Memory We have already mentioned that digital computer works on stored programmed concept introduced by Von Neumann. We use memory to store the information, which includes both program and data.
More informationECE 595Z Digital Systems Design Automation
ECE 595Z Digital Systems Design Automation Anand Raghunathan, raghunathan@purdue.edu How do you design chips with over 1 Billion transistors? Human designer capability grows far slower than Moore s law!
More informationLeakage Mitigation Techniques in Smartphone SoCs
Leakage Mitigation Techniques in Smartphone SoCs 1 John Redmond 1 Broadcom International Symposium on Low Power Electronics and Design Smartphone Use Cases Power Device Convergence Diverse Use Cases Camera
More informationInternal Memory. Computer Architecture. Outline. Memory Hierarchy. Semiconductor Memory Types. Copyright 2000 N. AYDIN. All rights reserved.
Computer Architecture Prof. Dr. Nizamettin AYDIN naydin@yildiz.edu.tr nizamettinaydin@gmail.com Internal Memory http://www.yildiz.edu.tr/~naydin 1 2 Outline Semiconductor main memory Random Access Memory
More informationReliable Physical Unclonable Function based on Asynchronous Circuits
Reliable Physical Unclonable Function based on Asynchronous Circuits Kyung Ki Kim Department of Electronic Engineering, Daegu University, Gyeongbuk, 38453, South Korea. E-mail: kkkim@daegu.ac.kr Abstract
More informationFPGA Programming Technology
FPGA Programming Technology Static RAM: This Xilinx SRAM configuration cell is constructed from two cross-coupled inverters and uses a standard CMOS process. The configuration cell drives the gates of
More informationMCD: A Multiple Clock Domain Microarchitecture
MCD: A Multiple Clock Domain Microarchitecture Dave Albonesi in collaboration with Greg Semeraro Grigoris Magklis Rajeev Balasubramonian Steve Dropsho Sandhya Dwarkadas Michael Scott Caveats We started
More informationNovel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014
Novel Nonvolatile Memory Hierarchies to Realize "Normally-Off Mobile Processors" ASP-DAC 2014 Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe Toshiba Corporation, R&D Center Advanced
More information250 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 2, FEBRUARY 2011
250 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 19, NO. 2, FEBRUARY 2011 Energy-Efficient Hardware Data Prefetching Yao Guo, Member, IEEE, Pritish Narayanan, Student Member,
More informationChapter 5 Internal Memory
Chapter 5 Internal Memory Memory Type Category Erasure Write Mechanism Volatility Random-access memory (RAM) Read-write memory Electrically, byte-level Electrically Volatile Read-only memory (ROM) Read-only
More informationDesign of Low Power 5T-Dual Vth SRAM-Cell
Design of Low Power 5T-Dual Vth SRAM- Chetna 1, Mr. Abhijeet 2 1 M-Tech Electronics and Communication, M.M. Engineering College Maharishi Markandeshwar University Mullana (Ambala) india 2 Lecturer in Electronics
More informationCOEN-4730 Computer Architecture Lecture 12. Testing and Design for Testability (focus: processors)
1 COEN-4730 Computer Architecture Lecture 12 Testing and Design for Testability (focus: processors) Cristinel Ababei Dept. of Electrical and Computer Engineering Marquette University 1 Outline Testing
More informationA 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias. David Kidd August 26, 2013
A 50% Lower Power ARM Cortex CPU using DDC Technology with Body Bias David Kidd August 26, 2013 1 HOTCHIPS 2013 Copyright 2013 SuVolta, Inc. All rights reserved. Agenda DDC transistor and PowerShrink platform
More informationShengyue Wang, Xiaoru Dai, Kiran S. Yellajyosula, Antonia Zhai, Pen-Chung Yew Department of Computer Science & Engineering University of Minnesota
Loop Selection for Thread-Level Speculation, Xiaoru Dai, Kiran S. Yellajyosula, Antonia Zhai, Pen-Chung Yew Department of Computer Science & Engineering University of Minnesota Chip Multiprocessors (CMPs)
More informationEnergy Efficient Asymmetrically Ported Register Files
Energy Efficient Asymmetrically Ported Register Files Aneesh Aggarwal ECE Department University of Maryland College Park, MD 20742 aneesh@eng.umd.edu Manoj Franklin ECE Department and UMIACS University
More informationReconfigurable Energy Efficient Near Threshold Cache Architectures
Reconfigurable Energy Efficient Near Threshold Cache Architectures Ronald G. Dreslinski, Gregory K. Chen, Trevor Mudge, David Blaauw, Dennis Sylvester University of Michigan - Ann Arbor, MI {rdreslin,grgkchen,tnm,blaauw,dennis}@eecs.umich.edu
More informationCache Architectures Design of Digital Circuits 217 Srdjan Capkun Onur Mutlu http://www.syssec.ethz.ch/education/digitaltechnik_17 Adapted from Digital Design and Computer Architecture, David Money Harris
More informationDesign and verification of low power SRAM system: Backend approach
Design and verification of low power SRAM system: Backend approach Yasmeen Saundatti, PROF.H.P.Rajani E&C Department, VTU University KLE College of Engineering and Technology, Udhayambag Belgaum -590008,
More informationAdaptive Robustness Tuning for High Performance Domino Logic
Adaptive Robustness Tuning for High Performance Domino Logic Bharan Giridhar 1, David Fick 1, Matthew Fojtik 1, Sudhir Satpathy 1, David Bull 2, Dennis Sylvester 1 and David Blaauw 1 1 niversity of Michigan,
More informationNon-Uniform Set-Associative Caches for Power-Aware Embedded Processors
Non-Uniform Set-Associative Caches for Power-Aware Embedded Processors Seiichiro Fujii 1 and Toshinori Sato 2 1 Kyushu Institute of Technology, 680-4, Kawazu, Iizuka, Fukuoka, 820-8502 Japan seiichi@mickey.ai.kyutech.ac.jp
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 10 -- Cache I 2014-2-20 John Lazzaro (not a prof - John is always OK) TA: Eric Love www-inst.eecs.berkeley.edu/~cs152/ Play: CS 152 L10: Cache I UC
More informationEnergy Efficiency and Resilience in Future ICs
Energy Efficiency and Resilience in Future ICs Andrew B. Kahng UCSD VLSI CAD Laboratory abk@cs.ucsd.edu http://vlsicad.ucsd.edu CSE and ECE Departments University of California, San Diego Outline The Power
More informationDYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech)
DYNAMIC CIRCUIT TECHNIQUE FOR LOW- POWER MICROPROCESSORS Kuruva Hanumantha Rao 1 (M.tech) K.Prasad Babu 2 M.tech (Ph.d) hanumanthurao19@gmail.com 1 kprasadbabuece433@gmail.com 2 1 PG scholar, VLSI, St.JOHNS
More informationReducing DRAM Latency at Low Cost by Exploiting Heterogeneity. Donghyuk Lee Carnegie Mellon University
Reducing DRAM Latency at Low Cost by Exploiting Heterogeneity Donghyuk Lee Carnegie Mellon University Problem: High DRAM Latency processor stalls: waiting for data main memory high latency Major bottleneck
More informationThe Design and Implementation of a Low-Latency On-Chip Network
The Design and Implementation of a Low-Latency On-Chip Network Robert Mullins 11 th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 24-27 th, 2006, Yokohama, Japan. Introduction Current
More informationISSN: [Bilani* et al.,7(2): February, 2018] Impact Factor: 5.164
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY A REVIEWARTICLE OF SDRAM DESIGN WITH NECESSARY CRITERIA OF DDR CONTROLLER Sushmita Bilani *1 & Mr. Sujeet Mishra 2 *1 M.Tech Student
More informationIntegrated CPU and Cache Power Management in Multiple Clock Domain Processors
Integrated CPU and Cache Power Management in Multiple Clock Domain Processors Nevine AbouGhazaleh, Bruce Childers, Daniel Mossé & Rami Melhem Department of Computer Science University of Pittsburgh HiPEAC
More informationWilliam Stallings Computer Organization and Architecture 8th Edition. Chapter 5 Internal Memory
William Stallings Computer Organization and Architecture 8th Edition Chapter 5 Internal Memory Semiconductor Memory The basic element of a semiconductor memory is the memory cell. Although a variety of
More informationAn Effective Reconstruction of Replica Memory Design Optimization for Embedded System
International Journal of Electronics Engineering Research. ISSN 0975-6450 Volume 9, Number 4 (2017) pp. 575-586 Research India Publications http://www.ripublication.com An Effective Reconstruction of Replica
More informationMTJ-Based Nonvolatile Logic-in-Memory Architecture
2011 Spintronics Workshop on LSI @ Kyoto, Japan, June 13, 2011 MTJ-Based Nonvolatile Logic-in-Memory Architecture Takahiro Hanyu Center for Spintronics Integrated Systems, Tohoku University, JAPAN Laboratory
More informationProcess Variations and Process-Tolerant Design
Process Variations and Process-Tolerant Design Swarup ~hunia', Saibal ~ukhopadhyay~, and Kaushik RO~' *Dept of EECS, Case Western Reserve University, 'Dept of ECE, Purdue University, skb2l @,case. edu;
More informationCS 152 Computer Architecture and Engineering
CS 152 Computer Architecture and Engineering Lecture 13 Memory and Interfaces 2005-3-1 John Lazzaro (www.cs.berkeley.edu/~lazzaro) TAs: Ted Hong and David Marquardt www-inst.eecs.berkeley.edu/~cs152/ Last
More informationA Fault Tolerant Cache Architecture for Sub 500mV Operation: Resizable Data Composer Cache (RDC-Cache)
A Fault Tolerant Cache Architecture for Sub 500mV Operation: Resizable Data Composer Cache (RDC-Cache) Avesta Sasan (Mohammad A. Makhzan), Houman Homayoun, Ahmed Eltawil, Fadi Kurdahi Electrical Engineering
More informationMemory Hierarchies. Instructor: Dmitri A. Gusev. Fall Lecture 10, October 8, CS 502: Computers and Communications Technology
Memory Hierarchies Instructor: Dmitri A. Gusev Fall 2007 CS 502: Computers and Communications Technology Lecture 10, October 8, 2007 Memories SRAM: value is stored on a pair of inverting gates very fast
More informationDependability, Power, and Performance Trade-off on a Multicore Processor
Dependability, Power, and Performance Trade-off on a Multi Processor Toshinori Sato System LSI Research Center Kyushu University toshinori.sato@computer.org Abstract - As deep submicron technologies are
More informationEmbedded Systems Design: A Unified Hardware/Software Introduction. Outline. Chapter 5 Memory. Introduction. Memory: basic concepts
Hardware/Software Introduction Chapter 5 Memory Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 1 2 Introduction Memory:
More informationEmbedded Systems Design: A Unified Hardware/Software Introduction. Chapter 5 Memory. Outline. Introduction
Hardware/Software Introduction Chapter 5 Memory 1 Outline Memory Write Ability and Storage Permanence Common Memory Types Composing Memory Memory Hierarchy and Cache Advanced RAM 2 Introduction Embedded
More informationInnovative Power Control for. Performance System LSIs. (Univ. of Electro-Communications) (Tokyo Univ. of Agriculture and Tech.)
Innovative Power Control for Ultra Low-Power and High- Performance System LSIs Hiroshi Nakamura Hideharu Amano Masaaki Kondo Mitaro Namiki Kimiyoshi Usami (Univ. of Tokyo) (Keio Univ.) (Univ. of Electro-Communications)
More informationA Write-Back-Free 2T1D Embedded. a Dual-Row-Access Low Power Mode.
A Write-Back-Free 2T1D Embedded DRAM with Local Voltage Sensing and a Dual-Row-Access Low Power Mode Wei Zhang, Ki Chul Chun, Chris H. Kim University of Minnesota, Minneapolis, MN zhang758@umn.edu Outline
More informationFinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University
FinFETs: Quo Vadis? Niraj K. Jha Dept. of Electrical Engineering Princeton University Talk Outline Quo Vadis FinFET devices? Quo Vadis FinFET standard cells and logic circuits? Addressing the Power Wall
More informationOptimizing Standby
Optimizing Power @ Standby Memory Benton H. Calhoun Jan M. Rabaey Chapter Outline Memory in Standby Voltage Scaling Body Biasing Periphery Memory Dominates Processor Area SRAM is a major source of static
More informationEN1640: Design of Computing Systems Topic 06: Memory System
EN164: Design of Computing Systems Topic 6: Memory System Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering Brown University Spring
More informationSigmaRAM Echo Clocks
SigmaRAM Echo s AN002 Introduction High speed, high throughput cell processing applications require fast access to data. As clock rates increase, the amount of time available to access and register data
More informationAn FPGA Architecture Supporting Dynamically-Controlled Power Gating
An FPGA Architecture Supporting Dynamically-Controlled Power Gating Altera Corporation March 16 th, 2012 Assem Bsoul and Steve Wilton {absoul, stevew}@ece.ubc.ca System-on-Chip Research Group Department
More informationVSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power Hai Li, Chen-Yong Cher, T. N. Vijaykumar, and Kaushik Roy 1285 EE Building, ECE Department, Purdue University @ecn.purdue.edu
More informationPower / Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches
/ Capacity Scaling: Energy Savings With Simple Fault-Tolerant Caches Nikil Dutt UC Irvine Computer Science dutt@uci.edu Mark Gottscho UCLA Electrical Engineering mgottscho@ucla.edu Alex Nicolau UC Irvine
More informationMemory in Digital Systems
MEMORIES Memory in Digital Systems Three primary components of digital systems Datapath (does the work) Control (manager) Memory (storage) Single bit ( foround ) Clockless latches e.g., SR latch Clocked
More informationCAD Technology of the SX-9
KONNO Yoshihiro, IKAWA Yasuhiro, SAWANO Tomoki KANAMARU Keisuke, ONO Koki, KUMAZAKI Masahito Abstract This paper outlines the design techniques and CAD technology used with the SX-9. The LSI and package
More information