Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE
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1 FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB
2 Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints and Reports Configuration Demo and Lab pp. 2
3 Concepts of Xilinx FPGA ACCESS IC LAB
4 Electronic Components pp. 4
5 FPGA Benefits Full-Custom ICs Cell-Based ICs Gate Arrays FPGA Speed Integration Density High-Volume Device Cost Low-Volume device Cost Time to Market Risk Reduction Future Modification Development Tool Educational Purpose pp. 5
6 Full Xilinx Design Support pp. 6
7 CPLDs and FPGAs Xilinx Products pp. 7
8 Xilinx FPGA Architecture ACCESS IC LAB
9 The Conceptual CPLD Architecture pp. 9
10 The Conceptual FPGA Architecture Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W pp. 10
11 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (1/6) pp. 11
12 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (2/6) Logic and Routing - the CLB tile pp. 12
13 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (3/6) Logic and Routing Simplified CLB Structure Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic. pp. 13
14 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (3/6) Logic and Routing Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LUTs) in a CLB. Capacity is limited by number of inputs, not complexity. Delay through CLB is constant. pp. 14
15 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (4/6) System Interface Select IO TM Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers pp. 15
16 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (5/6) System Memory Distributed RAM, Block RAM and External Memory pp. 16
17 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (6/6) System clock management - DLLs Clock Mirror Multiplication 1 DLL for 2x Combine 2 DLL for 4x Division Selectable division values - 1.5, 2, 2.5, 3, 4, 5, 8, or 16 Phase Shift 0, 90, 180, 270 pp. 17
18 Spatran-3, VirtexII FPGA Architecture (1/7) pp. 18
19 Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile pp. 19
20 Spatran-3, VirtexII FPGA Architecture (3/7) System Interface Select IO TM 23 different standards supported! pp. 20
21 Spatran-3, VirtexII FPGA Architecture (4/7) System Memory External Memory supports DDR memory pp. 21
22 Spatran-3, VirtexII FPGA Architecture (5/7) System clock management DCMs pp. 22
23 Spatran-3, VirtexII FPGA Architecture (6/7) System clock management DCMs pp. 23
24 Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer pp. 24
25 VirtexII Pro FPGA Architecture pp. 25
26 Programmable Logic Evolution pp. 26
27 Introduction to ISE ACCESS IC LAB
28 ISE 6.1i Future Xilinxdevices Proactive Timing Closure ECS & HDL Bencher & XST Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP Service Pack ISE WebPage ISE Philosophy pp. 28
29 Design Flow in ISE (1/2) Design A & B = C Synthesis A B C CLB Implement A B LUT Reg C Download A B C pp. 29
30 Design Flow in ISE (2/2) pp. 30
31 Introduction to Projection Navigator (1/4) pp. 31
32 Introduction to Projection Navigator (2/4) Source Windows pp. 32
33 Introduction to Projection Navigator (3/4) Introduction to Projection Navigator (3/4) Processes for current source pp. 33
34 Introduction to Projection Navigator (4/4) Processes for current source pp. 34
35 Create New Project pp. 35
36 Create New Source pp. 36
37 HDL Source File pp. 37
38 Text Entry pp. 38
39 Language Templates pp. 39
40 XST Synthesis (1/4) pp. 40
41 XST Flow Synthesis (2/4) pp. 41
42 Synthesis (3/4) Synthesis (3/4) Synthesis Step pp. 42
43 RTL view Synthesis (4/4) pp. 43
44 Implementation (1/8) Translate - Merge multiple design files into a single netlist Map - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route - Place components onto the chip, connect them, and extract timing data into reports pp. 44
45 Implementation (2/8) pp. 45
46 Implementation (3/8) Translate pp. 46
47 Implementation (4/8) Map pp. 47
48 Implementation (5/8) Map Property Trim Unconnected Signals If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly. Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending check it) Use Guide Design File (.ncd) You can refer the last mapping solution so that you maybe get better solution. Use RLOC Constraints Constraints of CLB (default check). Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O block. You can also chose only for input or only for output or off. pp. 48
49 Implementation (6/8) Place and Route pp. 49
50 Place and Route Property (1/2) Place & Route Effort Level (Overall) Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time. Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value. Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Route mean P&R must have been run at last once to use this option. Guide File Include the.ncd file. Implementation (7/8) pp. 50
51 Place and Route Property (2/2) Use Timing Constraints Include the.ucf file. Use Bonded I/Os Implementation (8/8) If it is checked, signals will be connected to I/O pads. Generate Detailed PAR Report Check the value to generate a detailed PAR report. Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report. Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.sdf). pp. 51
52 Download (1/2) pp. 52
53 Download (2/2) pp. 53
54 Code Generator ACCESS IC LAB
55 What are Cores? pp. 55
56 Benefits of Using Cores pp. 56
57 Invoking the CORE Generator GUI pp. 57
58 Xilinx Code Generator System GUI pp. 58
59 Core Customize Window pp. 59
60 Core Data Sheet pp. 60
61 Core Generator Design Flow pp. 61
62 Link with CodeGen IP (Verilog( Verilog) pp. 62
63 Constraints and Reports ACCESS IC LAB
64 Topics Assign Package Pins (PACE) Assigning Pins Create Timing Constraints The PERIOD Constraints The Pad-to-Pad Constraints The OFFSET Constraints The Constraints Editor Read Report pp. 64
65 Constraints GUI (1/2) pp. 65
66 Constraints GUI (2/2) pp. 66
67 Assign Package Pins (1/6) Start PACE Editor pp. 67
68 Assign Package Pins (2/6) PACE Editor GUI pp. 68
69 Assign Package Pins (3/6) Assign Package Pins (3/6) Method #1 to assign package pins pp. 69
70 Assign Package Pins (4/6) Method #2 to assign package pins pp. 70
71 Assign Package Pins (5/6) Assign Package Pins (5/6) Method #3 to assign package pins pp. 71
72 Assign Package Pins (6/6) Method #4 to assign package pins Use text editor to edit.ucf files NET is port name LOC assign pins to specific location pp. 72
73 The PERIOD Constraint pp. 73
74 The Pad-to to-pad Constraint pp. 74
75 The OFFSET Constraint pp. 75
76 The Constraint Editor (1/3) pp. 76
77 The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint pp. 77
78 The Constraint Editor (3/3) Enter OFFSET Constraint pp. 78
79 Create Report Files Read Report (1/12) pp. 79
80 Read Report (2/12) pp. 80
81 Read Report (3/12) Example of MAP Report (1/2) pp. 81
82 Read Report (4/12) Example of MAP Report (2/2) pp. 82
83 Read Report (5/12) pp. 83
84 Read Report (6/12) Example of PAR Report (1/2) pp. 84
85 Read Report (7/12) Example of PAR Report (2/2) pp. 85
86 Read Report (8/12) pp. 86
87 Read Report (9/12) Example of Timing Report (1/4) pp. 87
88 Read Report (10/12) Example of Timing Report (2/4) pp. 88
89 Read Report (11/12) Read Report (11/12) Example of Timing Report (3/4) pp. 89
90 Read Report (11/12) Example of Timing Report (4/4) pp. 90
91 Post-layout Simulation pp. 91
92 Configuration ACCESS IC LAB
93 What is configuration? Process for loading into the FPGA pp. 93
94 Configuration Mode (1/4) pp. 94
95 Serial Mode Configuration Mode (2/4) pp. 95
96 Configuration Mode (3/4) SelectMAP Mode pp. 96
97 Configuration Mode (4/4) Configuration Mode (4/4) JTAG or Boundary Scan pp. 97
98 IMACT (1/3) Must double clock Generate Programming File before programming FPGA pp. 98
99 IMACT (2/3) pp. 99
100 IMACT (3/3) pp. 100
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