Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE

Size: px
Start display at page:

Download "Graduate Institute of Electronics Engineering, NTU FPGA Design with Xilinx ISE"

Transcription

1 FPGA Design with Xilinx ISE Presenter: Shu-yen Lin Advisor: Prof. An-Yeu Wu 2005/6/6 ACCESS IC LAB

2 Outline Concepts of Xilinx FPGA Xilinx FPGA Architecture Introduction to ISE Code Generator Constraints and Reports Configuration Demo and Lab pp. 2

3 Concepts of Xilinx FPGA ACCESS IC LAB

4 Electronic Components pp. 4

5 FPGA Benefits Full-Custom ICs Cell-Based ICs Gate Arrays FPGA Speed Integration Density High-Volume Device Cost Low-Volume device Cost Time to Market Risk Reduction Future Modification Development Tool Educational Purpose pp. 5

6 Full Xilinx Design Support pp. 6

7 CPLDs and FPGAs Xilinx Products pp. 7

8 Xilinx FPGA Architecture ACCESS IC LAB

9 The Conceptual CPLD Architecture pp. 9

10 The Conceptual FPGA Architecture Field-programmable Re-programmable In-circuit design verification Rapid prototyping Fast time-to-market No IC-test & NRE cost H/W emulation instead of S/W pp. 10

11 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (1/6) pp. 11

12 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (2/6) Logic and Routing - the CLB tile pp. 12

13 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (3/6) Logic and Routing Simplified CLB Structure Two slices in each CLB Each slice contains 2 LUT, 2 Register and 2 Carry Logic. pp. 13

14 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (3/6) Logic and Routing Look-Up Tables (LUTs) Combinational logic is stored in Look-up Tables (LUTs) in a CLB. Capacity is limited by number of inputs, not complexity. Delay through CLB is constant. pp. 14

15 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (4/6) System Interface Select IO TM Supports multiple voltage and signal standards simultaneously Eliminate costly bus transceivers pp. 15

16 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (5/6) System Memory Distributed RAM, Block RAM and External Memory pp. 16

17 Spatran-2/2E, Virtex / Virtex-E E FPGA Architecture (6/6) System clock management - DLLs Clock Mirror Multiplication 1 DLL for 2x Combine 2 DLL for 4x Division Selectable division values - 1.5, 2, 2.5, 3, 4, 5, 8, or 16 Phase Shift 0, 90, 180, 270 pp. 17

18 Spatran-3, VirtexII FPGA Architecture (1/7) pp. 18

19 Spatran-3, VirtexII FPGA Architecture (2/7) Logic and Routing - the CLB tile pp. 19

20 Spatran-3, VirtexII FPGA Architecture (3/7) System Interface Select IO TM 23 different standards supported! pp. 20

21 Spatran-3, VirtexII FPGA Architecture (4/7) System Memory External Memory supports DDR memory pp. 21

22 Spatran-3, VirtexII FPGA Architecture (5/7) System clock management DCMs pp. 22

23 Spatran-3, VirtexII FPGA Architecture (6/7) System clock management DCMs pp. 23

24 Spatran-3, VirtexII FPGA Architecture (7/7) Embedded multiplexer pp. 24

25 VirtexII Pro FPGA Architecture pp. 25

26 Programmable Logic Evolution pp. 26

27 Introduction to ISE ACCESS IC LAB

28 ISE 6.1i Future Xilinxdevices Proactive Timing Closure ECS & HDL Bencher & XST Platform Unix: Solaris 2.7/2.8 PC: Win 2000/XP Service Pack ISE WebPage ISE Philosophy pp. 28

29 Design Flow in ISE (1/2) Design A & B = C Synthesis A B C CLB Implement A B LUT Reg C Download A B C pp. 29

30 Design Flow in ISE (2/2) pp. 30

31 Introduction to Projection Navigator (1/4) pp. 31

32 Introduction to Projection Navigator (2/4) Source Windows pp. 32

33 Introduction to Projection Navigator (3/4) Introduction to Projection Navigator (3/4) Processes for current source pp. 33

34 Introduction to Projection Navigator (4/4) Processes for current source pp. 34

35 Create New Project pp. 35

36 Create New Source pp. 36

37 HDL Source File pp. 37

38 Text Entry pp. 38

39 Language Templates pp. 39

40 XST Synthesis (1/4) pp. 40

41 XST Flow Synthesis (2/4) pp. 41

42 Synthesis (3/4) Synthesis (3/4) Synthesis Step pp. 42

43 RTL view Synthesis (4/4) pp. 43

44 Implementation (1/8) Translate - Merge multiple design files into a single netlist Map - Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) Place & Route - Place components onto the chip, connect them, and extract timing data into reports pp. 44

45 Implementation (2/8) pp. 45

46 Implementation (3/8) Translate pp. 46

47 Implementation (4/8) Map pp. 47

48 Implementation (5/8) Map Property Trim Unconnected Signals If you check this item, the mapping tool will remove the unconnected wire that let the tracing back become hardly. Generate Detailed Map Report If more detailed report is needed, you can check it. (Recommending check it) Use Guide Design File (.ncd) You can refer the last mapping solution so that you maybe get better solution. Use RLOC Constraints Constraints of CLB (default check). Pack I/O Registers/Latches into IOBs If the value chosen Default that pack the register nearby I/O into I/O block. You can also chose only for input or only for output or off. pp. 48

49 Implementation (6/8) Place and Route pp. 49

50 Place and Route Property (1/2) Place & Route Effort Level (Overall) Effort Level means the P&R effect result. Using the Higher get the better solution, but spend more time. Starting Placer Cost Table (0-100) Specify a placement initialization value with which to begin P&R attempts. Each subsequent attempt is assigned an incremental value based on the placement initialization value. Place and Route Mode Quick means without timing constraints; Route Only and Re-entrant Route mean P&R must have been run at last once to use this option. Guide File Include the.ncd file. Implementation (7/8) pp. 50

51 Place and Route Property (2/2) Use Timing Constraints Include the.ucf file. Use Bonded I/Os Implementation (8/8) If it is checked, signals will be connected to I/O pads. Generate Detailed PAR Report Check the value to generate a detailed PAR report. Generate Post-Place & Route Static Timing Report Check the value to generate post-place & route static timing report. Generate Post-Place & Route Simulation Model Check it for generating required simulation files for ModelSim (*.v and *.sdf). pp. 51

52 Download (1/2) pp. 52

53 Download (2/2) pp. 53

54 Code Generator ACCESS IC LAB

55 What are Cores? pp. 55

56 Benefits of Using Cores pp. 56

57 Invoking the CORE Generator GUI pp. 57

58 Xilinx Code Generator System GUI pp. 58

59 Core Customize Window pp. 59

60 Core Data Sheet pp. 60

61 Core Generator Design Flow pp. 61

62 Link with CodeGen IP (Verilog( Verilog) pp. 62

63 Constraints and Reports ACCESS IC LAB

64 Topics Assign Package Pins (PACE) Assigning Pins Create Timing Constraints The PERIOD Constraints The Pad-to-Pad Constraints The OFFSET Constraints The Constraints Editor Read Report pp. 64

65 Constraints GUI (1/2) pp. 65

66 Constraints GUI (2/2) pp. 66

67 Assign Package Pins (1/6) Start PACE Editor pp. 67

68 Assign Package Pins (2/6) PACE Editor GUI pp. 68

69 Assign Package Pins (3/6) Assign Package Pins (3/6) Method #1 to assign package pins pp. 69

70 Assign Package Pins (4/6) Method #2 to assign package pins pp. 70

71 Assign Package Pins (5/6) Assign Package Pins (5/6) Method #3 to assign package pins pp. 71

72 Assign Package Pins (6/6) Method #4 to assign package pins Use text editor to edit.ucf files NET is port name LOC assign pins to specific location pp. 72

73 The PERIOD Constraint pp. 73

74 The Pad-to to-pad Constraint pp. 74

75 The OFFSET Constraint pp. 75

76 The Constraint Editor (1/3) pp. 76

77 The Constraint Editor (2/3) Enter PERIOD and Pad-to-Pad Constraint pp. 77

78 The Constraint Editor (3/3) Enter OFFSET Constraint pp. 78

79 Create Report Files Read Report (1/12) pp. 79

80 Read Report (2/12) pp. 80

81 Read Report (3/12) Example of MAP Report (1/2) pp. 81

82 Read Report (4/12) Example of MAP Report (2/2) pp. 82

83 Read Report (5/12) pp. 83

84 Read Report (6/12) Example of PAR Report (1/2) pp. 84

85 Read Report (7/12) Example of PAR Report (2/2) pp. 85

86 Read Report (8/12) pp. 86

87 Read Report (9/12) Example of Timing Report (1/4) pp. 87

88 Read Report (10/12) Example of Timing Report (2/4) pp. 88

89 Read Report (11/12) Read Report (11/12) Example of Timing Report (3/4) pp. 89

90 Read Report (11/12) Example of Timing Report (4/4) pp. 90

91 Post-layout Simulation pp. 91

92 Configuration ACCESS IC LAB

93 What is configuration? Process for loading into the FPGA pp. 93

94 Configuration Mode (1/4) pp. 94

95 Serial Mode Configuration Mode (2/4) pp. 95

96 Configuration Mode (3/4) SelectMAP Mode pp. 96

97 Configuration Mode (4/4) Configuration Mode (4/4) JTAG or Boundary Scan pp. 97

98 IMACT (1/3) Must double clock Generate Programming File before programming FPGA pp. 98

99 IMACT (2/3) pp. 99

100 IMACT (3/3) pp. 100

TLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4

TLL5000 Electronic System Design Base Module. Getting Started Guide, Ver 3.4 TLL5000 Electronic System Design Base Module Getting Started Guide, Ver 3.4 COPYRIGHT NOTICE The Learning Labs, Inc. ( TLL ) All rights reserved, 2008 Reproduction in any form without permission is prohibited.

More information

FPGA Design Flow 1. All About FPGA

FPGA Design Flow 1. All About FPGA FPGA Design Flow 1 In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified version of FPGA design flow is given in the flowing diagram. FPGA Design Flow 2 FPGA_Design_FLOW

More information

ISE Design Suite Software Manuals and Help

ISE Design Suite Software Manuals and Help ISE Design Suite Software Manuals and Help These documents support the Xilinx ISE Design Suite. Click a document title on the left to view a document, or click a design step in the following figure to

More information

FPGA: What? Why? Marco D. Santambrogio

FPGA: What? Why? Marco D. Santambrogio FPGA: What? Why? Marco D. Santambrogio marco.santambrogio@polimi.it 2 Reconfigurable Hardware Reconfigurable computing is intended to fill the gap between hardware and software, achieving potentially much

More information

TLL5000 Electronic System Design Base Module

TLL5000 Electronic System Design Base Module TLL5000 Electronic System Design Base Module The Learning Labs, Inc. Copyright 2007 Manual Revision 2007.12.28 1 Copyright 2007 The Learning Labs, Inc. Copyright Notice The Learning Labs, Inc. ( TLL )

More information

CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline

CPE/EE 422/522. Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices. Dr. Rhonda Kay Gaede UAH. Outline CPE/EE 422/522 Introduction to Xilinx Virtex Field-Programmable Gate Arrays Devices Dr. Rhonda Kay Gaede UAH Outline Introduction Field-Programmable Gate Arrays Virtex Virtex-E, Virtex-II, and Virtex-II

More information

FPGA Based Digital Design Using Verilog HDL

FPGA Based Digital Design Using Verilog HDL FPGA Based Digital Design Using Course Designed by: IRFAN FAISAL MIR ( Verilog / FPGA Designer ) irfanfaisalmir@yahoo.com * Organized by Electronics Division Integrated Circuits Uses for digital IC technology

More information

Graduate Institute of Electronics Engineering, NTU. FPGA Lab. Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU. FPGA Lab. Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB FPGA Lab Speaker : 鍾明翰 (CMH) Advisor: Prof. An-Yeu Wu Date: 2010/12/14 ACCESS IC LAB Objective In this Lab, you will learn the basic set-up and design methods of implementing your design by ISE 10.1. Create

More information

DESIGN STRATEGIES & TOOLS UTILIZED

DESIGN STRATEGIES & TOOLS UTILIZED CHAPTER 7 DESIGN STRATEGIES & TOOLS UTILIZED 7-1. Field Programmable Gate Array The internal architecture of an FPGA consist of several uncommitted logic blocks in which the design is to be encoded. The

More information

What is Xilinx Design Language?

What is Xilinx Design Language? Bill Jason P. Tomas University of Nevada Las Vegas Dept. of Electrical and Computer Engineering What is Xilinx Design Language? XDL is a human readable ASCII format compatible with the more widely used

More information

DESIGN AND IMPLEMENTATION OF 32-BIT CONTROLLER FOR INTERACTIVE INTERFACING WITH RECONFIGURABLE COMPUTING SYSTEMS

DESIGN AND IMPLEMENTATION OF 32-BIT CONTROLLER FOR INTERACTIVE INTERFACING WITH RECONFIGURABLE COMPUTING SYSTEMS DESIGN AND IMPLEMENTATION OF 32-BIT CONTROLLER FOR INTERACTIVE INTERFACING WITH RECONFIGURABLE COMPUTING SYSTEMS Ashutosh Gupta and Kota Solomon Raju Digital System Group, Central Electronics Engineering

More information

Virtex-II Architecture

Virtex-II Architecture Virtex-II Architecture Block SelectRAM resource I/O Blocks (IOBs) edicated multipliers Programmable interconnect Configurable Logic Blocks (CLBs) Virtex -II architecture s core voltage operates at 1.5V

More information

Xilinx ISE Synthesis Tutorial

Xilinx ISE Synthesis Tutorial Xilinx ISE Synthesis Tutorial The following tutorial provides a basic description of how to use Xilinx ISE to create a simple 2-input AND gate and synthesize the design onto the Spartan-3E Starter Board

More information

INTRODUCTION TO FPGA ARCHITECTURE

INTRODUCTION TO FPGA ARCHITECTURE 3/3/25 INTRODUCTION TO FPGA ARCHITECTURE DIGITAL LOGIC DESIGN (BASIC TECHNIQUES) a b a y 2input Black Box y b Functional Schematic a b y a b y a b y 2 Truth Table (AND) Truth Table (OR) Truth Table (XOR)

More information

EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs)

EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Fall 2002 EECS150 - Lec06-FPGA Page 1 Outline What are FPGAs? Why use FPGAs (a short history

More information

Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs?

Outline. EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) FPGA Overview. Why FPGAs? EECS150 - Digital Design Lecture 6 - Field Programmable Gate Arrays (FPGAs) September 12, 2002 John Wawrzynek Outline What are FPGAs? Why use FPGAs (a short history lesson). FPGA variations Internal logic

More information

Chapter 9: Integration of Full ASIP and its FPGA Implementation

Chapter 9: Integration of Full ASIP and its FPGA Implementation Chapter 9: Integration of Full ASIP and its FPGA Implementation 9.1 Introduction A top-level module has been created for the ASIP in VHDL in which all the blocks have been instantiated at the Register

More information

PINE TRAINING ACADEMY

PINE TRAINING ACADEMY PINE TRAINING ACADEMY Course Module A d d r e s s D - 5 5 7, G o v i n d p u r a m, G h a z i a b a d, U. P., 2 0 1 0 1 3, I n d i a Digital Logic System Design using Gates/Verilog or VHDL and Implementation

More information

PlanAhead Release Notes

PlanAhead Release Notes PlanAhead Release Notes What s New in the 11.1 Release UG656(v 11.1.0) April 27, 2009 PlanAhead 11.1 Release Notes Page 1 Table of Contents What s New in the PlanAhead 11.1 Release... 4 Device Support...

More information

Introduction to Field Programmable Gate Arrays

Introduction to Field Programmable Gate Arrays Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May 9 June 2007 Javier Serrano, CERN AB-CO-HT Outline Historical introduction.

More information

Programmable Logic Devices HDL-Based Design Flows CMPE 415

Programmable Logic Devices HDL-Based Design Flows CMPE 415 HDL-Based Design Flows: ASIC Toward the end of the 80s, it became difficult to use schematic-based ASIC flows to deal with the size and complexity of >5K or more gates. HDLs were introduced to deal with

More information

FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011

FPGA for Complex System Implementation. National Chiao Tung University Chun-Jen Tsai 04/14/2011 FPGA for Complex System Implementation National Chiao Tung University Chun-Jen Tsai 04/14/2011 About FPGA FPGA was invented by Ross Freeman in 1989 SRAM-based FPGA properties Standard parts Allowing multi-level

More information

Synthesis of VHDL Code for FPGA Design Flow Using Xilinx PlanAhead Tool

Synthesis of VHDL Code for FPGA Design Flow Using Xilinx PlanAhead Tool Synthesis of VHDL Code for FPGA Design Flow Using Xilinx PlanAhead Tool Md. Abdul Latif Sarker, Moon Ho Lee Division of Electronics & Information Engineering Chonbuk National University 664-14 1GA Dekjin-Dong

More information

An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays

An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2013-11-07 An Incremental Trace-Based Debug System for Field-Programmable Gate-Arrays Jared Matthew Keeley Brigham Young University

More information

ECE 4514 Digital Design II. Spring Lecture 20: Timing Analysis and Timed Simulation

ECE 4514 Digital Design II. Spring Lecture 20: Timing Analysis and Timed Simulation ECE 4514 Digital Design II Lecture 20: Timing Analysis and Timed Simulation A Tools/Methods Lecture Topics Static and Dynamic Timing Analysis Static Timing Analysis Delay Model Path Delay False Paths Timing

More information

OVERVIEW OF FPGA AND EDA SOFTWARE

OVERVIEW OF FPGA AND EDA SOFTWARE CHAPTER 2 OVERVIEW OF FPGA AND EDA SOFTWARE 2.1 INTRODUCTION Developing a large FPGA-based system is an involved process that consists of many complex transformations and optimization algorithms. Software

More information

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes

A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes A Deterministic Flow Combining Virtual Platforms, Emulation, and Hardware Prototypes Presented at Design Automation Conference (DAC) San Francisco, CA, June 4, 2012. Presented by Chuck Cruse FPGA Hardware

More information

Evolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic

Evolution of Implementation Technologies. ECE 4211/5211 Rapid Prototyping with FPGAs. Gate Array Technology (IBM s) Programmable Logic ECE 42/52 Rapid Prototyping with FPGAs Dr. Charlie Wang Department of Electrical and Computer Engineering University of Colorado at Colorado Springs Evolution of Implementation Technologies Discrete devices:

More information

Version 1.6 Page 2 of 25 SMT351 User Manual

Version 1.6 Page 2 of 25 SMT351 User Manual SMT351 User Manual Version 1.6 Page 2 of 25 SMT351 User Manual Revision History Date Comments Engineer Version 28/07/04 First revision JPA 1.1 16/09/04 Added pin number for JP1 pinout section. Updated

More information

CHAPTER-IV IMPLEMENTATION AND ANALYSIS OF FPGA-BASED DESIGN OF 32-BIT FPAU

CHAPTER-IV IMPLEMENTATION AND ANALYSIS OF FPGA-BASED DESIGN OF 32-BIT FPAU CHAPTER-IV IMPLEMENTATION AND ANALYSIS OF FPGA-BASED DESIGN OF 32-BIT FPAU The design of 32 bit FPAU using VHDL presented in chapter III needs to be further implemented and tested on FPGA platform and

More information

FPGA. Logic Block. Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function.

FPGA. Logic Block. Plessey FPGA: basic building block here is 2-input NAND gate which is connected to each other to implement desired function. FPGA Logic block of an FPGA can be configured in such a way that it can provide functionality as simple as that of transistor or as complex as that of a microprocessor. It can used to implement different

More information

LSN 1 Digital Design Flow for PLDs

LSN 1 Digital Design Flow for PLDs LSN 1 Digital Design Flow for PLDs ECT357 Microprocessors I Department of Engineering Technology LSN 1 Programmable Logic Devices Functionless devices in base form Require programming to operate The logic

More information

EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09

EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 Lab Description Today s lab will introduce you to the Xilinx Integrated Software Environment (ISE)

More information

Tutorial: Working with Verilog and the Xilinx FPGA in ISE 9.2i

Tutorial: Working with Verilog and the Xilinx FPGA in ISE 9.2i Tutorial: Working with Verilog and the Xilinx FPGA in ISE 9.2i This tutorial will show you how to: Use Verilog to specify a design Simulate that Verilog design Define pin constraints for the FPGA (.ucf

More information

L2: FPGA HARDWARE : ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA

L2: FPGA HARDWARE : ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA L2: FPGA HARDWARE 18-545: ADVANCED DIGITAL DESIGN PROJECT FALL 2015 BRANDON LUCIA 18-545: FALL 2014 2 Admin stuff Project Proposals happen on Monday Be prepared to give an in-class presentation Lab 1 is

More information

Advanced FPGA Design Methodologies with Xilinx Vivado

Advanced FPGA Design Methodologies with Xilinx Vivado Advanced FPGA Design Methodologies with Xilinx Vivado Alexander Jäger Computer Architecture Group Heidelberg University, Germany Abstract With shrinking feature sizes in the ASIC manufacturing technology,

More information

Xilinx Tutorial Basic Walk-through

Xilinx Tutorial Basic Walk-through Introduction to Digital Logic Design with FPGA s: Digital logic circuits form the basis of all digital electronic devices. FPGAs (Field Programmable Gate Array) are large programmable digital electronic

More information

Lab 1: FPGA Physical Layout

Lab 1: FPGA Physical Layout Lab 1: FPGA Physical Layout University of California, Berkeley Department of Electrical Engineering and Computer Sciences EECS150 Components and Design Techniques for Digital Systems John Wawrzynek, James

More information

IDEA! Avnet SpeedWay Design Workshop

IDEA! Avnet SpeedWay Design Workshop The essence of FPGA technology IDEA! 2 ISE Tool Flow Overview Design Entry Synthesis Constraints Synthesis Simulation Implementation Constraints Floor-Planning Translate Map Place & Route Timing Analysis

More information

Field Programmable Gate Array (FPGA)

Field Programmable Gate Array (FPGA) Field Programmable Gate Array (FPGA) Lecturer: Krébesz, Tamas 1 FPGA in general Reprogrammable Si chip Invented in 1985 by Ross Freeman (Xilinx inc.) Combines the advantages of ASIC and uc-based systems

More information

Introduction to Partial Reconfiguration Methodology

Introduction to Partial Reconfiguration Methodology Methodology This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Define Partial Reconfiguration technology List common applications

More information

Basic FPGA Architecture Xilinx, Inc. All Rights Reserved

Basic FPGA Architecture Xilinx, Inc. All Rights Reserved Basic FPGA Architecture 2005 Xilinx, Inc. All Rights Reserved Objectives After completing this module, you will be able to: Identify the basic architectural resources of the Virtex -II FPGA List the differences

More information

ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004

ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004 Goals ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004 1. To review the use of Verilog for combinational logic design. 2. To become familiar with using the Xilinx ISE software

More information

High Capacity and High Performance 20nm FPGAs. Steve Young, Dinesh Gaitonde August Copyright 2014 Xilinx

High Capacity and High Performance 20nm FPGAs. Steve Young, Dinesh Gaitonde August Copyright 2014 Xilinx High Capacity and High Performance 20nm FPGAs Steve Young, Dinesh Gaitonde August 2014 Not a Complete Product Overview Page 2 Outline Page 3 Petabytes per month Increasing Bandwidth Global IP Traffic Growth

More information

Using Synplify Pro, ISE and ModelSim

Using Synplify Pro, ISE and ModelSim Using Synplify Pro, ISE and ModelSim VLSI Systems on Chip ET4 351 Rene van Leuken Huib Lincklaen Arriëns Rev. 1.2 The EDA programs that will be used are: For RTL synthesis: Synplicity Synplify Pro For

More information

ECE 331 Digital System Design

ECE 331 Digital System Design ECE 331 Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #17) The slides included herein were taken from the materials accompanying Fundamentals of Logic

More information

CS310 Embedded Computer Systems. Maeng

CS310 Embedded Computer Systems. Maeng 1 INTRODUCTION (PART II) Maeng Three key embedded system technologies 2 Technology A manner of accomplishing a task, especially using technical processes, methods, or knowledge Three key technologies for

More information

Digital Integrated Circuits

Digital Integrated Circuits Digital Integrated Circuits Lecture 9 Jaeyong Chung Robust Systems Laboratory Incheon National University DIGITAL DESIGN FLOW Chung EPC6055 2 FPGA vs. ASIC FPGA (A programmable Logic Device) Faster time-to-market

More information

Chapter 2. FPGA and Dynamic Reconfiguration ...

Chapter 2. FPGA and Dynamic Reconfiguration ... Chapter 2 FPGA and Dynamic Reconfiguration... This chapter will introduce a family of silicon devices, FPGAs exploring their architecture. This work is based on these particular devices. The chapter will

More information

Lab 3 Sequential Logic for Synthesis. FPGA Design Flow.

Lab 3 Sequential Logic for Synthesis. FPGA Design Flow. Lab 3 Sequential Logic for Synthesis. FPGA Design Flow. Task 1 Part 1 Develop a VHDL description of a Debouncer specified below. The following diagram shows the interface of the Debouncer. The following

More information

Hardware describing languages, high level tools and Synthesis

Hardware describing languages, high level tools and Synthesis Hardware describing languages, high level tools and Synthesis Hardware describing languages (HDL) Compiled/Interpreted Compiled: Description compiled into C and then into binary or directly into binary

More information

Tutorial on FPGA Design Flow based on Aldec Active HDL. Ver 1.5

Tutorial on FPGA Design Flow based on Aldec Active HDL. Ver 1.5 Tutorial on FPGA Design Flow based on Aldec Active HDL Ver 1.5 1 Prepared by Ekawat (Ice) Homsirikamol, Marcin Rogawski, Jeremy Kelly, John Pham, and Dr. Kris Gaj This tutorial assumes that you have basic

More information

8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments

8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments 8. Best Practices for Incremental Compilation Partitions and Floorplan Assignments QII51017-9.0.0 Introduction The Quartus II incremental compilation feature allows you to partition a design, compile partitions

More information

Digital Circuit Design Using Xilinx ISE Tools

Digital Circuit Design Using Xilinx ISE Tools Digital Circuit Design Using Xilinx ISE Tools Poras T. Balsara and Prashant Vallur Table of Contents 1. Introduction 2. Programmable logic devices: FPGA and CPLD 3. Creating a new project in Xilinx Foundation

More information

Hierarchical Design Methodology Guide. UG748 (v13.2) July 6, 2011

Hierarchical Design Methodology Guide. UG748 (v13.2) July 6, 2011 Hierarchical Design Methodology Guide Xilinx is disclosing this user guide, manual, release note, and/or specification (the Documentation ) to you solely for use in the development of designs to operate

More information

ALTERA FPGAs Architecture & Design

ALTERA FPGAs Architecture & Design ALTERA FPGAs Architecture & Design Course Description This course provides all theoretical and practical know-how to design programmable devices of ALTERA with QUARTUS-II design software. The course combines

More information

Synthesis Options FPGA and ASIC Technology Comparison - 1

Synthesis Options FPGA and ASIC Technology Comparison - 1 Synthesis Options Comparison - 1 2009 Xilinx, Inc. All Rights Reserved Welcome If you are new to FPGA design, this module will help you synthesize your design properly These synthesis techniques promote

More information

Verilog Design Entry, Synthesis, and Behavioral Simulation

Verilog Design Entry, Synthesis, and Behavioral Simulation ------------------------------------------------------------- PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walk you through some typical tasks and familiarize

More information

Introduction to WebPACK 6.1. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board

Introduction to WebPACK 6.1. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Introduction to WebPACK 6.1 Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Release date: 10/30/2003 All XS-prefix product designations are trademarks of XESS Corp. All XC-prefix

More information

EECS 151/251A FPGA Lab Lab 2: Introduction to FPGA Development + Creating a Tone Generator

EECS 151/251A FPGA Lab Lab 2: Introduction to FPGA Development + Creating a Tone Generator EECS 151/251A FPGA Lab Lab 2: Introduction to FPGA Development + Creating a Tone Generator Prof. John Wawrzynek, Nicholas Weaver TAs: Arya Reais-Parsi, Taehwan Kim Department of Electrical Engineering

More information

LSN 6 Programmable Logic Devices

LSN 6 Programmable Logic Devices LSN 6 Programmable Logic Devices Department of Engineering Technology LSN 6 What Are PLDs? Functionless devices in base form Require programming to operate The logic function of the device is programmed

More information

Circuit Design and Simulation with VHDL 2nd edition Volnei A. Pedroni MIT Press, 2010 Book web:

Circuit Design and Simulation with VHDL 2nd edition Volnei A. Pedroni MIT Press, 2010 Book web: Circuit Design and Simulation with VHDL 2nd edition Volnei A. Pedroni MIT Press, 2010 Book web: www.vhdl.us Appendix C Xilinx ISE Tutorial (ISE 11.1) This tutorial is based on ISE 11.1 WebPack (free at

More information

Hierarchical Design Using Synopsys and Xilinx FPGAs

Hierarchical Design Using Synopsys and Xilinx FPGAs White Paper: FPGA Design Tools WP386 (v1.0) February 15, 2011 Hierarchical Design Using Synopsys and Xilinx FPGAs By: Kate Kelley Xilinx FPGAs offer up to two million logic cells currently, and they continue

More information

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD

EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the

More information

CS152 FPGA CAD Tool Flow University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences

CS152 FPGA CAD Tool Flow University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences CS152 FPGA CAD Tool Flow University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Compiled: 4/3/2003 for CS152 Spring 03, Prof. John Kubiatowicz

More information

DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL (REGULATION-2013) LAB MANUAL DEPARTMENT OF ECE NAME: REGISTER NUMBER: YEAR/SEM.: ACADEMIC YEAR: 2015-2016 DEPT OF ECE EC6612 -VLSI DESIGN LABORATORY MANUAL

More information

Introduction to WebPACK 6.3. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board

Introduction to WebPACK 6.3. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Introduction to WebPACK 6.3 Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Release date: 1/1/2005 2005 by XESS Corp. All XS-prefix product designations are trademarks of XESS Corp.

More information

Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax

Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax Xilinx ISE WebPACK Schematic Capture Tutorial Revision: February 27, 2010 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This tutorial provides instruction for using the Xilinx

More information

ENGN 1630: CPLD Simulation Fall ENGN 1630 Fall Simulating XC9572XLs on the ENGN1630 CPLD-II Board Using Xilinx ISim

ENGN 1630: CPLD Simulation Fall ENGN 1630 Fall Simulating XC9572XLs on the ENGN1630 CPLD-II Board Using Xilinx ISim ENGN 1630 Fall 2018 Simulating XC9572XLs on the ENGN1630 CPLD-II Board Using Xilinx ISim You will use the Xilinx ISim simulation software for the required timing simulation of the XC9572XL CPLD programmable

More information

Tutorial: ISE 12.2 and the Spartan3e Board v August 2010

Tutorial: ISE 12.2 and the Spartan3e Board v August 2010 Tutorial: ISE 12.2 and the Spartan3e Board v12.2.1 August 2010 This tutorial will show you how to: Use a combination of schematics and Verilog to specify a design Simulate that design Define pin constraints

More information

Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 3rd year engineering. Winter/Summer Training

Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 3rd year engineering. Winter/Summer Training Method We follow- How to Get Entry Pass in SEMICODUCTOR Industries for 3rd year engineering Winter/Summer Training Level 2 continues. 3 rd Year 4 th Year FIG-3 Level 1 (Basic & Mandatory) & Level 1.1 and

More information

Signal Processing Algorithms into Fixed Point FPGA Hardware Dennis Silage ECE Temple University

Signal Processing Algorithms into Fixed Point FPGA Hardware Dennis Silage ECE Temple University Signal Processing Algorithms into Fixed Point FPGA Hardware Dennis Silage silage@temple.edu ECE Temple University www.temple.edu/scdl Signal Processing Algorithms into Fixed Point FPGA Hardware Motivation

More information

PlanAhead Methodology Guide

PlanAhead Methodology Guide PlanAhead Methodology Guide Release 10.1 1/18/2008 2:19 PM Page 1 Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design ) to you for use in the development of designs to

More information

FPGA architecture and design technology

FPGA architecture and design technology CE 435 Embedded Systems Spring 2017 FPGA architecture and design technology Nikos Bellas Computer and Communications Engineering Department University of Thessaly 1 FPGA fabric A generic island-style FPGA

More information

Introduction to WebPACK 8.1. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board

Introduction to WebPACK 8.1. Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Introduction to WebPACK 8.1 Using Xilinx WebPACK Software to Create FPGA Designs for the XSA Board Release date: 5/16/2005 2006 by XESS Corp. All XS-prefix product designations are trademarks of XESS

More information

and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly!

and 32 bit for 32 bit. If you don t pay attention to this, there will be unexpected behavior in the ISE software and thing may not work properly! This tutorial will show you how to: Part I: Set up a new project in ISE 14.7 Part II: Implement a function using Schematics Part III: Simulate the schematic circuit using ISim Part IV: Constraint, Synthesize,

More information

ChipScope Demo Instructions

ChipScope Demo Instructions UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Overview ChipScope is an embedded, software based logic analyzer. By inserting an intergrated

More information

Lab 3 Verilog Simulation Mapping

Lab 3 Verilog Simulation Mapping University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences 1. Motivation Lab 3 Verilog Simulation Mapping In this lab you will learn how to use

More information

Introduction to WebPACK 5.2 for FPGAs. Using Xilinx WebPACK Software to Create FPGA Designs for the XSB-300E Board

Introduction to WebPACK 5.2 for FPGAs. Using Xilinx WebPACK Software to Create FPGA Designs for the XSB-300E Board Introduction to WebPACK 5.2 for FPGAs Using Xilinx WebPACK Software to Create FPGA Designs for the XSB-300E Board Release date: 10/27/2003 All XS-prefix product designations are trademarks of XESS Corp.

More information

Hierarchical Design Methodology Guide. UG748 (v14.5) April 10, 2013

Hierarchical Design Methodology Guide. UG748 (v14.5) April 10, 2013 Hierarchical Design Methodology Guide This document applies to the following software versions: ISE Design Suite 14.5 through 14.6 Notice of Disclaimer The information disclosed to you hereunder (the Materials

More information

Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17

Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17 1 Logic Implementation on a Xilinx FPGA using VHDL WWU Linux platform assumed. rev 11/01/17 The following is a general outline of steps (i.e. design flow) used to implement a digital system described with

More information

Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax

Revision: February 27, E Main Suite D Pullman, WA (509) Voice and Fax Xilinx ISE WebPACK VHDL Tutorial Revision: February 27, 2010 215 E Main Suite D Pullman, WA 99163 (509) 334 6306 Voice and Fax Overview This tutorial provides simple instruction for using the Xilinx ISE

More information

Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial

Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial 1 Table of Contents Design Flow in Libero TM IDE v2.3 Step 1 - Design Creation 3 Step 2 - Design Verification

More information

Circuit design with configurable devices (FPGA)

Circuit design with configurable devices (FPGA) 1 Material Circuit design with configurable devices (FPGA) Computer with Xilinx's ISE software installed. Digilent's Basys2 prototype board and documentation. Sample design files (lab kit). Files and documents

More information

Field Programmable Gate Array

Field Programmable Gate Array Field Programmable Gate Array System Arch 27 (Fire Tom Wada) What is FPGA? System Arch 27 (Fire Tom Wada) 2 FPGA Programmable (= reconfigurable) Digital System Component Basic components Combinational

More information

Tutorial on FPGA Design Flow based on Xilinx ISE WebPack and ModelSim. ver. 2.0

Tutorial on FPGA Design Flow based on Xilinx ISE WebPack and ModelSim. ver. 2.0 Tutorial on FPGA Design Flow based on Xilinx ISE WebPack and ModelSim ver. 2.0 Updated: Fall 2013 1 Preparing the Input: Download examples associated with this tutorial posted at http://ece.gmu.edu/tutorials-and-lab-manuals

More information

ELEC 204 Digital System Design LABORATORY MANUAL

ELEC 204 Digital System Design LABORATORY MANUAL ELEC 204 Digital System Design LABORATORY MANUAL : Introductory Tutorial For Xilinx ISE Foundation v10.1 & Implementing XOR Gate College of Engineering Koç University Important Note: In order to effectively

More information

Timing Analysis in Xilinx ISE

Timing Analysis in Xilinx ISE Timing Analysis in Xilinx ISE For each design which is to be implemented, constraints should be defined to get predictable results. The first important class of constraints was already introduced in the

More information

ProASIC PLUS FPGA Family

ProASIC PLUS FPGA Family ProASIC PLUS FPGA Family Key Features Reprogrammable /Nonvolatile Flash Technology Low Power Secure Single Chip/Live at Power Up 1M Equivalent System Gates Cost Effective ASIC Alternative ASIC Design Flow

More information

ECEN 449 Microprocessor System Design. FPGAs and Reconfigurable Computing

ECEN 449 Microprocessor System Design. FPGAs and Reconfigurable Computing ECEN 449 Microprocessor System Design FPGAs and Reconfigurable Computing Some of the notes for this course were developed using the course notes for ECE 412 from the University of Illinois, Urbana-Champaign

More information

101-1 Under-Graduate Project Digital IC Design Flow

101-1 Under-Graduate Project Digital IC Design Flow 101-1 Under-Graduate Project Digital IC Design Flow Speaker: Ming-Chun Hsiao Adviser: Prof. An-Yeu Wu Date: 2012/9/25 ACCESS IC LAB Outline Introduction to Integrated Circuit IC Design Flow Verilog HDL

More information

Best Practices for Incremental Compilation Partitions and Floorplan Assignments

Best Practices for Incremental Compilation Partitions and Floorplan Assignments Best Practices for Incremental Compilation Partitions and Floorplan Assignments December 2007, ver. 1.0 Application Note 470 Introduction The Quartus II incremental compilation feature allows you to partition

More information

RTL Coding General Concepts

RTL Coding General Concepts RTL Coding General Concepts Typical Digital System 2 Components of a Digital System Printed circuit board (PCB) Embedded d software microprocessor microcontroller digital signal processor (DSP) ASIC Programmable

More information

Spiral 2-8. Cell Layout

Spiral 2-8. Cell Layout 2-8.1 Spiral 2-8 Cell Layout 2-8.2 Learning Outcomes I understand how a digital circuit is composed of layers of materials forming transistors and wires I understand how each layer is expressed as geometric

More information

Building Combinatorial Circuit Using Behavioral Modeling Lab

Building Combinatorial Circuit Using Behavioral Modeling Lab Building Combinatorial Circuit Using Behavioral Modeling Lab Overview: In this lab you will learn how to model a combinatorial circuit using behavioral modeling style of Verilog HDL. You will model a combinatorial

More information

Virtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued)

Virtex-II Architecture. Virtex II technical, Design Solutions. Active Interconnect Technology (continued) Virtex-II Architecture SONET / SDH Virtex II technical, Design Solutions PCI-X PCI DCM Distri RAM 18Kb BRAM Multiplier LVDS FIFO Shift Registers BLVDS SDRAM QDR SRAM Backplane Rev 4 March 4th. 2002 J-L

More information

DESIGN OF IEEE TAP CONTROLLER IP CORE

DESIGN OF IEEE TAP CONTROLLER IP CORE DESIGN OF IEEE 1149.1 TAP CONTROLLER IP CORE Shelja A S 1, Nandakumar R 2 and Muruganantham C 3 1 Department of Electronics and Communication Engineering, NCERC. sheljaas@gmail.com 2 Assistant scientist/engineer,

More information

Workspace for '4-FPGA' Page 1 (row 1, column 1)

Workspace for '4-FPGA' Page 1 (row 1, column 1) Workspace for '4-FPGA' Page 1 (row 1, column 1) Workspace for '4-FPGA' Page 2 (row 2, column 1) Workspace for '4-FPGA' Page 3 (row 3, column 1) ECEN 449 Microprocessor System Design FPGAs and Reconfigurable

More information

EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007

EE178 Lecture Module 2. Eric Crabill SJSU / Xilinx Fall 2007 EE178 Lecture Module 2 Eric Crabill SJSU / Xilinx Fall 2007 Lecture #4 Agenda Survey of implementation technologies. Implementation Technologies Small scale and medium scale integration. Up to about 200

More information

Evaluation of the RTL Synthesis Tools for FPGA/PLD Design. M.Matveev. Rice University. August 10, 2001

Evaluation of the RTL Synthesis Tools for FPGA/PLD Design. M.Matveev. Rice University. August 10, 2001 Evaluation of the RTL Synthesis Tools for FPGA/PLD Design M.Matveev Rice University August 10, 2001 Xilinx: Foundation ISE Design Entry: VHDL, Verilog, schematic, ABEL Synthesis: Xilinx XST, Synopsys FPGA

More information