VHDL CODE FOR SINGLE BIT ERROR DETECTION AND CORRECTION WITH EVEN PARITY CHECK METHOD USING XILINX 9.2i

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1 VHDL CODE FOR SINGLE BIT ERROR DETECTION AND CORRECTION WITH EVEN PARITY CHECK METHOD USING XILINX 9.2i Vivek Singh, Rahul Kumar, Manish Kumar Upadhyay Dept. of Electronics & Communication Engineering.. Siliguri Institute Of Technology, Siliguri, West Bengal, India. s: Abstract Single bit error detection and correction can be done through hamming code. Hamming code can be made with either even parity or odd parity check method. The information signal can get corrupted in the process of transmission which can lead to wrong information reception. In this paper, we have used even parity check method for encrypting the information signal and forming the hamming code. The information signal is first encrypted and then transmitted using some transmission media which may be corrupted in the process. The receiver receives the signal and detects and corrects the signal using even parity check method. 11 bit information signal which is encrypted to form 15 bit hamming code where 4 bits are the redundant bit which is transmitted. And at the receiver, it is decrypted to get the original 11 bit information signal. The VHDL code for the transmitter and receiver is written and simulation of the transmitter and receiver code using Xilinx 9.2 simulator is done. I. INTRODUCTION In communication system the information signal is send through transmitter and is transmitted through some random media. In the process of transmission the information gets corrupted, so we get a signal at the receiver which is different than the original information signal. The general idea for achieving error detection and correction is to add some redundancy (i.e., some extra data) to a message, which receivers can use to check consistency of the delivered message, and to recover data determined to be corrupted. The information k bits is encrypted using even parity check method to form hamming code of n bits. The information signal is added with redundant bits r to form the code this code is then transmitted. n= k + r (1) The receiver receives the code and corrects it to get the original k bits information signal. VHDL code is written for the transmitter and receiver which is simulated through Xilinx 9.2i simulator. VHDL (VHSIC hardware description language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language. Xilinx ISE 9.2i (Integrated Software Environment) is a software tool produced by Xilinx for synthesis and analysis of HDL designs, which enables the developer to synthesize ("compile") their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with the programmer. VLSI Trainer Kit is very useful for the VLSI design engineer to verify and experience the design functionality in real life condition for PLD devices. Here we have used it for CPLD device. It consists of Macro cells. The function of these devices is similar to PAL with programmable switch matrix. These devices consist of flash memory thus the configuration is retained even in the absence of power supply. II. HAMMING CODE Hamming codes are the codes used in communication for error free transmission of information. Hamming codes can detect up to two and correct up to one bit errors. Hamming code is formed by adding the information and redundant bits i.e, n= k + r. The size of the redundant bit is determined by the formula 2 r k+ r+ 1 (2) The code is represented by (n, k) code where n is the codeword length and k is datalength. We can use this formula for calculating the number of redundancy bits. A very common hamming code is (7, 4) it contains 4 bit information and 3 bit redundancy. Redundancy is added at the encoder to form the codeword and will be removed at the decoder after getting the correct sequence and the desired information will be the final output. We calculate the redundant bits according to the information bits and place the bits in the codeword in positions given by the sequence, 2 0, 2 1, 2 2, 2 3, 2 4,.. 2 r-1,where r is the number of redundancy bits. (3) The redundant bits can be calculated either by Even parity check method or Odd parity check method. Here in this paper we have we have used even parity check method for the Hamming Encoder and Decoder. 49

2 Here for a test purpose we have taken 11 bit information signal and 4 bit redundancy is required to form a 15 bit codeword. And we have calculated the redundancy by even parity check method and will be at the 1 st, 2 nd, 4 th, and 8 th position bit of the codeword. III. CALCULATION OF REDUNDANCY AT ENCODER We have used even parity check method for calculating redundancy. The value of redundancy bit can be finding by XORING of different location of information data bit for different redundancy bit. the property of XOR gate is that if number of one`s are even in input its shows the output zero else its shows output one. Let the number information bits is k and the corresponding redundancy is r and the codeword length n= k + r, So the bit positions of the redundancies in codeword will be, 2 0, 2 1, 2 2, 2 3, 2 4,.. 2 r-1.the values of the redundancies can be given by x-or operation of the information bits present at the positions alternately in codeword for r1 and taking two consecutive leaving next two and so for r2. Similarly we take 2 t bits and left next 2 t for r(t). r1: k1 x-or k2 x-or k4 x-or k5 x-or k7 x-or k9 x-or k11 r2: k1 x-or k3 x-or k4 x-or k6 x-or k 7 x-or k10 x-or k11 r4: k2 x-or k3 x-or k4 x-or k8 x-or k9 x-or k10 x-or k11 r8: k5 x-or k6 x-or k7 x-or k8 x-or k9 x-or k10 x-or k11 (5) The value of r (1) is 1(the number of one`s are 3) The value of r (2) is 0(the number of one`s are 4) The value of r (4) is 0(the number of one`s are 4) The value of r (8) is 0(the number of one`s are 6) Therefore the final output sequence of the encoder becomes Then we download the program in the VLSI kit and provide the input by switching the LEDSs and verify the output. VHDL code for source end shown in given below Xilinx ISE 9.2i project navigator window. So the calculation for redundancies can be easily done by x-or operation of the above information bit positions, r1: k1 x-or k2 x-or k4 x-or k5 x-or k7 x-or k9 x-or k11 x-or k12 x-or k14 x-or r2: k1 x-or k3 x-or k4 x-or k6 x-or k 7 x-ork10 x-or k11 x-or k13 x-or k14 x-or.... r4: k2 x-or k3 x-or k4 x-or k8 x-or k9 x-or k10 x-or k11 x-or k15 x-or. Fig 1:VHDL code for even parity check method at source r8: k5 x-or k6 x-or k7 x-or k8 x-or k9 x-or k10 x-or k11 x-or r16: k12 x-or k13 x-or k14 x-or k15 x-or. (4) So, the value of redundancy can be calculated in the same way depending upon the number of redundancies. IV. CALCULATION OF REDUNDANCY WITH 11 BIT INFORATION SIGNAL The number of redundancy bits for 11 bit information will be 4. The redundancies will be r1, r2, r4, r8. Let the 11 bit information signal be , so the value of redundancies become, Fig 2: Simulation window shows input wave form for source end in binary format. 50

3 redundancy bits, which is then altered that is not operation is done on that bit and then the redundant bits are eliminated from the corrected signal to get the original information signal. The error position for t redundant bits can be represented as err = err(t).err(5) err(4) err(3) err(2) err(1) (6) err(1) = 1 x-or 3 x-or 5 x-or 7 x-or 11 x-or 13 x-or 15 x-or 17 x-or 19 x-or err(2)= 2 x-or 3 x-or 6 x-or 7 x-or 10 x-or 11 x-or 14 x-or 15 x-or 18 x-or 19 x-or.... err(3)= 4 x-or 5 x-or 6 x-or 7 x-or 12 x-or 13 x-or 14 x-or 15 x-or 20 x-or err(4)= 8 x-or 9 x-or 10 x-or 11 x-or 12 x-or 13 x-or 14 x- or 15 x-or, err(5)= 16 x-or 17 x-or 18 x-or 19 x-or 20 x-or.. (7) Fig 3: Simulation window shows output wave form for source end in binary format. Fig 4: VLSI Kit Showing Results of Encoder V. CALCULATION OF ERROR BIT POSITION AT DECODER VI. CALCULATION OF ERROR WITH THE RECEIVED 15 BIT CODEWORD In the process of transmission let the 9 th position gets corrupted. So, the received sequence becomes We calculate the error bit position for this codeword by the process as above stated, err(1) = 1 x-or 3 x-or 5 x-or 7 x-or 11 x-or 13 x-or 15. err(2) = 2 x-or 3 x-or 6 x-or 7 x-or 10 x-or 11 x-or 14 x- or 15. err(3) = 4 x-or 5 x-or 6 x-or 7 x-or 12 x-or 13 x-or 14 x- or 15. err(4) = 8 x-or 9 x-or 10 x-or11 x-or 12 x-or 13 x-or14 x-or 15 (8) err(1) = 1 (the number of one`s are 5 ) err(2) = 0 (The number of one`s are 4) err(3) = 0 (The number of one`s are 4 ) err(4) = 1 (The number of one`s are 7) Therefore the error position becomes err = 1001 i.e, the 9 th position is corrupted, so the not operation is done with that bit. So the corrected code becomes Then we eliminate the redundant bits i.e,1 st, 2 nd, 4 th, and 8 th bit. Therefore the final 11 bit output becomes which is the desired original information signal. The codeword from the output is transmitted through some transmission media. In the meanwhile let a bit gets corrupted and the corrupted sequence is received by the receiver. The error bit position can be calculated by the same even parity check method. The position is calculated in binary sequence that will be equal to the number of Then we download the program in the VLSI kit and provide the input by switching the LEDSs and verify the output. 51

4 Fig 5: VHDL code for destination end shown in given below Xilinx ISE 9.2i project navigator window. Fig 8: VLSI Kit Showing Results of Decoder VII. ADVANTAGES & APPLICATIONS If we use the correcting codes no resending of data is required as it will automatically detect the error and correct it. We can use transmitter of higher bit capacity no need to break the data into smaller section. So it speeds up the communication. Application of the VHDL is very effective as it is much easier to write the codes. These error correcting techniques are used in many applications as in mobile communication, storage devices, television, satellite communications and all other communications. VIII. CONCLUSION Fig 6: Simulation window shows input wave form for destination end in binary format. We see from this paper how we can use the even parity check method for any sequence of information. And we have shown it for 11 bit information signal. It speeds up the communication as we can encode the total information as a whole and send as one, there is no need for splitting. And using the same parity method at the destination we can successfully recover the original information sequence. The circuitry for this is also reduced as it makes the detection and correction becomes easier and using the VLSI makes it much more efficient. IX. REFERENCES Fig 7: Simulation window shows output wave form for destination end in binary format. [1] 30 Bit Hamming code for error detection and correction with even parity and odd parity check method by using VHDL published in IJCA( ) Volume 35 No.13, December [2] Data communication and networking, Behrouz A. Forouzan, 2nd edition Tata McGrawHill publication. [3] Xilinx Training Course Listing, available at [4] VHDL Primer, by J. Bhasker, 2 nd Edition. 52

5 [5] Error detection and correction: correction [6] VHDLtutorial: [7] VLSI Trainer Kit: 53