Design of Serial Interface for Neuron Base Smart Sensors

Transcription

1 Design of Serial Interface for Neuron Base Smart Sensors B. Donchev, Member, IEEE, K. Hristov, Member, IEEE, A. Cordery Member, IEEE and M. Hristov, Member, IEEE Abstract LIN interface module for neuron base smart sensors is presented in this paper, which is based on Programmable Logic Devices Implementation. Top-down approach has been used during the design stage and VHDL has been applied for the design description. Operate rates are as following: 2400 b/sec, 9600 b/sec, b/sec. The verification of this module has been tested by the Xilinx FPGA demo board. Index Terms VHDL, CPLD, Top-Down, LIN, FSM, EMI I. INTRODUCTION The LIN (Local Interconnect Network) is a serial communications protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The domain is class-a multiplex buses with a single master node and a set of slave nodes [1]. The main properties of the LIN bus are: 1) Single-master / multiple-slave concept; 2) Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as pure state machine; 3) Self synchronization without quartz or ceramics resonator in the slave nodes ; 4) Guarantee of latency times for signal transmission; 5) Low cost single-wire implementation; 6) Speed up to 20 kbit/s. The maximum baud rate is 20kbit/s, given by the EMI limitation of the single wire transmission medium. The minimum baud rate is 1kbit/s to avoid conflicts with the practical implementation of time-out periods. Only the controller node containing the Master Task is allowed to transmit the message header, and one Slave Task responds to this header. As there is no arbitration procedure, an error occurs if more than one slave responds. The fault confinement for this case has to be specified by the user depending on the application requirements. Error Detection B. R. Donchev PhD Student, Technical University-Sofia, Kliment Ohridski Str. 8, 1977, Sofia, Bulgaria (telephone: , donchev@ecad.vmei.acad.bg). M. H. Hristov, PhD, Professor, Technical University-Sofia, Kliment Ohridski Str. 8, 1977, Sofia, Bulgaria (telephone: , mhristov@ecad.vmei.acad.bg). K. H. Hristov, BSc., Technical University-Sofia, Kliment Ohridski Str. 8, 1977, Sofia, Bulgaria (telephone: , khhristov@yahoo.com). A. A. Cordery, PhD, Professor, Oxford Brookes University School of Engineering, Gipsy Lane Campus, Headington, Oxford OX30BP, UNITED KINGDOM (telephone: , aacordery@brookes.ac.uk) 1) Monitoring, the transmitter compares should with is value on the bus 2) Inverted modulo-256 checksum for the Data fields, with the carry of the MSB being added to the LSB; 3) Double-parity protection for the identifier field; Performance of Error Detection 4) All local errors at the transmitter are detected; 5) High error coverage of global protocol errors. LIN nodes are able to distinguish short disturbances from permanent failures and carry out appropriate local diagnostics and actions on failures. An acknowledgment procedure for a correctly received message is not defined in the LIN protocol. The master control unit checks the consistency of a message being initiated by the master task and being received by it s own slave task. In case of inconsistency (e.g. missing slave response, incorrect checksum etc.) the master task can change the message schedule. In case a slave has detected an inconsistency, the slave controller will save this information and provide it on request to the master control unit in form of diagnostics information. This diagnostics information can be transmitted as data in a regular MESSAGE FRAME. To reduce the system s power consumption, a LIN node may be sent into the sleep mode without any internal activity and with passive bus driver. The message that is used to broadcast a sleep mode is a dedicated command. The bus is recessive during sleep mode. There are five different message error types specified. 1) Bit-Error A unit that is sending a bit on the bus also monitors the bus. A BIT_ERROR has to be detected at that bit time, when the bit value that is monitored is different from the bit value that is sent. 2) Checksum-Error A CHECKSUM_ERROR has to be detected if the sum of the inverted modulo-256 sum over all received data bytes and the checksum does not result in 0xFF. 3) Identifier-Parity-Error A parity error in the identifier (i.e. corrupted identifier) will not be flagged. Typical LIN slave applications do not distinguish between an unknown but valid identifier, and a corrupted identifier. However, it is mandatory for all slave nodes to evaluate in case of a known identifier all 8 bits of the ID-Field and distinguish between a known and a corrupted identifier. 4) Slave-Not-Responding-Error A NO_RESPONSE_ERROR has to be detected if the MESSAGE FRAME is not fully completed within the maximum length T FRAME_MAX by any slave task upon transmission of the SYNCH and IDENTIFIER fields. 5) Inconsistent-Synch-Field-Error

2 An Inconsistent-Synch-Field-Error has to be detected if a slave detects the edges of the SYNCH FIELD outside the given tolerance. 6) No-Bus-Activity A No-Bus-Activity condition has to be detected if no valid SYNCH BREAK FIELD or BYTE FIELD was received for more than T TIMEOUT since the reception of the last valid message. II. PHYSICAL IMPLEMENTATION OF LIN INTERFACE MODULE A. Operation modes The connection block diagram is shown on fig.1. There are one master and one slave units on it. Fig. 1 Connection block diagram Both of them can be linked each other by additional driver integrated circuits. Each of the modules has interface of its own for the connection with microcontroller. Information on the bus is sent in fixed format messages of selectable length. Every MESSAGE FRAME (fig.2) comprises between two, four, or eight bytes of data plus three bytes of control and safety information. The bus traffic is controlled by a single master. Each message frame starts with a break signal and is followed by a synchronization field and an identifier field, all sent out by a master task. The slave task sends back the data field and the check field. Fig. 2 Message frame format The designed module can be embedded in smart neuron sensors, drivers or microcontrollers as own internal block for communication over LIN network. The internal structure of the MaCU and SCU are depicted on the fig3. The module has been build of four sub-modules as follows: ContrFSM_McU, LIN_IO_McU, FCB_McU, LIN_Err_McU. The first one is the main control design block. It supervises the other functional blocks. The second block ensures the correct data transfer. The third one is unit for post error operations. The last one is error detection unit. There are some specific conditions which concern master and slave mode. Fig. 3 Internal structure of the MaCU and SCU System clock frequency rate is equal to 8 MHz. B. Master Control Unit The block has an input for initial set condition. The transfer among the other modules is performed by two 8 bit buses. The first one is output bus (DataBusOut), and the second one is input bus (DataBusIn). The control signal NewDSys has active level(logical one) when there are valid data on the bus. This is a signal for block read enable. When the data has been read the control signal NewDLIN turns into logical 1. When the valid data are taken out from the unit the signal NewDLIN is set to logical 0 and waits NewDSys to turn into logical 1. The Table 1. contains the signals description of the unit. TABLE 1 SIGNAL DESCRIPTION OF MASTER CONTROL UNIT Signal Description BaudR Determines the rate of the data transfer Bit_r TxD signal monitoring Clk Main system clock input Rst Initial set input ValidMode Valid data control signal for Mode input Mode Input mode control signal NewDSys Receive acknowledge signal DataBusIn Data input bus DataBusOut Data output bus RxD LIN network receive data signal SCU_N Receive slave unit number ErrPin Error detection signal NewDLIN Valid information signal TxD LIN network transmit data signal WakeUpSgnl Wakeup signal detection WrongID Wrong ID signal detection When a valid data has been taken out from the MaCU the signal NewDLIN is set to logical 1, waiting for logical 1 on the line NewDSys. In case of sleep mode the unit is not active. During the active state MaCU sends data frame to SCUs that is called Master Task. If MaCU generates Master Task, the SCU responds with data frame called Slave Task. There is capability of recognition of entry ID. If the ID is not valid the unit activates Wrong ID signal. Operating transfer rate is determined by two bits of BoudR bus signal. TxD and RxD lines are LIN s data interface.

3 1) ContrFSM_MaCU- The behavior of this module is thoroughly described in the flow chart given below(fig.4). Fig. 5 Flow state chart diagram of LIN_IO_ MaCU. 3) LIN_Err_MaCU The purpose of this module is to detect from errors during the data transfer. Its architecture consists of Internal State Machine, Verification Active Data Block, Message Duration Measurement Block, Error Coding Block. Fig. 4 Flow state chart diagram of ContrFSM_MaCU. After the RESET condition state and active state of the ValidMode signal, the internal register, determined the operating mode has been loaded. The next condition is START. During this state, depending of the value of the internal register, the module switches into two possible states (SLEEPM or FETCH_DSN). During the state FETCH_DSN the data has been read from system unit inp ut. After that in the next state ID_CHECK the input ID is verified. If the received ID is valid the slave unit sends Slave Task Data to the master unit. 2) LIN_IO_MaCU If the system is not in the Sleep Mode, a command for a new massage is waited. If it is received, the synchronization between the units take place. The rate of the transfer is determined by the value written in the internal configuration register. Flow state chart diagram is shown on the fig. 5. 4) FCB_MaCU Depending of the of error type this module determines reaction of the unit. During the operation time, the master unit checks the number of the errors and their location. The limitation of errors number - 64 is adopted as is recommended in the specification. If the same error emerges 64 times an user defined error handling procedure may take place on the application level. C. The Slave Control Unit It s identical module like the Master Control Unit but there are some slight differences. The ID field determines if the unit will work as a master or a slave. There is a requirement during the slave mode operation which is assignment for speed transfer. This assignment is given by master control unit. Sleep Mode regime is also supported by slave control unit. The synchronization of the slave is made according to the master clock frequency. The description of signals is given in the Table 2 TABLE 2 SIGNAL DESCRIPTION OF SLAVE CONTROL UNIT Signal Description BRMode Determines the rate of the data transfer BaudRSet Valid BRMode data signal Bit_r TxD signal monitoring Clk Main system clock input DataBusIn Data input bus Mode Input mode control signal NewDSys Receive acknowledge signal Rst Initial set input RxD WakeUp DataBusOut LIN network receive data signal Error flag Data output bus

4 ErrPin NewDLIN TxD WakeUpFail WakeUpSgnl Error detection signal Valid information signal LIN network transmit data signal Error WakeUp decoding signal WakeUp signal detection 1) ContrFSM_SCU The purpose of this module is the same as the Master Module but the main differences are as follows: There are two additional functions. The first one is direction transfer determination. The second one is speed operation transfer fetch. The structure is based on finite automate design. The state flow chart of the unit is depicted on Fig. 6. Fig. 7 Flow state chart diagram of LIN_IO_ScU. 3) LIN_ERR_SCU The purpose of the module is to determine the type and the location of the error. This is achieved by the aid of internal processes which work in parallel with the base control process. There is a specific counter destined for length message measurement. 4) FCB_SCU The main difference from FCB_MCU is that the unit is supplied with message slave receiving error counter. It is not activated in case of slave not responding error. III. SIMULATION RESULTS AND SYNTHESIS Fig. 6 Flow state chart diagram of ContrFSM_ScU. 2) LIN_IO_SCU There is a similarity between LIN_IO_SCU and LIN_IO_MaCU. The purpose to both of them is to transmit and receive information. They have different structures, determined by the destination of the unit. The flow chart is shown on fig. 7. Fig. 8 Data transfer from SCU to MaCU

5 Fig. 9 Transmiting of Master Task with CheckSum Error Fig. 12 SCU synthesis results Fig. 10 Simulation results of Sleep Mode command Fig.11 MaCU synthesis results IV. CONCLUSION The goal of this paper is to present an implementation of LIN protocol for Neuron base smart sensors in programmable logic areas. The physical connection among participants in LIN network is done by LIN transceivers, which make available the communication among all devices in a single common network where there are always one Master Control Unit and up to sixteen Slave Control Units. The basic inner architectures of a master and slave units are the same, as there are specific functions in each one of these two units that has to be fulfilled in design. As an additional function of the module, to reduce the system s power consumption, a LIN node may be sent into the sleep mode without any internal activity and with passive bus driver. The basic construct blocks of the developed design are: ContrFSM, LIN_IO, FCB, LIN_Err. The ContrFSM block is a hardware model of a state machine determining the different states in which the device can be set in the process of work. It also accomplishes the communication with the upper layer of LIN ISO model (LLC layer). The LIN_IO executes the interface with LIN network. The main task of LIN_Err block is to identify the situations in which there is a mistake. It is in direct connection with FCB block, which determines the reaction of the system in accordance with the type of the mistake. There are six types of mistakes. The whole process of development was made with hardware description language VHDL. The top-down method has been used in order to decrease the design time. The presented module meets the requirements of LIN Protocol Specification, Revision 1.2 from November 17, 2000, which is the latest up to now. REFERENCES [1] LIN Specification, Revision 1.2, Nov 17, 2002; [2] LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS AN1278 Application Note, 2002 STMicroelectronics [3] Local Interconnect Network (LIN) Demonstration Motorola Semiconductor, Application Note AN2103, January 2002 [4] J.Will Speks, Motorola GmbH, Munich Antal Rajnak, Volcano Communication Technologies, LIN protocol, development tools, and software inerfaces for local interconnect network in vehicles. [5] Christopher A. Lupini, Mutiplex bus progression Delphi Delco Electronics System [6] Roth, H. Charles Digital system design using VHDL, PWS Publishing Copmany, 1998 [7] Philips smart power solitions, Philips Semiconductors, February 2002