Advanced module: Video en/decoder on Virtex 5

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1 Advanced module: Video en/decoder on Virtex 5

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3 Content 1. Advanced module: Video en/decoder on Virtex Introduction to the lab environment Remote control Getting started with the Xilinx design flow Write VHDL-files Verify functionality with simulation in Modelsim Implement design using the Tcl-based Xilinx Flow Verify the design on the FPGA-board Version from:

4 1. Advanced module: Video en/decoder on Virtex 5 Requirements for the lab: Windows PC with administrator rights Good knowledge in VHDL In the course "FPGA-Online Advanced Course with VHDL" you will learn advanced techniques to program an FPGA. These techniques include: Script-based synthesis and loading of the FPGA, the use of the high speed interface PCI Express, and the use of special hardware blocks on the FPGA. The techniques are applied on the example application of hardware accelerated video compression and decompression. The experimental setup consists out of a standard PC with a build-in XUPV5-platform (more information can be found here [ ). The two systems are connected over the PCI Express bus. With this connection, a high speed hardware-software communication is possible that enables us to send a video stream in real-time to the FPGA and back. On the FPGA the video stream is encoded using different techniques in real-time. Since we are not building a standardized video codec, the stream is also decoded on the board. It is then send back to the PC, where we can display the result. Learning Objectives Learn how to build an advanced design for a high-performance FPGA. As an example throughout the lab, we want to build a modular real-time video compression system based on a Xilinx Virtex 5 FPGA. Get familiar with the Hardware/Software communication PCI Express, which allows a high-speed communication between a standard PC and an FPGA. Use the hard-wired resources such as XtremeDSP or BlockRAM to speed up your FPGA design. - Version from:

5 1.1. Introduction to the lab environment In this unit, the experimental setup is explained. You will learn the basic steps to control the pc and the FPGAboard. The setup of the lab is shown in the above figure. The main components are four standard PCs. Inside each of them an FPGA board is connected to the PCIe interface. The FPGA boards can be programed by a central server PC. This has the advantage, that the FPGA board can be programed anytime independent from the current status of the host PC. For on-board debugging the FPGA boards serial connection is connected to the host PC. - Version from:

6 Remote control There are two possibilities to connect to the lab pc. The first one is only possible when the operation system, i.e. SUSE linux, is running correct. It is using the secure shell, short ssh. One way to connect via ssh is using the software putty [ You should be provided with a username, a password and an ip address to your assigned pc. Using this information you can log into your pc. The second way is to use Intel Active Management Technology. It provides a way to take operating system independent remote control of a PC. There are two ways to access it: Web front end and Intel software. The web front end can be accessed by browsing address": Or, you can download the Manageability Developer Tool Kit [ After installing it you should be able to start the Manageability Commander Tool. Here, you can use again the same login information as for ssh. The most interesting function of this tool is found under the "remote control" tab: the function "KVM Viewer Redirect Port". Here, you can take full remote control and see the status of your system. This is especially useful when restarting the pc. A screenshot is provided in the following figure. - Version from:

7 1.2. Getting started with the Xilinx design flow The Xilinx design flow In order to create an FPGA design, Xilinx suggests the design flow shown in the above Figure [Page 5]. The design flow comprises the following steps: 1. Design Entry and Synthesis In this step of the design flow, you create your design using a schematic editor, a hardware description language (HDL) for text-based entry, or both. In a Functional Simulation your HDL can be verified. If you use an HDL for text-based entry, you must synthesize the HDL file into an EDIF file or, if you are using the Xilinx Synthesis Technology (XST) GUI, you must synthesize the HDL file into an NGC file. - Version from:

8 2. Design Implementation By implementing to a specific Xilinx architecture, you convert the logical design file format, such as EDIF, that you created in the design entry and synthesis stage into a physical file format. The physical information is contained in the native circuit description (NCD) file for FPGAs and the VM6 file for CPLDs. Then you create a bit stream file from these files and optionally program a PROM or EPROM for subsequent programming of your Xilinx device. 3. Design Verification Using a gate-level simulator or cable, you ensure that your design meets your timing requirements and functions properly. In our first lab, we want to take the following steps: 1. Write the VHDL-files (entry) 2. Verify functionality with simulation in Modelsim (synthesis and verification) 3. Implement design using the Tcl-based Xilinx Flow (synthesis and implementation) 4. Verify the design on the FPGA-board (physical verification) Learning Objectives Build a simple serial connection between the FPGA and the PC. Get familiar with the simulation in Modelsim Create a first bitfile for the FPGA Run the bitfile on the FPGA - Version from:

9 Write VHDL-files Our first communication between the PC and the FPGA will be a simple serial connection. The communication should use the universal asynchronous receiver/transmitter(uart) protocol RS232. RS232 is a standard for serial binary single-ended data communication. Serial means that only one bit is transfered at one time instance. Asynchronous means, that the communication partners don't have a common clock. The communication is structured in messages. One of it is shown in the following Figure. Typical trace of a transmission using the RS232 protocol The standard describes the physical setup and the bit representation, but things such as bit rate, character framing and communications protocol are left open. So the communication partners, here the FGPA and the PC, have to agree on something. Over time, the following setup has established itself because of its simplicity but still good performance: Bit rate: bit/s Data length: 8 bit Parity bit: None Number of stop bits: 1 For many tools this setup is abbreviated " N-1". In the following, we want to use this setup to create an FPGA design that can read characters written on the serial port and write them back with small changes. In the folder /scratch-local/fpgaonline/lab01, you will find the necessary files to complete this lab. Simply copy these file to your home directory in order to edit them. "top.vhd" describes the top-level entity. The I/O-ports of this entity are the actual I/0-Pins on the FPGA. Normally, this file only contains connections and no logic, but for our first simple design, we will include some logic here. "rs232.vhd" describes our actual communication module. The interface can be described as follows: Receive serial data from pc: - Version from:

10 DATAOUT : out std_logic_vector(7 downto 0); -- 8 bit data word that was received via rs232 VALID : out std_logic; -- signals one clock cycle that DATAOUT can be read RX : in std_logic; -- io read port (physical connection) Send serial data to pc: DATAIN : in std_logic_vector(7 downto 0); -- 8 bit data word that should be send via rs232 WREN : in std_logic; -- write enable signals that DATAIN is should be read, only possible when READY=1 READY : out std_logic;-- ready for new tx data TX : out std_logic; -- io write port (physical connection) Reset and clock signals: RESET : std_logic; -- synchronous reset CLK : std_logic A receive sequence starts with receiving a serial message over the RX-port. When the message is complete, the receive data word is put on DATAOUT and signaled for one clock cycle with a logical one on VAlID. The send sequence can only start when the rs232 module signals read with READY = 1. If ready the data to send can be put on the DATAIN port and signaled with WREN. The rs232 module buffers the data and sends it serially over TX. The state machine for the receive process is already included. Read through the code and implement the state machine for the transmit process. Keep in mind that reading a logical '0' from the RX port means positive voltage signal is received. Also, writing a logical '0' to the TX port means sending a positive voltage signal. - Version from:

11 Verify functionality with simulation in Modelsim In order to test your design, you have to create a test bench. The name comes from the real hardware test bench, where a device under test is stimulated with signal generators and the output is observed by probes. Using a simulated VHDL test bench has the big advantage that you can actually look inside the device under test and find functional errors much faster. A VHDL test bench is similar to normal VHDL file. It consists out of an architecture body containing an instance of the device under test or several devices under test and processes that generate signals that stimulate these devices. In contrast to a normal VHDL entity, a test bench doesn't have any input or output ports. "tb_rs232.vhd" provides the basic structure of our first test bench. We want to check whether the written state machine for the transmit process is working correct. Write a stimulation for our rs232 module to send 8 bit with up counting value. This means you send ' ', ' ', ' '... ' '. Of course, you have to keep the specification of the interface in mind: Wait until READY is "1", put the value to DATAIN and set WREN to "1". In our lab, we are using Modelsim to simulate our FPGA design. You need to install it locally on your PC. A free non-commercial student version is available at Modelsim [ At the moment, only a windows based version is freely available. After installing Modelsim, do the following steps: create a new project "rs232" add the existing files (rs232.vhd, tb_rs232.vhd) to your project compile all (Compile -> Compile All) simulate (Simulate -> Start Simulation) choose tb_rs232 as Design Unit the sim window opens select work -> tb_rs232 add all signals to the wave form (Add -> To Wave -> All items in region and below) the Wave window opens start the simulation for 10 us (see the following figure) check whether the waveform is as expected - Version from:

12 Screenshot of the waveviewer in Modelsim If you ran through these steps without any errors then you are either already a Modelsim expert or you were very lucky. If you hit any problems, here are some hints to solve them. If you have problems with creating a project or starting the simulation you can refer to the built-in documentation of Modelsim (Help -> PDF Documentation -> Tutorial is a good start). Make sure that your VHDL files compile without errors and warnings. If you can't see anything happen try to run the simulation longer or use the Zoom Full button (see above figure). Now, that we have a fully functional RS232 module, we want to use it on the FPGA. It is necessary to define an entity as a top entity, where the I/O-ports represent the pins on the FPGA. We could use our RS232 module as top entity, but then data that should be read/sent would also need to be sent/read from an external source. Instead, it would be more useful to generate the data read/sent inside the FPGA. A wrapper entity is needed that contains the RS232 module and a little logic to generate data. Instead of just simple generating data, we want to make a test design which receives a byte from the serial interface from the pc, inverts one bit and sends it back. In this way, we can easily use a terminal program on the pc to test our design. On terminal programs like minicom the ascii code that you type in your keyboard is sent over the serial interface. The received bytes are interpreted as ascii code and displayed as such. Further information on ascii encoding is given at Wikipedia [ The basic structure for the provided "top.vhd" contains the entity declaration and the instantiation of the rs232 module. You now have to create a process that receives data from the rs232 module inverts the bit that converts a capital letter to a lower case letter and vice versa. You can verify your design by creating a new test bench tb_top.vhd. Take the previous test bench tb_rs232.vhd as basis and add the top module. The rs232 module - Version from:

13 represents the behaviour of our pc. This means we need to connect the tx signal from the rs232 module to the rx signal of the top module and vice versa. Simulate this test bench on Modelsim. You should see that the correct data is sent to from the rs232 module to the top module, one bit is inverted, send back to the rs232 module and received. Especially look at /tb_top/rs232_inst/datain and /tb_top/rs232_inst/dataout which should have some delay and one bit inverted. - Version from:

14 Implement design using the Tcl-based Xilinx Flow In the previous labs you used the Xilinx ISE GUI, but in this more advanced lab we want to optimize and automate the design creation. Tool Command Language (Tcl) is an easy to use scripting language and an industry standard popular in the electronic design automation (EDA) industry. The Xilinx Tcl command language is designed to complement and extend the ISE graphical user interface (GUI). For new users and projects, the GUI provides an easy interface to set up a project, perform initial implementations, explore available options, set constraints, and visualize the design. Alternatively, for users who know exactly what options and implementation steps they wish to perform, the Xilinx Tcl commands provide a batch interface that makes it convenient to execute the same script or steps repeatedly. Since the syntax of the Xilinx Tcl commands match the GUI interaction as closely as possible, Xilinx Tcl commands allow an easy transition from using the GUI to running the tools in script or batch mode. Unfortunately, the FPGA device we are using is not support by the free Xilinx Webpack. Therefore, from now on you have to work remotely on the machines in our department. Use your favorite command line tool to connect to your assigned PC with "ssh username@ipadress" as described in this learning object [Page 4] In the folder /scratch-local/fpgaonline/lab01/tcl, we provide the basic scripts to run through the whole design flow. Here, it is divided into three steps: 1. create the project "create_project.tcl" 2. synthesize and generate bitfile "synthesize.tcl" 3. load bitfile onto FPGA "loadfpgax" First, we will look into "create_project.tcl". Fill up the missing fields and run the script with "xtclsh create_project". Hint: The constraint file is provided "xupv5-lx110t.ucf". Second, look into "synthesize.tcl". It is not doing anything yet. Look into Xilinx Development System Reference Guide (chapter 3) [ to find the proper commands to create the bitfile from the already created project. Hint: Triggering the very last "process" will automatically do the previous steps. Third, load the bitfile "top.bit" onto the FPGA. The bitfile can be found in the "compile_directory" you set in "create_project.tcl". To do this, copy the "top.bit" to the folserver with "scp top.bit :~/". Open a new terminal and connect to the folserver via ssh. On the folserver, you can load the bitfile by running "/ opt/impact/loadfpgayournumber", for example "opt/impact/loadfpga1". The FPGAs serial interface should now respond. - Version from:

15 Verify the design on the FPGA-board As serial terminal program we want to use minicom. For more information run "man minicom". Start minicom with "minicom -s". Check if the "Serial port setup" is as described here [Page 7] (Bps/Par/Bits : N1). "Exit" the configuration window. If you now type lower case letters they should appear upper case and vice versa. Congratulations, you have build your first FPGA design using an advanced design flow. - Version from:

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