Compact Dual Block AES core on FPGA for CCM Protocol
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1 Compact Dual Block AES core on FPGA for CCM Protocol João Carlos C. Resende Ricardo Chaves 1 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
2 Outline Introduction & Motivation Digital Security Today The AES Block Cipher The CCMP Encryption mode State of the Art in AES implementations on FPGA Proposed Architecture: Description and Implementation Combining Solutions Improved Solution Result Analysis Resource requirements and performance Comparison with related State of the Art Conclusions 2 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
3 Digital Security Today Encryption Authentication Integrity Non-repudiation 3 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
4 Digital Security Today Encryption Authentication Ciphers Hash functions Higher Lvl Protocols Integrity Non-repudiation 4 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
5 Digital Security Today Encryption Authentication Ciphers Hash functions Higher Lvl Protocols Ciphers + Hash 2 cores Integrity Non-repudiation 5 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
6 Digital Security Today Encryption Authentication Ciphers Hash functions Higher Lvl Protocols Ciphers + Hash 2 cores Integrity Non-repudiation Ciphers + Cipher Modes CCM GCM 6 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
7 Digital Security Today (AES-CCM) Cipher Modes (more easily embeddable & efficient) It specifies the order in which blocks are encryption AES-CCM most common: Advanced Encryption Standard Counter with CBC-MAC 7 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
8 Digital Security Today (AES-CCM) Cipher Modes (more easily embeddable & efficient) It specifies the order in which blocks are encryption AES-CCM most common: Advanced Encryption Standard Counter with CBC-MAC Used in: IEEE (WLAN) IEEE (Broadband Wi-Fi) IPSec TLS Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
9 The AES Block Cipher Official NIST standard since 2001 FIPS bit block cipher Logic or Table implementation Shared structure for Enc/Dec Input keys of 128,192 or 256 bits 10, 12 or 14 iterative rounds 9 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
10 The Counter with CBC-MAC Protocol Original submission 2002 RFC 3610 Encryption; Authentication; Integrity for any block cipher Typically AES 10 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
11 The Counter with CBC-MAC Protocol Two stream chains Counter: non-feedback mode Counter tags for each independent Plaintext block CBC-MAC: feedback mode Chainned and dependent Plaintext encryption Cipher s decryption is not required Additional Shared Data for extra security 11 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
12 Outline Introduction & Motivation Digital Security Today The AES Block Cipher The CCMP Encryption mode State of the Art in AES implementations on FPGA Proposed Architecture: Description and Implementation Combining Solutions Improved Solution Result Analysis Resource requirements and performance Comparison with related State of the Art Conclusions 12 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
13 State of the Art in AES implementations on FPGA Chodowiec and Gaj [2003] ShiftRows performed by addressable Shift Register SubBytes performed by BRAM-based S-Boxes MixColumns performed by logic 13 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
14 State of the Art in AES implementations on FPGA Rouvroy et al. [2004] ShiftRows performed by Shift Register SubBytes & MixColumns performed by BRAM-based T-Boxes Extra InvS-Box in BRAM for decryption Embedded Key Scheduler SBOX SBOX SBOX SBOX C O L 1 C O L 2 C O L 3 C O L 4 32b SBOX SBOX SBOX SBOX COL1 COL2 COL3 COL4 32b Matrix TBOX 14 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
15 State of the Art in AES implementations on FPGA Drimer et al. [2010] ShiftRows performed by Logic Shift Register SubBytes & MixColumns by BRAM based T-Boxes XOR operations performed by Cascade of 4 DSPs 8-stage Pipeline for maximum clock frequency 15 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
16 Outline Introduction & Motivation Digital Security Today The AES Block Cipher The CCMP Encryption mode State of the Art in AES implementations on FPGA Proposed Architecture: Description and Implementation Combining Solutions Improved Solution Result Analysis Resource requirements and performance Comparison with related State of the Art Conclusions 16 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
17 Proposed Architecture: Description and Implementation Proposed Structure Combine solutions from State of the Art Improve efficiency through: Removal of DSPs Most use of LUT6 technology Improved Scheduling/Pipelining Minimize Critical Path 17 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
18 Proposed Architecture: Description and Implementation Step-by-step components Initial Whitening Keys 18 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
19 Proposed Architecture: Description and Implementation Step-by-step components Initial Whitening Keys Shift Register for AES x32 bits 19 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
20 Proposed Architecture: Description and Implementation Step-by-step components Initial Whitening Keys Shift Register for AES BRAM based T-Boxes 20 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
21 Proposed Architecture: Description and Implementation Step-by-step components Initial Whitening Keys Shift Register for AES BRAM based T-Boxes AddRoundKey and Feedback 21 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
22 Proposed Architecture: Description and Implementation Step-by-step components Initial Whitening Keys Shift Register for AES BRAM based T-Boxes AddRoundKey and Feedback Output Block Addition // Imediate load of new Block (Counter) 22 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
23 Proposed Architecture: Description and Implementation Scheduling Each block takes 9 cycles to process & re-store. There are 2 blocks = 8 Words (32 bits) 1 dead cycle = 1 register too many 23 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
24 Proposed Architecture: Description and Implementation Scheduling Each block takes 9 cycles to process & re-store. There are 2 blocks = 8 Words (32 bits) 1 dead cycle = 1 register too many Two viable solutions 24 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
25 Proposed Architecture: Description and Implementation Scheduling Each block takes 9 cycles to process & re-store. There are 2 blocks = 8 Words (32 bits) 1 dead cycle = 1 register too many Removal of the SRL ouput register Shorter propagation signal Each block takes 8 cycles to process & re-store. There are 2 blocks = 8 Words (32 bits) 0 dead cycles 25 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
26 Proposed Architecture: Description and Implementation Compact Double Block AES FPGA core. Double Input (Counter or CBC-MAC) Shift Register for Shift Rows BRAM-based TBoxes Output Stage with Final block addition Overlapping Input/Output cycles Critical Path = 1 Logic level + routing Total of 96 LUTs + 2 BRAMs (+32 isolated FFs) 26 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
27 Outline Introduction & Motivation Digital Security Today The AES Block Cipher The CCMP Encryption mode State of the Art in AES implementations on FPGA Proposed Architecture: Description and Implementation Combining Solutions Improved Solution Result Analysis Resource requirements and performance Comparison with related State of the Art Conclusions 27 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
28 Result Analysis State of the Art Comparison (double block) Round Structure Device Resources Throughput Efficiency Slices BRAMs DSPs [Gbps] [Mbps/S] El Maraghy Rolled(128b) V ,327 (2,653) 4,38 (8,75) Chaves Rolled(128b) V ,427 5,96 Bulens Rolled(128b) V ,185 5,46 Drimer Rolled(32b) V , , ,30 V5 70 1,696 24,22 This Work Rolled(32b) V ,555 30,49 S ,575 4,05 Resende Rolled(32b) V ,012 8, V ,955 8,3 Liu Unrolled V ,388 1, V ,107 1,95 de la Piedra Rolled(128b) A ,195 2,44 ECB 633 1,68 Lopez-Trejo w/ CTR Unrolled ,067 1,45 S3 0 MAC ,03 Total 2xUnrolled ,05 0,49 Algredo-Badillo 2xRolled(128b) S ,087 1,04 28 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
29 Result Analysis El Maraghy Chaves Bulens Drimer w/ DSPs Drimer w/o DSPs This Work V5 This Work V6 This Work S3 Resende V5 Resende V Slices Liu V Liu V de la Piedra 80 Lopez-Trejo ECB Lopez-Trejo w/ Lopez-Trejo MAC 1031 Lopez-Trejo Total 2154 Algredo-Badillo Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
30 Result Analysis El Maraghy 26,53 Chaves 24,27 Bulens 21,85 Drimer w/ DSPs 17,6 Drimer w/o DSPs 17,6 This Work V5 16,96 This Work V6 15,55 This Work S3 Resende V5 Resende V6 5,75 10,12 9,55 Slices/100 Throughput [Mbps/100] Liu V5 43,88 Liu V6 61,07 de la Piedra 1,95 Lopez-Trejo ECB 10,67 Lopez-Trejo w/ CTR 10,67 Lopez-Trejo MAC 10,67 Lopez-Trejo Total 10,5 Algredo-Badillo 10,87 30 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
31 Result Analysis El Maraghy 8,75 Chaves Bulens 5,96 5,46 Drimer w/ DSPs 16,45 Drimer w/o DSPs 8,3 This Work V5 24,22 This Work V6 30,49 This Work S3 4,05 Resende V5 Resende V6 8,23 8,3 Efficiency [Mbps/S] Liu V5 Liu V6 de la Piedra Lopez-Trejo ECB Lopez-Trejo w/ CTR Lopez-Trejo MAC Lopez-Trejo Total Algredo-Badillo 1,22 1,95 2,44 1,68 1,45 1,03 0,49 1,04 31 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
32 32-bit Conclusions Compact Double Block AES core on FPGA for CCMP Processing of 2 data streams 51 Slices+3 BRAMs ; 486 MHz ; 1,55 Gbps ; 30,49 Mbps/Slice Improvements (Virtex 5) Smallest 32-bit structure to date Most efficient AES structure in the state of the art Similar Throughput Resources Throughput Efficiency de La Piedra 16xDSPs -12,5% +770% +892% Drimer 4xDSPs -34% -4% +47% Drimer 0xDSPs -67% +177% 128-bit El Maraghy -76% -36% +176% 32 Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
33 Thank you! Questions? Compact Dual Block AES core on FPGA for CCM Protocol João CC Resende & Ricardo Chaves
Compact Dual Block AES core on FPGA for CCM Protocol
Compact Dual Block AES core on FPGA for CCM Protocol João Carlos Resende and Ricardo Chaves Instituto Superior Técnico, Universidade de Lisboa / INESC-ID Rua Alves Redol 9, 1000-029 Lisbon, Portugal joaocresende@tecnico.ulisboa.pt,
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