Low-Power Data Address Bus Encoding Method
|
|
- Kelly Gibbs
- 6 years ago
- Views:
Transcription
1 Low-Power Data Address Bus Encoding Method Tsung-Hsi Weng, Wei-Hao Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, and Jimmy Lu Dept. of Computer Science and Information Engineering, National Chao Tung University, HsinChu, Taiwan, ROC IP Technology Department, SOC Technology Center, Industrial Technology Research Institute, HsinChu, Taiwan, ROC Abstract-Reducing power consumption of computer systems has gained much research attention recently. In a typical system, the memory bus power constitute will over 50% of all system power; and this power is required due to bus signal transitions (0 1 or 1 0). Reducing the number of memory bus transitions is hence an effective way to reduce system power. While many techniques deal with reducing bus power on instruction address bus, only a few have been proposed for data address bus power reduction. We present an encoding scheme to reduce data address bus power consumption. In this scheme, data address bus can be frozen for sequential addresses, or inverted as appropriate for other cases. Furthermore, data addresses are classified into read addresses and write addresses, and each address set is encoded independently. Simulation results show that the overall bus line switching reduction is 26% of unencoded bus, or 14.5% of the previous T0_BI method [1]. Keywords: low-power, bus encoding, data address bus, T0_BI_1 1. Introduction The increase in complexity of system-on-chip (SoC) designs has led to the power consumption, hence cooling, and reliability problems. Power consumption is becoming one of the most important design issues especially for embedded systems. On the other hand, we are witnessing a dramatic market size increase for portable electronic devices such as mobile phones and personal digital assistants. While these products are battery-powered, plus their functional requirements due to users are even increasing, low power design for these systems hence becomes a very important research topic. In a digital computer system, the major power consumption comes from the off-chip processor-memory bus traffic, as a result of the huge capacitances of the bus lines. More specifically, it has been estimated that the capacitance driven by the I/O nodes is usually three orders of magnitude [2] that of the one seen by the internal nodes of a microprocessor. Design techniques leading to decrease in power dissipation on external buses will make a significant impact on the overall power dissipation of the system. While many bus encoding techniques [3][4] focus on instruction address bus encoding, only a few interested in data address bus encoding. Although memory access instructions account for only 20% to 25% of all instructions, the data address bus bit transitions account for 30% to 60% of all address bus transitions, due to the random bit-pattern nature of data addresses.
2 Techniques for reducing bit transitions on data address buses deserve in-depth exploration. The rest of the paper is organized as follows: Section 2 describes the background of low-power data address bus encoding. Section 3 presents the proposed design for reducing the bit transitions on data address buses. Section 4 gives the performance results. The last section summarizes the work. 2. Background In this section, the behaviors of a data address sequence and its related low-power bus encoding techniques are described. Some potential improvements to these existing designs and other design issues yet explored are also unveiled. The data address sequences for general-purpose computing are usually randomly distributed. However, accesses to arrays or scalar data in loops do give the resulted data address sequences some pattern. Bus-Invert (BI) method [5] is proposed for random data sequence patterns. It inverts the to-be transmitted bus value whenever doing so can result in less bit transitions less than half of bus width. An extra control line, called INV, is used to indicate if the bus value had been inverted. Zero-Transition (T0) method [6], which avoids the transmission of sequential data completely, is proposed by Benini. An extra control line, called INC, is used to indicate if the bus value is sequential to last bus value. A true INC renders the signals on bus lines meaningless, hence these lines can remain unchanged to save power. T0_BI method [1], which combines both BI and T0 methods, uses two extra control signals, the INV and the INC, to integrate both methods in one design. However, these two control lines themselves may produce excessive number of bit-transitions in many cases. We believe that there exists room for improvement in existing designs, and also new design issues for further studying. First, the two control lines of T0_BI method may be combined into one control line to indicate both invert and sequential condition. Second, the stride value of data addresses may be updated dynamically to allow for different data address strides. Finally, the read and write data address sets usually have their distinct behaviors, and they should be encoded independently for the greatest benefit of both sets. 3. Designs Our low-power data address bus encoding scheme is described in this section. Section 3.1 will introduce the overview of our designs, section 3.2 to 3.4 will show our design details, and section 3.5 gives the design summary Design Overview Figure 1: Data address bus encoding architecture Figure 1 shows our low-power data address bus encoding architecture. The encoder gets data addresses from CPU and outputs the encoded address and some control signals. Encoded addresses and control signals are transmitted to the decoder of data memory. When the decoder receives encoded addresses and control signals, it converts this information into original data address. Two control lines, called Read/Write and enable, are traditional memory control signals, and we will make use of them later.
3 Three versions of our low-power bus encoding scheme are proposed in this paper, with the second and third built upon its predecessor version: T0_BI_1 combining T0 & BI using a single control line; T0_BI_1/S with Variable-Stride capability added; T0_BI_1/S/RW preserving read/write continuities in a multiplexed data address sequence. T0 schemes. Following is the T0_BI_1 encoding algorithm: 3.2. Combining T0 & BI using single control line (T0_BI_1) T0_BI_1 design uses only one control line, called INCV, to control both INC and INV functions to transmit a data address, the encoder of T0_BI_1 first detects the continuity of the transferred address sequence. The continuity means that the current address is equal to the sum of the previous address and the stride. Transmission of an address with continuity property is done with an asserted INCV and a frozen address bus. If continuity test fails, then the encoder checks to see if the address pattern produces bus bit-transitions on more than half of the address bus lines and the inverted address pattern is not equal to the previous bus value, then the INCV is also asserted and the inverted address is sent over the address bus. Otherwise, the INCV line is de-asserted and the address will be sent directly. Upon activation, the decoder needs to identify the meaning of an asserted INCV line according to the received bus value. If the bus value is unchanged, the INCV line is interpreted as an increment-by-stride indicator. Otherwise, it is interpreted as an invert indicator. In this way, the single INCV line can act as both INC and INV control signals, and address encoding still benefit from both BI and Figure 2: T0_BI_1 encoding algorithm And the corresponding T0_BI_1 decoding algorithm is: Figure 3: T0_BI_1 decoding algorithm Note that the decoder interprets the meaning of the asserted INCV line according to the received bus value. If the encoder intends to invert the bus value but the inverted value happens to equal the current bus value, the decoder may erroneously interpret this as a frozen address bus. As a result, to avoid this error, the encoder simply sends the current address out directly. We believe that this is a very unlikely situation, but precaution must be carefully taken.
4 3.3. T0_BI_1 with Variable-Stride capability (T0_BI_1/S) Many data are structured (arrays, matrices, etc.), and accesses to such structured data have very predictable data addresses. We use the term stride to describe the byte offset between consecutive access addresses of this kind. Two factors affect the stride value: one is the data item size (64 bits for scientific data, 32 bits for general-purpose computing, and 16 or 8 bits for multimedia applications). The other is the access pattern (column, row, diagonal, ) interacted with the storage scheme (row-major, column-major, others). These complicate the stride value computation and identification; different stride values may even mix in the code sequence. Here we deal only with the changing stride problem. Interleaved stride problem will be tackled in next section. Following is the T0_BI_1/S encoding algorithm, in which italic and underlined contents are newly added: Figure 4: T0_BI_1/S encoding algorithm And the corresponding T0_BI_1/S decoding algorithm, in which italic and underlined contents are newly added, is: Figure 5: T0_BI_1/S decoding algorithm The above algorithms are very simple and straight forward methods, and work only with array accesses without any intervening data accesses. Nevertheless, with these simple ideas as the basis, many innovative schemes can be derived, such as the one to be introduced next Preserving Read/Write Continuities in a multiplexed data address sequence (T0_BI_1/S/RW) Data memory are read and written by the CPU, both over the same set of address and data buses. While data read sequence and write sequence each has its own stride characteristics, these stride characteristics are unfortunately torn apart and severely contaminated due to the intervention of the read/write address sequences in a single address trace. How to preserve and utilize the individual read and write stride characteristics in bus encoding hence becomes an interesting problem. As a result, if we can encode the read and write address sequences individually, we must gain more power savings. Figure 6 shows the T0_BI_1/S/RW block diagram. In this modification, the read/write control line, which exists in all memory systems, is used to indicate the address being a read or
5 Figure 6: T0_BI_1/S/RW block diagram write address. With this, we can encode each of the read and write address sequences separately using our variable stride T0_BI_1/S method. Following is the T0_BI_1/S/RW encoding algorithm, in which italic and underlined contents are newly added: Figure 8: T0_BI_1/S/RW decoding algorithm 3.5. Summary Figure 7: T0_BI_1/S/RW encoding algorithm And the corresponding T0_BI_1/S/RW decoding algorithm, in which italic and underlined contents are newly added, is: We have introduced our low-power data address encoding/decoding schemes. The data address sequences are bi-streamed into read and write addresses and each of them use their own encoding logic of variable-stride T0_BI_1/S. The decoding process is similar to encoding, and we ignore its details here.
6 Figure 9: Simulation flowchart 4. Simulation We implement our design using simulation, and use benchmarks to validate our design. The target embedded system conforms to a portable personal multimedia/communication device, and the test programs are selected accordingly. The performance metric is the ratio of reduced data address bus bit toggles. To simplify the result, only overall performance improvements are reported. Although readers may be interested in the effects of each individual technique and their incremental effects on top of other techniques, these data are not shown here due to page limits Simulation Environment The simulated embedded system platform assumptions are listed below: 1. The processor is ARM7TDMI, and there is only one processor in the system. 2. The memory is separated into two parts: instruction memory, and data memory. 3. There is no cache memory. 4. All instructions are compiled in ARM mode. There are four types of benchmarks, and each type has 2 programs in it. These benchmark programs are selected from MediaBench, a popular benchmark suite including multi-media and communication applications. These benchmarks are: 1. ADPCM Audio Coder and Decoder 2. Efficient Pyramid Image Coder, an experimental image data compression utility 3. GSM full-rate speech trans-coding 4. JPEG image compression & decompression Figure 9 shows the flowchart of simulation. The benchmarks are run in the ARM-Emulator7t, and the emulator dumps the trace of program execution. After that, a simulator takes the trace as input and counts the number of data address bus bit transitions. Number of bit transitions are collected for 1) a traditional data address bus, 2) BI encoded bus, 3) T0 encoding bus, 4) T0_BI encoded bus, and 5) T0_BI_1/S/RW encoded bus Simulation Results The goal of data address bus encoding methods is to reduce the switching activities on data address bus, so the result of encodings will be presented as percentage of reduced switching activities, which is calculated as (% of Reduced Switching Activities) = (Reduced Switching count) (unencoded Switching count). The higher this value is, the more effective the corresponding design. To make the results more readable, following only shows the average of all eight benchmarks due to each design. Reduced Transitions 30% 25% 20% 15% 10% 5% 0% Simulation Results our scheme T0_BI BI T0 Figure 10: Simulation Results
7 5. Conclusions In this paper, we address low-power data address bus encoding technique. First, we have proposed a T0_BI_1 method to integrate T0 and BI methods using only one control line. Second, we have introduced a variable-stride method which deals with dynamically changing strides, and can be combined with T0_BI_1. Lastly, we have used separate sets of encoding information for read and write address sets to preserve their individuality. Compared with the T0_BI method, our design achieves 26% reduction of the original bit transitions, and the improvements rate is 226%. The simulation results show that our data address bus encoding scheme has much less bit transitions. To make the power estimation results more precise, a bus power model needs to be carefully constructed. And the hardware overheads for the additional control lines/logic, include silicon area, delay, and power, also need to be evaluated. Several related research directions worth further studying. For one, we can allow multiple candidate strides and adaptively select among them for encoding. The challenge is how to determine which stride is to be used. Second, we can extend our bus encoding method to be applicable on multiplexed instruction/data address bus. Many designs with pin count/pcb real estate limitations use such multiplexed bus. The challenge of this extended work is how to capture and use the individual instruction/load/ store address sets from the multiplexed bus, on these three intervened address set sequences. And last, we can try to preserve more continuity in all kinds of address bus sequences, but how to do it remains a question! 6. References [1] L. Benini, G. DeMicheli, E.Macii, D. Sciuto, and C. Silvano, Address bus encoding techniques for system-level power optimization, Proc. Of Design Automation and Test in Europe, pp , Feb [2] S. Wuytack, F. Catthoor, L. Nachtergaele, H. De Man, Global communication and memory optimizing transformati ons for low power signal processing systems, IWLPD-94: ACM/IEEE International Workshop on Low Power Design, Apr. 1994, pp [3] C. L. Su, C. Y. Tsui, A. M. Despain, Saving Power in the Control Path of Embedded Processors, IEEE Design and Test of Computers, Vol. 11, No. 4, pp , Winter 1994 [4] Y. Aghaghiri, F. Fallah, and M. Pedram, Irredundant address bus encoding for low-power, in Proc. IEEE Int. Symp. Low-Power Electronics and Design, Aug. 2001, pp [5] M. R. Stan and W. P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on VLSI Systems, Vol. 3, No. 1, pp , 1995 [6] L. Benini, G. DeMicheli, E.Macii, D. Sciuto, and C. Silvano, Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems GLS-VLSI-97: IEEE 7th Great Lakes Symposium on VLSI,pp , Urbanana-Champaign, IL, March 1997.
Bus Encoding Technique for hierarchical memory system Anne Pratoomtong and Weiping Liao
Bus Encoding Technique for hierarchical memory system Anne Pratoomtong and Weiping Liao Abstract In microprocessor-based systems, data and address buses are the core of the interface between a microprocessor
More informationMemory Bus Encoding for Low Power: A Tutorial
Memory Bus Encoding for Low Power: A Tutorial Wei-Chung Cheng and Massoud Pedram University of Southern California Department of EE-Systems Los Angeles CA 90089 Outline Background Memory Bus Encoding Techniques
More informationAddress Bus Encoding Techniques for System-Level Power Optimization. Dip. di Automatica e Informatica. Dip. di Elettronica per l'automazione
Address Bus Encoding Techniques for System-Level Power Optimization Luca Benini $ Giovanni De Micheli $ Enrico Macii Donatella Sciuto z Cristina Silvano # z Politecnico di Milano Dip. di Elettronica e
More informationShift Invert Coding (SINV) for Low Power VLSI
Shift Invert oding (SINV) for Low Power VLSI Jayapreetha Natesan* and Damu Radhakrishnan State University of New York Department of Electrical and omputer Engineering New Paltz, NY, U.S. email: natesa76@newpaltz.edu
More informationBus Encoding Techniques for System- Level Power Optimization
Chapter 5 Bus Encoding Techniques for System- Level Power Optimization The switching activity on system-level buses is often responsible for a substantial fraction of the total power consumption for large
More informationPower Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study
Power Estimation of System-Level Buses for Microprocessor-Based Architectures: A Case Study William Fornaciari Politecnico di Milano, DEI Milano (Italy) fornacia@elet.polimi.it Donatella Sciuto Politecnico
More informationReference Caching Using Unit Distance Redundant Codes for Activity Reduction on Address Buses
Reference Caching Using Unit Distance Redundant Codes for Activity Reduction on Address Buses Tony Givargis and David Eppstein Department of Information and Computer Science Center for Embedded Computer
More informationEfficient Power Reduction Techniques for Time Multiplexed Address Buses
Efficient Power Reduction Techniques for Time Multiplexed Address Buses Mahesh Mamidipaka enter for Embedded omputer Systems Univ. of alifornia, Irvine, USA maheshmn@cecs.uci.edu Nikil Dutt enter for Embedded
More informationA Low Power Design of Gray and T0 Codecs for the Address Bus Encoding for System Level Power Optimization
A Low Power Design of Gray and T0 Codecs for the Address Bus Encoding for System Level Power Optimization Prabhat K. Saraswat, Ghazal Haghani and Appiah Kubi Bernard Advanced Learning and Research Institute,
More informationPower Aware Encoding for the Instruction Address Buses Using Program Constructs
Power Aware Encoding for the Instruction Address Buses Using Program Constructs Prakash Krishnamoorthy and Meghanad D. Wagh Abstract This paper examines the address traces produced by various program constructs.
More informationBehavioral Array Mapping into Multiport Memories Targeting Low Power 3
Behavioral Array Mapping into Multiport Memories Targeting Low Power 3 Preeti Ranjan Panda and Nikil D. Dutt Department of Information and Computer Science University of California, Irvine, CA 92697-3425,
More informationPower-Aware Bus Encoding Techniques for I/O and Data Busses in an Embedded System
Power-Aware Bus Encoding Techniques for I/O and Data Busses in an Embedded System Wei-Chung Cheng and Massoud Pedram Dept. of EE-Systems University of Southern California Los Angeles, CA 90089 ABSTRACT
More informationVERY large scale integration (VLSI) design for power
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 7, NO. 1, MARCH 1999 25 Short Papers Segmented Bus Design for Low-Power Systems J. Y. Chen, W. B. Jone, Member, IEEE, J. S. Wang,
More informationAdaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 11, NO.5, OCTOBER 2003 827 Adaptive Low-Power Address Encoding Techniques Using Self-Organizing Lists Mahesh N. Mamidipaka, Daniel
More informationReusing Cache for Real-Time Memory Address Trace Compression
Reusing for Real-Time Memory Address Trace Ing-Jer Huang Dept of Computer Science and Engineering National Sun Yat-Sen University Kaohsiung 804, Taiwan Tel : +886-7-525-2000 ext 4315 e-mail: ijhuang@csensysuedutw
More informationTransition Reduction in Memory Buses Using Sector-based Encoding Techniques
Transition Reduction in Memory Buses Using Sector-based Encoding Techniques Yazdan Aghaghiri University of Southern California 3740 McClintock Ave Los Angeles, CA 90089 yazdan@sahand.usc.edu Farzan Fallah
More informationRECENTLY, researches on gigabit wireless personal area
146 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 55, NO. 2, FEBRUARY 2008 An Indexed-Scaling Pipelined FFT Processor for OFDM-Based WPAN Applications Yuan Chen, Student Member, IEEE,
More informationParameterized System Design
Parameterized System Design Tony D. Givargis, Frank Vahid Department of Computer Science and Engineering University of California, Riverside, CA 92521 {givargis,vahid}@cs.ucr.edu Abstract Continued growth
More informationEvaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs
500 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 9, NO. 4, AUGUST 2001 Evaluating Power Consumption of Parameterized Cache and Bus Architectures in System-on-a-Chip Designs Tony
More informationUnified VLSI Systolic Array Design for LZ Data Compression
Unified VLSI Systolic Array Design for LZ Data Compression Shih-Arn Hwang, and Cheng-Wen Wu Dept. of EE, NTHU, Taiwan, R.O.C. IEEE Trans. on VLSI Systems Vol. 9, No.4, Aug. 2001 Pages: 489-499 Presenter:
More informationReducing Transitions on Memory Buses Using Sectorbased Encoding Technique
Reducing Transitions on Memory Buses Using Sectorbased Encoding Technique Yazdan Aghaghiri University of Southern California 3740 McClintock Ave Los Angeles, CA 90089 yazdan@sahand.usc.edu Farzan Fallah
More informationPredictive Line Buffer: A fast, Energy Efficient Cache Architecture
Predictive Line Buffer: A fast, Energy Efficient Cache Architecture Kashif Ali MoKhtar Aboelaze SupraKash Datta Department of Computer Science and Engineering York University Toronto ON CANADA Abstract
More informationA Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors Murali Jayapala 1, Francisco Barat 1, Pieter Op de Beeck 1, Francky Catthoor 2, Geert Deconinck 1 and Henk Corporaal
More informationA Translation Framework for Automatic Translation of Annotated LLVM IR into OpenCL Kernel Function
A Translation Framework for Automatic Translation of Annotated LLVM IR into OpenCL Kernel Function Chen-Ting Chang, Yu-Sheng Chen, I-Wei Wu, and Jyh-Jiun Shann Dept. of Computer Science, National Chiao
More informationDATA HIDING IN PDF FILES AND APPLICATIONS BY IMPERCEIVABLE MODIFICATIONS OF PDF OBJECT PARAMETERS
DATA HIDING IN PDF FILES AND APPLICATIONS BY IMPERCEIVABLE MODIFICATIONS OF PDF OBJECT PARAMETERS 1 Jiun-Tsung Wang ( 王竣聰 ) and 2 Wen-Hsiang Tsai ( 蔡文祥 ) 1 Institute of Multimedia Eng., National Chiao
More informationDESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTER
DESIGN AND IMPLEMENTATION OF BIT TRANSITION COUNTER Amandeep Singh 1, Balwinder Singh 2 1-2 Acadmic and Consultancy Services Division, Centre for Development of Advanced Computing(C-DAC), Mohali, India
More informationLow Power Set-Associative Cache with Single-Cycle Partial Tag Comparison
Low Power Set-Associative Cache with Single-Cycle Partial Tag Comparison Jian Chen, Ruihua Peng, Yuzhuo Fu School of Micro-electronics, Shanghai Jiao Tong University, Shanghai 200030, China {chenjian,
More informationEncoding Scheme for Power Reduction in Network on Chip Links
RESEARCH ARICLE OPEN ACCESS Encoding Scheme for Power Reduction in Network on Chip Links Chetan S.Behere*, Somulu Gugulothu** *(Department of Electronics, YCCE, Nagpur-10 Email: chetanbehere@gmail.com)
More informationEfficient Algorithm for Test Vector Decompression Using an Embedded Processor
Efficient Algorithm for Test Vector Decompression Using an Embedded Processor Kamran Saleem and Nur A. Touba Computer Engineering Research Center Department of Electrical and Computer Engineering University
More informationDUE to the high computational complexity and real-time
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 15, NO. 3, MARCH 2005 445 A Memory-Efficient Realization of Cyclic Convolution and Its Application to Discrete Cosine Transform Hun-Chen
More informationArchitectures and Synthesis Algorithms for Power-Efficient Bus Interfaces
IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 19, NO. 9, SEPTEMBER 2000 969 Architectures and Synthesis Algorithms for Power-Efficient Bus Interfaces Luca Benini,
More informationParallel-computing approach for FFT implementation on digital signal processor (DSP)
Parallel-computing approach for FFT implementation on digital signal processor (DSP) Yi-Pin Hsu and Shin-Yu Lin Abstract An efficient parallel form in digital signal processor can improve the algorithm
More informationPower-Mode-Aware Buffer Synthesis for Low-Power Clock Skew Minimization
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.* No.*,*-* Power-Mode-Aware Buffer Synthesis for Low-Power
More informationReal-time and smooth scalable video streaming system with bitstream extractor intellectual property implementation
LETTER IEICE Electronics Express, Vol.11, No.5, 1 6 Real-time and smooth scalable video streaming system with bitstream extractor intellectual property implementation Liang-Hung Wang 1a), Yi-Mao Hsiao
More informationTHE use of intellectual proprietary components, such as
554 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 6, NO. 4, DECEMBER 1998 Power Optimization of Core-Based Systems by Address Bus Encoding Luca Benini, Giovanni De Micheli, Fellow,
More informationOUTLINE Introduction Power Components Dynamic Power Optimization Conclusions
OUTLINE Introduction Power Components Dynamic Power Optimization Conclusions 04/15/14 1 Introduction: Low Power Technology Process Hardware Architecture Software Multi VTH Low-power circuits Parallelism
More informationPower Protocol: Reducing Power Dissipation on Off-Chip Data Buses
Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses K. Basu, A. Choudhary, J. Pisharath ECE Department Northwestern University Evanston, IL 60208, USA fkohinoor,choudhar,jayg@ece.nwu.edu
More informationPROOFS Fault Simulation Algorithm
PROOFS Fault Simulation Algorithm Pratap S.Prasad Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL prasaps@auburn.edu Term Paper for ELEC 7250 (Spring 2005) Abstract This paper
More informationAbridged Addressing: A Low Power Memory Addressing Strategy
Abridged Addressing: A Low Power Memory Addressing Strategy Preeti anjan Panda Department of Computer Science and Engineering Indian Institute of Technology Delhi Hauz Khas New Delhi 006 INDIA Abstract
More informationEnergy-Efficient Encoding Techniques for Off-Chip Data Buses
9 Energy-Efficient Encoding Techniques for Off-Chip Data Buses DINESH C. SURESH, BANIT AGRAWAL, JUN YANG, and WALID NAJJAR University of California, Riverside Reducing the power consumption of computing
More informationDesign and Implementation of Advanced Modified Booth Encoding Multiplier
Design and Implementation of Advanced Modified Booth Encoding Multiplier B.Sirisha M.Tech Student, Department of Electronics and communication Engineering, GDMM College of Engineering and Technology. ABSTRACT:
More informationTHE orthogonal frequency-division multiplex (OFDM)
26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II: EXPRESS BRIEFS, VOL. 57, NO. 1, JANUARY 2010 A Generalized Mixed-Radix Algorithm for Memory-Based FFT Processors Chen-Fong Hsiao, Yuan Chen, Member, IEEE,
More informationISSN Vol.04,Issue.01, January-2016, Pages:
WWW.IJITECH.ORG ISSN 2321-8665 Vol.04,Issue.01, January-2016, Pages:0077-0082 Implementation of Data Encoding and Decoding Techniques for Energy Consumption Reduction in NoC GORANTLA CHAITHANYA 1, VENKATA
More informationA Universal Test Pattern Generator for DDR SDRAM *
A Universal Test Pattern Generator for DDR SDRAM * Wei-Lun Wang ( ) Department of Electronic Engineering Cheng Shiu Institute of Technology Kaohsiung, Taiwan, R.O.C. wlwang@cc.csit.edu.tw used to detect
More informationManaging Dynamic Reconfiguration Overhead in Systems-on-a-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks
Managing Dynamic Reconfiguration Overhead in Systems-on-a-Chip Design Using Reconfigurable Datapaths and Optimized Interconnection Networks Zhining Huang, Sharad Malik Electrical Engineering Department
More informationMulti-Level Cache Hierarchy Evaluation for Programmable Media Processors. Overview
Multi-Level Cache Hierarchy Evaluation for Programmable Media Processors Jason Fritts Assistant Professor Department of Computer Science Co-Author: Prof. Wayne Wolf Overview Why Programmable Media Processors?
More informationLossless Compression using Efficient Encoding of Bitmasks
Lossless Compression using Efficient Encoding of Bitmasks Chetan Murthy and Prabhat Mishra Department of Computer and Information Science and Engineering University of Florida, Gainesville, FL 326, USA
More informationCode Compression for RISC Processors with Variable Length Instruction Encoding
Code Compression for RISC Processors with Variable Length Instruction Encoding S. S. Gupta, D. Das, S.K. Panda, R. Kumar and P. P. Chakrabarty Department of Computer Science & Engineering Indian Institute
More informationEfficient VLSI Huffman encoder implementation and its application in high rate serial data encoding
LETTER IEICE Electronics Express, Vol.14, No.21, 1 11 Efficient VLSI Huffman encoder implementation and its application in high rate serial data encoding Rongshan Wei a) and Xingang Zhang College of Physics
More informationSlide Set 9. for ENCM 369 Winter 2018 Section 01. Steve Norman, PhD, PEng
Slide Set 9 for ENCM 369 Winter 2018 Section 01 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary March 2018 ENCM 369 Winter 2018 Section 01
More informationA LOW-COMPLEXITY AND LOSSLESS REFERENCE FRAME ENCODER ALGORITHM FOR VIDEO CODING
2014 IEEE International Conference on Acoustic, Speech and Signal Processing (ICASSP) A LOW-COMPLEXITY AND LOSSLESS REFERENCE FRAME ENCODER ALGORITHM FOR VIDEO CODING Dieison Silveira, Guilherme Povala,
More informationInternational Journal of Emerging Technology and Advanced Engineering Website: (ISSN , Volume 2, Issue 4, April 2012)
A Technical Analysis Towards Digital Video Compression Rutika Joshi 1, Rajesh Rai 2, Rajesh Nema 3 1 Student, Electronics and Communication Department, NIIST College, Bhopal, 2,3 Prof., Electronics and
More informationPOWER ANALYSIS RESISTANT SRAM
POWER ANALYSIS RESISTANT ENGİN KONUR, TÜBİTAK-UEKAE, TURKEY, engin@uekae.tubitak.gov.tr YAMAN ÖZELÇİ, TÜBİTAK-UEKAE, TURKEY, yaman@uekae.tubitak.gov.tr EBRU ARIKAN, TÜBİTAK-UEKAE, TURKEY, ebru@uekae.tubitak.gov.tr
More informationSimultaneously Improving Code Size, Performance, and Energy in Embedded Processors
Simultaneously Improving Code Size, Performance, and Energy in Embedded Processors Ahmad Zmily and Christos Kozyrakis Electrical Engineering Department, Stanford University zmily@stanford.edu, christos@ee.stanford.edu
More informationISSCC 2006 / SESSION 22 / LOW POWER MULTIMEDIA / 22.1
ISSCC 26 / SESSION 22 / LOW POWER MULTIMEDIA / 22.1 22.1 A 125µW, Fully Scalable MPEG-2 and H.264/AVC Video Decoder for Mobile Applications Tsu-Ming Liu 1, Ting-An Lin 2, Sheng-Zen Wang 2, Wen-Ping Lee
More informationThermal-Aware Memory Management Unit of 3D- Stacked DRAM for 3D High Definition (HD) Video
Thermal-Aware Memory Management Unit of 3D- Stacked DRAM for 3D High Definition (HD) Video Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang and Wei Hwang Department of Electronics Engineering
More informationComplexity-effective Enhancements to a RISC CPU Architecture
Complexity-effective Enhancements to a RISC CPU Architecture Jeff Scott, John Arends, Bill Moyer Embedded Platform Systems, Motorola, Inc. 7700 West Parmer Lane, Building C, MD PL31, Austin, TX 78729 {Jeff.Scott,John.Arends,Bill.Moyer}@motorola.com
More informationProcessor and DRAM Integration by TSV- Based 3-D Stacking for Power-Aware SOCs
Processor and DRAM Integration by TSV- Based 3-D Stacking for Power-Aware SOCs Shin-Shiun Chen, Chun-Kai Hsu, Hsiu-Chuan Shih, and Cheng-Wen Wu Department of Electrical Engineering National Tsing Hua University
More informationSF-LRU Cache Replacement Algorithm
SF-LRU Cache Replacement Algorithm Jaafar Alghazo, Adil Akaaboune, Nazeih Botros Southern Illinois University at Carbondale Department of Electrical and Computer Engineering Carbondale, IL 6291 alghazo@siu.edu,
More informationUsing a Victim Buffer in an Application-Specific Memory Hierarchy
Using a Victim Buffer in an Application-Specific Memory Hierarchy Chuanjun Zhang Depment of lectrical ngineering University of California, Riverside czhang@ee.ucr.edu Frank Vahid Depment of Computer Science
More informationMinimizing Power Dissipation during Write Operation to Register Files
Minimizing Power Dissipation during Operation to Register Files Abstract - This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional
More informationAn Efficient Multi Mode and Multi Resolution Based AHB Bus Tracer
An Efficient Multi Mode and Multi Resolution Based AHB Bus Tracer Abstract: Waheeda Begum M.Tech, VLSI Design & Embedded System, Department of E&CE, Lingaraj Appa Engineering College, Bidar. On-Chip program
More informationPower Efficient Arithmetic Operand Encoding
Power Efficient Arithmetic Operand Encoding Eduardo Costa, Sergio Bampi José Monteiro UFRGS IST/INESC P. Alegre, Brazil Lisboa, Portugal ecosta,bampi@inf.ufrgs.br jcm@algos.inesc.pt Abstract This paper
More informationCS 24: INTRODUCTION TO. Spring 2015 Lecture 2 COMPUTING SYSTEMS
CS 24: INTRODUCTION TO Spring 2015 Lecture 2 COMPUTING SYSTEMS LAST TIME! Began exploring the concepts behind a simple programmable computer! Construct the computer using Boolean values (a.k.a. bits )
More informationLow Power Mapping of Video Processing Applications on VLIW Multimedia Processors
Low Power Mapping of Video Processing Applications on VLIW Multimedia Processors K. Masselos 1,2, F. Catthoor 2, C. E. Goutis 1, H. DeMan 2 1 VLSI Design Laboratory, Department of Electrical and Computer
More informationA Simulation: Improving Throughput and Reducing PCI Bus Traffic by. Caching Server Requests using a Network Processor with Memory
Shawn Koch Mark Doughty ELEC 525 4/23/02 A Simulation: Improving Throughput and Reducing PCI Bus Traffic by Caching Server Requests using a Network Processor with Memory 1 Motivation and Concept The goal
More informationGated-Demultiplexer Tree Buffer for Low Power Using Clock Tree Based Gated Driver
Gated-Demultiplexer Tree Buffer for Low Power Using Clock Tree Based Gated Driver E.Kanniga 1, N. Imocha Singh 2,K.Selva Rama Rathnam 3 Professor Department of Electronics and Telecommunication, Bharath
More informationISSN Vol.05,Issue.09, September-2017, Pages:
WWW.IJITECH.ORG ISSN 2321-8665 Vol.05,Issue.09, September-2017, Pages:1693-1697 AJJAM PUSHPA 1, C. H. RAMA MOHAN 2 1 PG Scholar, Dept of ECE(DECS), Shirdi Sai Institute of Science and Technology, Anantapuramu,
More informationMemory Systems IRAM. Principle of IRAM
Memory Systems 165 other devices of the module will be in the Standby state (which is the primary state of all RDRAM devices) or another state with low-power consumption. The RDRAM devices provide several
More informationWrite only as much as necessary. Be brief!
1 CIS371 Computer Organization and Design Midterm Exam Prof. Martin Thursday, March 15th, 2012 This exam is an individual-work exam. Write your answers on these pages. Additional pages may be attached
More informationOptimal Cache Organization using an Allocation Tree
Optimal Cache Organization using an Allocation Tree Tony Givargis Technical Report CECS-2-22 September 11, 2002 Department of Information and Computer Science Center for Embedded Computer Systems University
More informationWITH integrated circuits, especially system-on-chip
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 14, NO. 11, NOVEMBER 2006 1227 Improving Linear Test Data Compression Kedarnath J. Balakrishnan, Member, IEEE, and Nur A. Touba, Senior
More informationCharacterization of Native Signal Processing Extensions
Characterization of Native Signal Processing Extensions Jason Law Department of Electrical and Computer Engineering University of Texas at Austin Austin, TX 78712 jlaw@mail.utexas.edu Abstract Soon if
More informationLow-Power Instruction Bus Encoding for Embedded Processors. Peter Petrov, Student Member, IEEE, and Alex Orailoglu, Member, IEEE
812 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 8, AUGUST 2004 Low-Power Instruction Bus Encoding for Embedded Processors Peter Petrov, Student Member, IEEE, and Alex
More informationVector an ordered series of scalar quantities a one-dimensional array. Vector Quantity Data Data Data Data Data Data Data Data
Vector Processors A vector processor is a pipelined processor with special instructions designed to keep the (floating point) execution unit pipeline(s) full. These special instructions are vector instructions.
More informationDesign of a Pipelined 32 Bit MIPS Processor with Floating Point Unit
Design of a Pipelined 32 Bit MIPS Processor with Floating Point Unit P Ajith Kumar 1, M Vijaya Lakshmi 2 P.G. Student, Department of Electronics and Communication Engineering, St.Martin s Engineering College,
More informationSynthesis of Customized Loop Caches for Core-Based Embedded Systems
Synthesis of Customized Loop Caches for Core-Based Embedded Systems Susan Cotterell and Frank Vahid* Department of Computer Science and Engineering University of California, Riverside {susanc, vahid}@cs.ucr.edu
More informationEffective Memory Access Optimization by Memory Delay Modeling, Memory Allocation, and Slack Time Management
International Journal of Computer Theory and Engineering, Vol., No., December 01 Effective Memory Optimization by Memory Delay Modeling, Memory Allocation, and Slack Time Management Sultan Daud Khan, Member,
More informationCODING METHOD FOR EMBEDDING AUDIO IN VIDEO STREAM. Harri Sorokin, Jari Koivusaari, Moncef Gabbouj, and Jarmo Takala
CODING METHOD FOR EMBEDDING AUDIO IN VIDEO STREAM Harri Sorokin, Jari Koivusaari, Moncef Gabbouj, and Jarmo Takala Tampere University of Technology Korkeakoulunkatu 1, 720 Tampere, Finland ABSTRACT In
More information(1) Define following terms: Instruction, Machine Cycle, Opcode, Oprand & Instruction Cycle. Instruction:
(1) Define following terms: Instruction, Machine Cycle, Opcode, Oprand & Instruction Cycle. Instruction: Instruction is the command given by the programmer to the Microprocessor to Perform the Specific
More informationSoftware Power Optimizations In An Embedded System
Software Power Optimizations In An Embedded System Vishal Dalal 3G Wireless Group Silicon Automation Systems Limited Bangalore, India vishald @ sasi. com C.P. Ravikumar Department of Electrical Engineering
More informationApplication-Specific Design of Low Power Instruction Cache Hierarchy for Embedded Processors
Agenda Application-Specific Design of Low Power Instruction ache ierarchy for mbedded Processors Ji Gu Onodera Laboratory Department of ommunications & omputer ngineering Graduate School of Informatics
More information6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1
6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,
More informationSDR Forum Technical Conference 2007
THE APPLICATION OF A NOVEL ADAPTIVE DYNAMIC VOLTAGE SCALING SCHEME TO SOFTWARE DEFINED RADIO Craig Dolwin (Toshiba Research Europe Ltd, Bristol, UK, craig.dolwin@toshiba-trel.com) ABSTRACT This paper presents
More informationEnergy Efficient Caching-on-Cache Architectures for Embedded Systems
JOURNAL OF INFORMATION SCIENCE AND ENGINEERING 19, 809-825 (2003) Energy Efficient Caching-on-Cache Architectures for Embedded Systems HUNG-CHENG WU, TIEN-FU CHEN, HUNG-YU LI + AND JINN-SHYAN WANG + Department
More informationCOMPUTER ARCHITECTURES
COMPUTER ARCHITECTURES Random Access Memory Technologies Gábor Horváth BUTE Department of Networked Systems and Services ghorvath@hit.bme.hu Budapest, 2019. 02. 24. Department of Networked Systems and
More informationEEL 4783: Hardware/Software Co-design with FPGAs
EEL 4783: Hardware/Software Co-design with FPGAs Lecture 5: Digital Camera: Software Implementation* Prof. Mingjie Lin * Some slides based on ISU CPrE 588 1 Design Determine system s architecture Processors
More informationPower Optimized Transition and Forbidden Free Pattern Crosstalk Avoidance
Power Optimized Transition and Forbidden Free Pattern Crosstalk Avoidance Sigmala Mani Raju PG Scholar, Dept of ECE, Global College of Engineering & Technology, Kadapa, YSR (Dt), AP, India. Abstract: In
More informationChapter 7 The Potential of Special-Purpose Hardware
Chapter 7 The Potential of Special-Purpose Hardware The preceding chapters have described various implementation methods and performance data for TIGRE. This chapter uses those data points to propose architecture
More informationVector Bank Based Multimedia Codec System-on-a-Chip (SoC) Design
2009 10th International Symposium on Pervasive Systems, Algorithms, and Networks Vector Bank Based Multimedia Codec System-on-a-Chip (SoC) Design Ruei-Xi Chen, Wei Zhao, Jeffrey Fan andasaddavari Computer
More informationMemory Access Optimizations in Instruction-Set Simulators
Memory Access Optimizations in Instruction-Set Simulators Mehrdad Reshadi Center for Embedded Computer Systems (CECS) University of California Irvine Irvine, CA 92697, USA reshadi@cecs.uci.edu ABSTRACT
More informationA Bus Architecture for Crosstalk Elimination in High Performance Processor Design
A Bus Architecture for Crosstalk Elimination in High Performance Processor Design Wen-Wen Hsieh Department of Computer Science National Tsing Hua University HsinChu, Taiwan 300, R.O.C wwhsieh@cs.nthu.edu.tw
More informationAn Integrated ECC and BISR Scheme for Error Correction in Memory
An Integrated ECC and BISR Scheme for Error Correction in Memory Shabana P B 1, Anu C Kunjachan 2, Swetha Krishnan 3 1 PG Student [VLSI], Dept. of ECE, Viswajyothy College Of Engineering & Technology,
More informationTradeoff between coverage of a Markov prefetcher and memory bandwidth usage
Tradeoff between coverage of a Markov prefetcher and memory bandwidth usage Elec525 Spring 2005 Raj Bandyopadhyay, Mandy Liu, Nico Peña Hypothesis Some modern processors use a prefetching unit at the front-end
More informationChapter-5 Memory Hierarchy Design
Chapter-5 Memory Hierarchy Design Unlimited amount of fast memory - Economical solution is memory hierarchy - Locality - Cost performance Principle of locality - most programs do not access all code or
More informationA Low Power SRAM Base on Novel Word-Line Decoding
Vol:, No:3, 008 A Low Power SRAM Base on Novel Word-Line Decoding Arash Azizi Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, Ali Barati, and Ali Sarchami International Science Index, Computer and
More informationEnergy-Efficient Value-Based Selective Refresh for Embedded DRAMs
Energy-Efficient Value-Based Selective Refresh for Embedded DRAMs K. Patel 1,L.Benini 2, Enrico Macii 1, and Massimo Poncino 1 1 Politecnico di Torino, 10129-Torino, Italy 2 Università di Bologna, 40136
More informationPower Aware External Bus Arbitration for System-on-a-Chip Embedded Systems
Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems Ke Ning 12 and David Kaeli 1 1 Northeastern University 360 Huntington Avenue, Boston MA 02115 2 Analog Devices Inc. 3 Technology
More informationDesign and Implementation of AMBA AXI to AHB Bridge K. Lakshmi Shirisha 1 A.Ramkumar 2
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 01, 2015 ISSN (online): 2321-0613 K. Lakshmi Shirisha 1 A.Ramkumar 2 2 Assistant Professor 1,2 Department of Electronic
More informationEvaluation of Static and Dynamic Scheduling for Media Processors. Overview
Evaluation of Static and Dynamic Scheduling for Media Processors Jason Fritts Assistant Professor Department of Computer Science Co-Author: Wayne Wolf Overview Media Processing Present and Future Evaluation
More information