AT17F Series. Application Note. Programming Circuits for AT17F Series Configurators with Xilinx FPGAs. 1. Introduction
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1 Programming Circuits for ATF Series s with Xilinx s. Introduction Atmel s ATF series Flash Configuration Memory devices use a simple serial-access procedure to configure one or more Xilinx Field Programmable Gate Arrays (s). ATF devices easily interface to Xilinx s in Master Serial configuration mode, which is the most common and simple configuration mode supported by all Xilinx families. This application note provides several drawings, showing Drop-In, In-System and Cascade Programming circuits for ATF series devices with Xilinx s. Please note that since older Xilinx devices use the PROGRAM and INIT pin names, the and PROGRAM pins can be used interchangeably and so are and. Since the ATFF family devices operate at.v, the Xilinx chips must be set-up to use a.v I/O interface with the configurator. The ATF devices can be programmed using Atmel s ATDH00E programming system and are supported by several major third-party programmer vendors. ATF Series Application Note. Drop-In Programming Circuits for ATF Series s with Xilinx s The Atmel ATDH00E programming system allows users to easily program ATF Configuration Memory devices with configuration files prior to mounting them on the target system. Once programmed, the configuration device can be placed on the target board to configure the s. Figure - below shows the use of the ATDH00. Figure -. ATDH00E Stand-Alone Device Programming ATDH00E Parallel Port Cable DB-M PC DB-F Connected to the Parallel Port Device Socket
2 In addition to the ATDH00E programming system, many third-party programmers support the ATF Flash memory devices. A list of third-party programmer vendors supporting Atmel products can be found at: Please contact the programmer vendors for support availability. Figure - below shows all the required connections between the ATF configurator and a Xilinx device when in-system programming is not required. This circuit requires that the ATF device be programmed either by the ATDH000E programming system or a third-party programmer prior to mounting or using with target. Figure -. Drop-In circuit showing an ATF Series Device with an Xilinx () Spartan / II / E / III Virtex / E / II / II-Pro FGPA C () () RESET/OE O/A READY () () GND Notes:. Use of the READY pin is optional.. Refer to the -specific datasheet.. VCC =.V ATF Series Application Note
3 ATF Series Application Note. In-System Programming Setup for ATF Series s with Xilinx s To perform In-System Programming (ISP), the ATDH programming dongle is required in order to provide communication between the PC and the configurator targeted for programming. See Figure -. Figure -. ATDH In-System Programming Setup -pin Ribbon Cable ATF Series Device Target System PC Connected to Parallel Port ATDH Programming Dongle In-System Programming Connector -pin
4 . In-System Programming Circuits for ATF Series s with Xilinx s Figure - below shows all the required connections between the ATF, ISP circuits, and a single Xilinx device. Figure -. In-System Programming Circuit of ATF Series Devices with a Xilinx C () -pin O/A () RESET/OE READY () () Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V. ATF Series Application Note
5 ATF Series Application Note Figure -. In-System-Programming of a Single ATF and Cascaded Xilinx devices C () Series Device -pin O/A () RESET/OE Series Device O/A () RESET/OE READY () () Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V. Cascaded Programming Circuits using ATF Series s with Xilinx s ATF devices provide a feature that allows a large configuration file that will not fit into one configurator device to be stored and downloaded from two ATF devices in serial cascade fashion. When performing in-system programming with cascaded configurators, special attention must be given to the O/A I/O pins of the two configurator devices. While in configurator programming mode, SEREN = 0, the O/A pins act as address line input A. Consequently, in order for the ISP software to individually communicate with each device, each device must have a different address setting. In Figure -, Device uses its internal pull-up resister to provide the
6 logic setting to its A pin, while the A pin of Device is connected to ground for logic 0. Hence, each configurator responds only to ISP software messages bearing its unique address. Figure -. In-System Programming of Cascaded ATF Series Devices with a Single Xilinx DOUT Master Device C VCC () -pin O/A () RESET/OE READY () () GND Slave Device C Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V ATF Series Application Note
7 ATF Series Application Note Figure -. In-System Programming of Cascaded ATF Series Devices with Cascaded Xilinx s DOUT Master Device C () Series Device -pin O/A () RESET/OE READY () GND Slave Device C Series Device () O/A () RESET/OE READY () Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V
8 . Using the Multiple Configuration Page Capabilities of ATF s ATF configurators provide a memory page feature that allows users to store four configuration files at four different page locations and instantly configure their device with the functionality given by each bitstream. As an example of its usefulness, designs requiring a M-bit configuration device may benefit from using the ATF00A since up to four different configurations can be stored and accessed as needed. This will simplify field upgrades and parts inventory by reducing the need for four M-bit devices holding different design implementations, to just one M-bit device with four different configurations. When the () input of the ATF device is set to logic, the storage space of the ATF device is split into four equal size partitions. Upon initiating a configuration sequence, the configuration bitstream residing at the page given by the Pagesel [:0] bits, will be downloaded into the. CPS software version.0 or later can be used to select and program the individual bitstreams at the page locations the user desires. Alternatively, designers who choose to write there own ISP code should note the address page boundaries as shown in Table -. Additional details on the use of the memory page feature and exact address boundary locations () can be found in the corresponding ATF device datasheet. Table -. ATF Address Boundaries PAGESEL [:0] PAGE ATF00 ADDR RANGE ATF00 ADDR RANGE ATF ADDR RANGE ATF ADDR RANGE 0 XX FFFF FFFF FFFFF FFFFF FFFF FFFF FFFF FFFF FFFF 0000-FFFF 0000-FFFF FFFFF 0000-FFFF 0000-FFFF 0000-BFFFF 0000-FFFF 0000-FFFF 0000-FFFF C0000-FFFFF 0000-FFFFF Figures - and - show circuit drawings, implementing the page enable and page select features of ATF devices. Use of the page feature is aided by control logic such as a microcontroller, PLD or DIP switch for the purpose of controlling the page selection pins. Notes:. The page enable feature is not available on the low -lead LAP package. The address ranges reflect that data is stored -bits per address. ATF Series Application Note
9 ATF Series Application Note Figure -. PLD/Microcontroller Logic Controlled Page Selection C () -pin O/A () RESET/OE READY () () External Controller (Microcontroller/PLD) Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V
10 Figure -. Manually-Controlled Paging Selection C () -pin O/A () RESET/OE READY () () VCC DIP Switches Notes:. The A bit-level setting in the Programming System (CPS) software should match the A pin setting in the hardware. By default, it must be set to high for ISP access to Series Device and set to low for Series Device.. Use of the READY pin is optional.. Refer to the device-specific datasheet.. IN00 or equivalent.. VCC =.V ATF Series Application Note
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