1. SWITCHING FUNDAMENTALS
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1 . SWITCING FUNDMENTLS Switchig is the provisio of a o-demad coectio betwee two ed poits. Two distict switchig techiques are employed i commuicatio etwors-- circuit switchig ad pacet switchig. Circuit switchig provides a dedicated path betwee the two ed poits. The etire badwidth of the coectio is allocated for commuicatio betwee the ed poits, for the duratio of the call, whether or ot messages are passed. I pacet switchig, o the other had, messages to be passed are pacetized ad the coectio is used by a call as ad whe pacets are ready. I betwee these pacets, the coectio ca be used to route pacets belogig to other calls. Circuit switchig is ubiquitous i the telephoe etwor. It is ideal for providig ormal voice commuicatios. It ca also be used for data commuicatios by employig modems which covert data to voice bad sigals. Pacet switchig is popular i computer commuicatio etwors. ecetly, however, it has started to proliferate ito the telephoe etwor uder the asychroous trasfer mode (TM) baer. Need for Cetral Switchig: Whe the umber of statios N is small, we ca simply itercoect the statios with a mesh etwor. Whe N gets larger, it is ecoomical to use a cetral switch. Whe N is very large ad the statios are spread over wide geographical area, oe or more levels of itermediate switchig is more ecoomical. This leads to a hierarchical switchig etwor, cosistig of a etwor of switches. These scearios are illustrated below. Switch No cetral Switchig N Statios N(N-)/ Lies Cetral Switchig N Statios N Lies Loop Local Tru L T Toll Coectig Tru Toll Tru L: Local Switch T: Toll Swich T L L ierarchical Switchig - -
2 Four-Wire Switchig: The regular telephoe istrumet uses the same pair of wires for both trasmittig (talig) ad receivig (listeig). This is ow as two-wire trasmissio. This two-wire system, however, is coverted to a four-wire system, which employs separate paths for each of the directios, to facilitate log distace trasmissio ad switchig. The device that performs this coversio is ow as a "hybrid." Two separate paths have to be set up through the four wire switchig matrix to complete a call as show below. N SWITCING MTIX ybrids Ilets Four-Wire Switchig Outlets. SPCE SWITCING Space switchig arrays are used i older aalog as well as moder digital switchig exchages. They are also employed i the itercoectio fabrics of fast pacet switches. The techiques developed for the desig ad aalysis of multistage space switches ca be easily exteded to the case of multistage time-space switchig matrices. Sigle-stage space switch: sigle-stage space switch cosists of a rectagular array of crosspoits. It ca coect a arbitrary idle ilet to a arbitrary idle outlet. The space switch for coectig N ilets to N outlets requires N crosspoits. I l e t s Symbol O u t l e t s space switch - - < : cocetrator > : expader = : distributor Multistage space switchig: The umber of crosspoits eeded to build large sigle stage space switches grows as N. Furthermore, there is oly oe path from a specified ilet to a specified
3 outlet. This leads to a very iefficiet utilizatio of the crosspoits ad also raises reliability questios. Both of these problems ca be solved by employig multistage switchig matrices. Stage Stage Stage 3 r x r x r x r x N ilets N outlets r = N/ r r x r x r Ilets Iput lis Output lis Outlets Three-stage space switch The bloc diagram of a three-stage switch is show i the diagram. I this structure the ilets ad outlets are partitioed ito subgroups of size ad there are paths from a ilet to a outlet. The total umber of crosspoits i such a implemetatio is give by: N C = N + Clo's Theorem for strictly oblocig etwors: strictly oblocig etwor allows coectio betwee a idle ilet-outlet pair, without disturbig existig coectios, regardless of the previous state of the etwor. The requiremets o a three-stage etwor that satisfies this coditio ca be derived as follows. Suppose we wat to set up a coectio betwee a idle ilet a ad a idle outlet b i a three-stage desig. The worst sceario, as for as blocig is cocered, is show i the diagram. ll the (-) ilets o the first stage switch origiatig ilet a ad the (-) outlets o the third stage switch termiatig outlet b are busy. Furthermore, these (-) coectios are doe via a differet secod stage switch. Uder these circumstaces, a further oe secod stage switch is required to coect a adb. Thus, for a strictly oblocig etwor, the miimum umber of required secod stage switches = -. This is ow as Clo's Theorem. 3. DIGITL TIME DIVISION SWITCING Iterchage (TSI) Module: Suppose we wat to build a 00 lie strictly oblocig telephoe switch. This ca be accomplished by a sigle stage or multistage space switch described previously. alterate (ad more ecoomical) method is to use a time slot iterchage (TSI) module. The architecture of such a switch is show below: - 3 -
4 0 - - DEMUX & D- 0 0 Data Memory -D & MUX 0 TSI 0 00 z cl Couter Cotrol Memory Data Memory Operatio 0 W W W W TSI Switch I this method, chaels are sampled at the stadard z rate (which yields a frame iterval of 5 µs), coded at bits per sample, ad multiplexed to form a TDM sigal. These chael samples are writte sequetially ito a 00 word data memory. The write address to this memory is geerated by the time slot couter. The data memory is read i a order determied by the cotets of a secod 00 word memory ow as the cotrol memory. The output of the time slot couter serves as the read address of this cotrol memory ad its cotets are programmed accordig to the required itercoectio patter betwee the ilets ad outlets. s a example, to coect telephoe lies ad, locatio of the cotrol memory is programmed with the umber ad locatio with the umber, as show i the diagram. Whe the cotets of the data memory is read out usig the output of the cotrol memory as the read address, the output TDM lie will have the proper time slots iterchaged to realize the required coectio. This TDM sigal is demultiplexed, coverted to aalog, ad directed to the proper telephoe sets. The combiatio of the data memory, time slot couter ad the cotrol memory is ow as the TSI module (or a time switch ). It ca redirect a give iput time slot to ay desired output time slot. ece, it is equivalet to a strictly oblocig switch as show below: Ilet TDM Sigal TSI Outlet TDM Sigal TS TS N- N x N Space Switch TS TS N- The TSI module described above employs a sequetial write followed by a 'radom' read to accomplish the switchig fuctio. It is ow as a output cotrolled TSI module. lterately, it is possible to realize the same fuctio with a iput cotrolled TSI module. I this case the cotrol memory geerates the write address of the data memory. The icomig voice samples are writte ito the appropriate locatios of the data memory, depedig o the desired switchig fuctio. The cotets of the data memory are read out i a sequetial order usig the output of the time slot couter as the read address. The architecture of this TSI module is show below:
5 0 TDM Ilet Cotrol Memory Data Memory Co uter iput cotrolled TSI module - - TDM Outlet 0 W W W Data Memory Operatio 00 z cl Chael limitatios of the sigle stage time switch: The data memory i the TSI module described above has to perform N read operatios ad N write operatios durig the frame iterval of 5 µs, where N deotes the umber of chaels i the TDM ilet/outlet sigals. ssumig that a read or a write operatio taes the same amout of time, equal to the memory cycle time, the maximum umber of chaels that ca be switched with a sigle TSI module is give by: Maximum chaels = 5 µs / [xmemory cycle time i µs] s a example, we ca switch 500 chaels with 5 s memories. Icreasig the capacity of the sigle stage time switch: We will describe two methods for icreasig the umber of chaels that ca be switched with a sigle stage time switch. The first method allows the capacity to be doubled. It uses two data memories i the double bufferig mode as show i the diagram. Durig odd umbered frames, data memory is writte ito whereas data memory is read. The roles are reversed i the eve umbered frames. The TDM outlet is always coected to the output of the memory beig read. s i the case of the ormal TSI module, the cotrol memory cotais the desired itercoectio patter. This method requires twice the amout of data memory. The maximum switchig delay ca be close to two frames. The lie rate of the TDM sigals is also doubled. The secod method icorporates a techique of storig multiple copies of the iput data. The umber of copies stored equals the desired capacity icrease over the ormal TSI module. architecture that doubles the capacity is show i the diagram. The N iput chaels are multiplexed oto two TDM highways, labeled ad B, each cosistig of N chaels. The chaels are writte ito both the ad data memories. Similarly, the B chaels are writte ito both the B ad B data memories. The chaels appearig o the TDM outlet are determied by the cotets of cotrol memory. I each time slot, this memory outputs a read address which determies the data memory locatio to be read, ad a output eable () sigal which determies whether memory or B is to be eabled. This gives complete cotrol over which oe of the N chaels appears i a particular time slot o the TDM outlet. idetical method is used to determie the chaels o the B TDM outlet
6 0 N- Data Mem TDM Outlet TDM Ilet Data Mem Mem Mem Outlet Odd Write ead Mem Eve ead Write Mem Couter Ctrl Mem Double Buffered TSI Module TDM Ilet Data Mem 0 N- TDM Outlet BTDM Ilet Data Mem B Data Mem Ctrl Mem ctrl Data Mem 0 N- W W BTDM Outlet Couter Data Mem B Ctrl Mem B ctrl Multiple Data Copy Metod - 6 -
7 4. MULTISTGE TIME-SPCE SWITCING Time-multiplexed space switch: Multistage time-space architectures are ecessary for the desig of large switches. The time stages i these desigs are similar to the TSI modules discussed previously. owever, space switches that wor i cojuctio with time switches should be able to chage their coectio patters o every time slot. Such space switches are ow as time multiplexed space switches (TMSS). The architecture of a time multiplexed space switch operatig o TDM sigals which have N time slots is show below: TDM Ilets TDM Outlets Ilets Selector Outlets Symbol Selector TS N- Time slot couter Cotrol Memory Equivalet space switch Implemetatio Time multiplexed space switch simple implemetatio of this switch cosists of a ba of selectors, each of which has the TDM ilets, ad a N-word cotrol memory addressed by a time slot couter. The specific ilet selected by each of these selectors i every time slot is cotrolled by the output of the cotrol memory. The umber of bits required i the cotrol word for this implemetatio is log. Sice this switch realizes a differet itercoectio patter for each of the N time slots, its space equivalet represetatio cosists of a ba of N switches, oe for each time slot. Noblocig STS Switch: The TSI modules ad the TMSS ca be combied to implemet large multistage etwors. Cosider the desig of a N -lie switch usig TSI modules capable of operatig o TDM lies with N time slots. Such a switch ca be implemeted with a STS architecture show below: TDM Ilets TSI TDM Outlets TSI x TSI STS Switch The equivalet space switch for the STS cofiguratio is depicted below: - 7 -
8 N x N TSI x TS N x N TSI x TS TS N- N x N TSI x TS N- Space equivalet of the STS switch From Clo's theorem, we require = - for this switch to be strictly oblocig. It should be poited out that, for a give total umber of chaels (N i this case), we pic the value of N so as to operate the TSI modules close to their maximum speed. This usually leads to more ecoomical desigs sice the cost of a memory bit is much smaller tha that of a crosspoit. ssumig that a crosspoit costs M times as much as a memory bit, the complexity of the switch ca be characterized by: Switch complexity = Total amout of memory + M x Total umber of cross poits Noblocig TST switch: To costruct strictly oblocig switches usig the TST structure, we eed TSI modules i which the umber of time slots i the ilet TDM sigal is differet tha that i the outlet TDM sigal. Furthermore, we will set the first stage expasio ratio (or the third stage compressio ratio) / = to simplify the desig. The desig of TSI modules which perform the expasio ad cocetratio fuctios is show below: / TDM Ilet word data mem / TDM Outlet / TDM Ilet word data mem / TDM Outlet x z cloc Iput time slot couter x z cloc word cotrol memory Output time slot couter x z cloc word cotrol memory Iput time slot couter Output time slot couter x z cloc Iput - Output - - Data Mem W - W - Output - Iput - - Data Mem W - W W - W Time Expader Time Cocetrator It should be oted that the data ad cotrol memories i these TSI modules have to be twice as fast compared to the ormal TSI module which has the same umber of time slots o the ilets - -
9 ad outlets. Equivaletly, for the same memory speed, the TDM sigals termiatig o the expader ad cocetrator TSI modules are allowed to cotai oly half as may chaels. The desig of a strictly oblocig TST switch usig these modules ad the TMSS is show below for the case of N = chaels: / TSI / / TSI / TSI x TSI TSI TSI TDM Ilets TST Switch TDM Outlets The space equivalet of this switch is: x x x x TS x x x x TS - x Space equivalet of TST switch The complexity of this switch ca be evaluated as before. Geerally, for large strictly oblocig switches, STS desigs tur out to be more ecoomical tha TST desigs. Furthermore, the delay through the STS switch is smaller
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