Workshop 1: Specification for SystemC-AADL interoperability
|
|
- Daisy Phillips
- 5 years ago
- Views:
Transcription
1 Workshop 1: System Design in Avionics & Space Specification for -AADL interoperability Eugenio Villar Eduardo de las Heras Microelectronic Engineering Group University of Cantabria
2 Outline Motivations General Concepts AADL PERFidiX and SCope AADL- Design Flow Mapping AADL to Example
3 Motivations System design issues: Incomplete capture of specification Need for design refinement and validation Impact of functional and non-functional properties Timing properties Platform architecture Software/Hardware co-design
4 AADL Concepts AADL Basic elements PIM PSM
5 Concepts features Standard platform for system design (IEEE 1666) developed by the OSCI C++ extension Strict-time, event driven simulator Concurrent Execution Kernel
6 Concepts Basic Elements
7 SCoPE Concepts System Co-simulation and Performance Estimation in Multi-processor SW source-code simulation OS Modelling POSIX Timed SW simulation Performance estimation of SW code Time & Power
8 SCoPE Concepts PIM Application Code Task 1... Task n Memory Proc. 1 POSIX API Packages PERFidiX Drivers Proc. 2 Proc. n PSM Memory Bus 1 Bus n Devices Devices Devices Devices
9 AADL- Design Flow AADL Application Model AADL Execution Platform Model AADL To translation Platform independent description Platform model AADL To Scope parameters translation Binding executable model Performance analysis Simulation Configuration parameters SCope
10 AADL to Framework Graphical editor ECLIPSE OSATE Textual editor AADL Model SC SC HW HW description C/C++ Code XMI XMI file file Refinement integrator and generator HetSC SCV SCV Configuration parameters Simulation SCope Performance analysis
11 AADL Semantics in AADL Thread: Schedulable unit of sequential source code. Properties Dispatch protocol Period Deadline SC_THREAD: Is Called once when simulation Start. Properties Specific SC_THREAD implementation SC_TIME, wait ( SC_TIME) Assertions SCV
12 AADL Semantics in AADL Process: space partitioning where protection is provided SC_MODULE: principle structural building blocks of Subprogram: sequentially executable source text C++ function: called from the SC_THREAD
13 AADL Semantics in AADL Data: Enable manipulate data in concurrently in non-deterministic order. Properties Concurrency_Control_Protocol Channel: Enable communication between modules Properties Semaphores, mutex, custom channels.
14 AADL Semantics in AADL Processor: Abstraction of hardware and software responsible for scheduling and executing threads. Properties Process_Swap_Execution_time Thread_Swap_Execution_time Scheduling_Protocols High level, POSIX simulation library and performance Analysis SCope configuration parameters POSIX scheduling_protocols
15 AADL Semantics in AADL Memory: platform component that stores binary images. Bus: platform component that can exchange control and data between modules. Properties Transmission time, propagation delay System Co-simulation and Performance Estimation in SCope configuration parameters
16 AADL Semantics in AADL Devices: Execution platform component that interface with the exterior Event data port Event port Data port Ports and Connections: Logical Connections to exchange control and data between threads. description at various levels: TLM RTL Synthesis Signal channel, ports, interface FIFO channel ports, interface Custom Channels, ports, interface
17 Example system_example Refinement
18 Example process_producer thread_producer Refinement
19 Example thread_producer Refinement
20 Conclusions allows modeling AADL Different abstraction levels Refinement Validation Specification for model transformation from AADL to Tool proposal for embedded system design
21 END THANK YOU FOR YOUR ATTENTION QUESTIONS?
MoCC - Models of Computation and Communication SystemC as an Heterogeneous System Specification Language
SystemC as an Heterogeneous System Specification Language Eugenio Villar Fernando Herrera University of Cantabria Challenges Massive concurrency Complexity PCB MPSoC with NoC Nanoelectronics Challenges
More informationAADS+: AADL Simulation including the Behavioral Annex
AADS+: AADL Simulation including the Behavioral Annex Fifth IEEE International workshop UML and AADL 24th March 2010, Oxford, UK Roberto Varona Gómez Eugenio Villar {roberto, evillar}@teisa.unican.es University
More informationSCope: Efficient HdS simulation for MpSoC with NoC
SCope: Efficient HdS simulation for MpSoC with NoC Eugenio Villar Héctor Posadas University of Cantabria Marcos Martínez DS2 Motivation The microprocessor will be the NAND gate of the integrated systems
More informationAADL Simulation and Performance Analysis in SystemC
Fourth IEEE International workshop UML and AADL 2nd June 2009 Potsdam, Germany Roberto Varona Gómez Eugenio Villar {roberto, evillar}@teisa.unican.es University of Cantabria, Santander, Spain. This work
More informationModeling and SW Synthesis for
Modeling and SW Synthesis for Heterogeneous Embedded Systems in UML/MARTE Hector Posadas, Pablo Peñil, Alejandro Nicolás, Eugenio Villar University of Cantabria Spain Motivation Design productivity it
More informationModeling Software with SystemC 3.0
Modeling Software with SystemC 3.0 Thorsten Grötker Synopsys, Inc. 6 th European SystemC Users Group Meeting Stresa, Italy, October 22, 2002 Agenda Roadmap Why Software Modeling? Today: What works and
More informationA MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models
A MDD Methodology for Specification of Embedded Systems and Automatic Generation of Fast Configurable and Executable Performance Models Int. Conf. on HW/SW codesign and HW synthesis (CODES-ISSS 2012) Embedded
More informationPresentation of the AADL: Architecture Analysis and Design Language
Presentation of the AADL: Architecture Analysis and Design Language Outline 1. AADL a quick overview 2. AADL key modeling constructs 1. AADL components 2. Properties 3. Component connection 3. AADL: tool
More informationAADL : about code generation
AADL : about code generation AADL objectives AADL requirements document (SAE ARD 5296) Analysis and Generation of systems Generation can encompasses many dimensions 1. Generation of skeletons from AADL
More informationPresentation of the AADL: Architecture Analysis and Design Language
Presentation of the AADL: Architecture Analysis and Design Language Outline 1. AADL a quick overview 2. AADL key modeling constructs 1. AADL components 2. Properties 3. Component connection 3. AADL: tool
More informationAn Information Model for High-Integrity Real Time Systems
An Information Model for High-Integrity Real Time Systems Alek Radjenovic, Richard Paige, Philippa Conmy, Malcolm Wallace, and John McDermid High-Integrity Systems Group, Department of Computer Science,
More informationAADL Inspector Tutorial. ACVI Workshop, Valencia September 29th, Pierre Dissaux. Ellidiss. Technologies w w w. e l l i d i s s.
AADL Inspector Tutorial ACVI Workshop, Valencia September 29th, 2014 Pierre Dissaux Ellidiss Technologies w w w. e l l i d i s s. c o m Independent Technology Provider: Ellidiss Software w w w. e l l i
More informationAUTOBEST: A United AUTOSAR-OS And ARINC 653 Kernel. Alexander Züpke, Marc Bommert, Daniel Lohmann
AUTOBEST: A United AUTOSAR-OS And ARINC 653 Kernel Alexander Züpke, Marc Bommert, Daniel Lohmann alexander.zuepke@hs-rm.de, marc.bommert@hs-rm.de, lohmann@cs.fau.de Motivation Automotive and Avionic industry
More informationEmbedded System Design and Modeling EE382V, Fall 2008
Embedded System Design and Modeling EE382V, Fall 2008 Lecture Notes 4 System Design Flow and Design Methodology Dates: Sep 16&18, 2008 Scribe: Mahesh Prabhu SpecC: Import Directive: This is different from
More informationA Model-based, Single-Source approach to Design-Space Exploration and Synthesis of Mixed-Criticality Systems
A Model-based, Single-Source approach to Design-Space Exploration and Synthesis of Mixed-Criticality Systems Reusability Optimization Architectural Mapping Schedulablity Analysis SW Synthesis Simulation
More informationInvestigation of System Timing Concerns in Embedded Systems: Tool-based Analysis of AADL Models
Investigation of System Timing Concerns in Embedded Systems: Tool-based Analysis of AADL Models Peter Feiler Software Engineering Institute phf@sei.cmu.edu 412-268-7790 2004 by Carnegie Mellon University
More informationChapter 2 M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration
Chapter 2 M3-SCoPE: Performance Modeling of Multi-Processor Embedded Systems for Fast Design Space Exploration Hector Posadas, Sara Real, and Eugenio Villar Abstract Design Space Exploration for complex,
More informationPOK. An ARINC653-compliant operating system released under the BSD licence. Julien Delange, European Space Agency
POK An ARINC653-compliant operating system released under the BSD licence Julien Delange, European Space Agency Laurent Lec, MakeMeReach Introduction Problems
More informationRAMSES. Refinement of AADL Models for the Synthesis of Embedded Systems. Etienne Borde
Refinement of AADL Models for the Synthesis of Embedded Systems Etienne Borde etienne.borde@telecom-paristech.fr AADL: Architecture Analysis and Design Language We use AADL to model SCES architectures:
More informationFast and Accurate Source-Level Simulation Considering Target-Specific Compiler Optimizations
FZI Forschungszentrum Informatik at the University of Karlsruhe Fast and Accurate Source-Level Simulation Considering Target-Specific Compiler Optimizations Oliver Bringmann 1 RESEARCH ON YOUR BEHALF Outline
More informationAn Approach for Execution of MARTE-based Application Models
An Approach for Execution of MARTE-based Application Models Workshop on Distributed Object Computing for Real-time and Embedded Systems Washington, DC, USA July 16th, 2008 C. Mraidha, A. Cuccuru and S.
More informationHardware-Software Codesign. 6. System Simulation
Hardware-Software Codesign 6. System Simulation Lothar Thiele 6-1 System Design specification system simulation (this lecture) (worst-case) perf. analysis (lectures 10-11) system synthesis estimation SW-compilation
More informationFrom MDD back to basic: Building DRE systems
From MDD back to basic: Building DRE systems, ENST MDx in software engineering Models are everywhere in engineering, and now in software engineering MD[A, D, E] aims at easing the construction of systems
More informationThe Montana Toolset: OSATE Plugins for Analysis and Code Generation
Fremont Associates Process Project QA The Montana Toolset: OSATE Plugins for Analysis and Code Generation Oleg Sokolsky University of Pennsylvania AADL Workshop 005 Paris, France October 17-18, 18, 005
More informationModular SystemC. In-house Training Options. For further information contact your local Doulos Sales Office.
Modular SystemC is a set of modules related to SystemC TM (IEEE 1666-2005) aimed at fulfilling teambased training requirements for engineers from a range of technical backgrounds, i.e. hardware and software
More informationOutline. SLD challenges Platform Based Design (PBD) Leveraging state of the art CAD Metropolis. Case study: Wireless Sensor Network
By Alberto Puggelli Outline SLD challenges Platform Based Design (PBD) Case study: Wireless Sensor Network Leveraging state of the art CAD Metropolis Case study: JPEG Encoder SLD Challenge Establish a
More informationExecutable AADL. Real Time Simulation of AADL Models. Pierre Dissaux 1, Olivier Marc 2.
Executable AADL Real Time Simulation of AADL Models Pierre Dissaux 1, Olivier Marc 2 1 Ellidiss Technologies, Brest, France. 2 Virtualys, Brest, France. pierre.dissaux@ellidiss.com olivier.marc@virtualys.com
More informationLab-STICC : Dominique BLOUIN Skander Turki Eric SENN Saâdia Dhouib 11/06/2009
Lab-STICC : Power Consumption Modelling with AADL Dominique BLOUIN Skander Turki Eric SENN Saâdia Dhouib 11/06/2009 Outline Context Review of power estimation methodologies and tools Functional Level Power
More informationHardware Design and Simulation for Verification
Hardware Design and Simulation for Verification by N. Bombieri, F. Fummi, and G. Pravadelli Universit`a di Verona, Italy (in M. Bernardo and A. Cimatti Eds., Formal Methods for Hardware Verification, Lecture
More informationIntroduction to AADL analysis and modeling with FACE Units of Conformance
Introduction to AADL analysis and modeling with FACE Units of Conformance AMRDEC Aviation Applied Technology Directorate Contract Number W911W6-17- D-0003 Delivery Order 3 This material is based upon work
More informationReconOS: An RTOS Supporting Hardware and Software Threads
ReconOS: An RTOS Supporting Hardware and Software Threads Enno Lübbers and Marco Platzner Computer Engineering Group University of Paderborn marco.platzner@computer.org Overview the ReconOS project programming
More information4 th European SystemC Users Group Meeting
4 th European SystemC Users Group Meeting http://www-ti.informatik.uni-tuebingen.de/systemc Copenhagen October 5 th, 2001, 1100-1600 SystemC 2.0 Tutorial Thorsten Grötker R & D Manager Synopsys, Inc. Motivation
More informationADeS presentation. a simulator for AADL v Amélie Schyn Romain Sezestre Jean-François Tilman
ADeS presentation a simulator for AADL v0.2.3 Amélie Schyn Romain Sezestre Jean-François Tilman 1 Agenda Objective of the simulation Presentation of the tool Demonstration To go further 2 Part I Objective
More informationCode Generation for QEMU-SystemC Cosimulation from SysML
Code Generation for QEMU- Cosimulation from SysML Da He, Fabian Mischkalla, Wolfgang Mueller University of Paderborn/C-Lab, Fuerstenallee 11, 33102 Paderborn, Germany {dahe, fabianm, wolfgang}@c-lab.de
More informationUsing AADL in Model Driven Development. Katholieke Universiteit Leuven Belgium
Using AADL in Model Driven Development Didier Delanote, Stefan Van Baelen, Wouter Joosen and Yolande Berbers Katholieke Universiteit Leuven Belgium Contents Introduction Overview of AADL Usability assessment
More informationTowards a SystemC Transaction Level Modeling Standard. Stuart Swan Senior Architect Cadence Design Systems, Inc. June 2004
Towards a SystemC Transaction Level Modeling Standard Stuart Swan Senior Architect Cadence Design Systems, Inc. June 2004 SystemC Transaction Level Modeling What is TLM? Communication uses function calls
More informationPlug-in Development for the Open Source AADL Tool Environment Part 3: Generation & External Models
Plug-in Development for the Open Source AADL Tool Environment Part 3: Generation & External Models Peter Feiler / Aaron Greenhouse Software Engineering Institute (phf / aarong)@sei.cmu.edu 412-268- (7790
More informationArchitecture Description Languages. Peter H. Feiler 1, Bruce Lewis 2, Steve Vestal 3 and Ed Colbert 4
Architecture Description Languages An Overview of the SAE Architecture Analysis & Design Language (AADL) Standard: A Basis for Model-Based Architecture-Driven Embedded Systems Engineering Peter H. Feiler
More informationTransaction Level Modeling with SystemC. Thorsten Grötker Engineering Manager Synopsys, Inc.
Transaction Level Modeling with SystemC Thorsten Grötker Engineering Manager Synopsys, Inc. Outline Abstraction Levels SystemC Communication Mechanism Transaction Level Modeling of the AMBA AHB/APB Protocol
More informationChoosing IP-XACT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms
hoosing IP-XAT IEEE 1685 standard as a unified description for timing and power performance estimations in virtual platforms platforms Emmanuel Vaumorin (Magillem Design Services) Motivation New needs
More informationAADL Meta Model & XML/XMI
AADL Meta Model & XML/XMI Peter Feiler Software Engineering Institute phf@sei.cmu.edu Meta Modeling Approach Declarative AADL Model AADL Instance Model Outline 2 XMI/XML Based Tool Interoperability Textual
More informationSchedulability Analysis of AADL Models
Schedulability Analysis of AADL Models Oleg Sokolsky Insup Lee University of Pennsylvania Duncan Clarke Fremont Associates Overview AADL modeling language Why is it useful and what it has Formal schedulability
More informationThe Ocarina Tool Suite. Thomas Vergnaud
The Ocarina Tool Suite Motivation 2 ENST is developing a middleware architecture: PolyORB generic, configurable, interoperable enables middleware verification create a tool chain
More informationMODELING OF MULTIPROCESSOR HARDWARE PLATFORMS FOR SCHEDULING ANALYSIS
1 MODELING OF MULTIPROCESSOR HARDWARE PLATFORMS FOR SCHEDULING ANALYSIS Stéphane Rubini, Christian Fotsing, Frank Singhoff, Hai Nam Tran Lab-STICC, University of Western Britany (UBO) Contact: Stephane.Rubini@univ-brest.fr
More informationTranslating AADL into BIP Application to the Verification of Real time Systems
Toulouse, France (in conjunction with MODELS 2008) 1st International Workshop on Model Based Architecting and Construction of Embedded Systems (ACESMB 2008) Translating AADL into BIP Application to the
More informationThe SystemC Verification Standard (SCV) Stuart Swan Senior Architect Cadence Design Systems, Inc.
The SystemC Verification Standard (SCV) Stuart Swan Senior Architect Cadence Design Systems, Inc. stuart@cadence.com The Verification Problem System Level Verification is typically done last, is typically
More informationChapter 2 Overview of SystemC
Chapter 2 Overview of SystemC The previous chapters gave a brief context for the application of SystemC. This chapter presents an overview of the SystemC language elements. Details are discussed in-depth
More informationShort Term Courses (Including Project Work)
Short Term Courses (Including Project Work) Courses: 1.) Microcontrollers and Embedded C Programming (8051, PIC & ARM, includes a project on Robotics) 2.) DSP (Code Composer Studio & MATLAB, includes Embedded
More informationAUTOBEST: A microkernel-based system (not only) for automotive applications. Marc Bommert, Alexander Züpke, Robert Kaiser.
AUTOBEST: A microkernel-based system (not only) for automotive applications Marc Bommert, Alexander Züpke, Robert Kaiser vorname.name@hs-rm.de Outline Motivation AUTOSAR ARINC 653 AUTOBEST Architecture
More informationCosimulation of ITRON-Based Embedded Software with SystemC
Cosimulation of ITRON-Based Embedded Software with SystemC Shin-ichiro Chikada, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada Graduate School of Information Science, Nagoya University Information Technology
More informationTowards AADL to SystemC mapping for partitioned systems. Etienne Borde Laurent Pautet Marc Gatti
Towards AADL to SystemC mapping for partitioned systems Michael Lafaye Etienne Borde Laurent Pautet Marc Gatti Presentation of a First Mapping Prototype: AADL to SystemC for Avionics Partitioned Systems
More informationSystem-level design refinement using SystemC. Robert Dale Walstrom. A thesis submitted to the graduate faculty
System-level design refinement using SystemC by Robert Dale Walstrom A thesis submitted to the graduate faculty in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Major: Computer
More informationProject Report. Using the AADL to support the ASSERT modeling process
Project Report Using the AADL to support the ASSERT modeling process Pierre Dissaux (Ellidiss) AADL committee Salt Lake City April 16, 2007 Copyright 2004-2007 ASSERT Project 1 Goals Improve system-and-software
More informationxuml, AADL and Beyond
xuml and AADL xuml, AADL and Beyond Chris Raistrick www.kc.com xuml and AADL xuml Overview Chris Raistrick www.kc.com Platform Independent Model A Platform Independent Model (PIM) is a technology agnostic
More informationSWE 760 Lecture 1: Introduction to Analysis & Design of Real-Time Embedded Systems
SWE 760 Lecture 1: Introduction to Analysis & Design of Real-Time Embedded Systems Hassan Gomaa References: H. Gomaa, Chapters 1, 2, 3 - Real-Time Software Design for Embedded Systems, Cambridge University
More informationA Meta-Modeling-Based Approach for Automatic Generation of Fault- Injection Processes
A Meta-Modeling-Based Approach for Automatic Generation of Fault- Injection Processes B.-A. Tabacaru, M. Chaari, W. Ecker, T. Kruse Infineon Technologies AG Accellera Systems Initiative 1 Outline Motivation
More informationAADL v2.1 errata AADL meeting Sept 2014
AADL v2.1 errata AADL meeting Sept 2014 Software Engineering Institute Carnegie Mellon University Pittsburgh, PA 15213 V2.1 Errata Additional applies to allowances Inconsistency in reference/applies to
More informationEmbedded Software Generation from System Level Design Languages
Embedded Software Generation from System Level Design Languages Haobo Yu, Rainer Dömer, Daniel Gajski Center for Embedded Computer Systems University of California, Irvine, USA haoboy,doemer,gajski}@cecs.uci.edu
More informationAutomatic deployment of component-based embedded systems from UML/MARTE models using MCAPI
Automatic deployment of component-based embedded systems from UML/MARTE models using MCAPI Alejandro Nicolas, Hector Posadas, Pablo Peñil, Eugenio Villar University of Cantabria Santander, Spain {nicolasa,
More informationArchitecture Modeling in embedded systems
Architecture Modeling in embedded systems Ákos Horváth Model Driven Software Development Lecture 11 Budapest University of Technology and Economics Department of Measurement and Information Systems Abstract
More informationOSATE Analysis Support
OSATE Analysis Support Software Engineering Institute Carnegie Mellon University Pittsburgh, PA 15213 Julien Delange/Peter Feiler 07/08/2013 Overview of OSATE2 Eclipse-based AADL editor Support for AADLv2.1,
More informationAADL committee, Valencia October 2 nd, Pierre Dissaux (Ellidiss) Maxime Perrotin (ESA)
AADL committee, Valencia October 2 nd, 2014 Pierre Dissaux (Ellidiss) Maxime Perrotin (ESA) what is TASTE? A tool-chain targeting heterogeneous, embedded systems, using a model-centric development approach
More informationCommercial Real-time Operating Systems An Introduction. Swaminathan Sivasubramanian Dependable Computing & Networking Laboratory
Commercial Real-time Operating Systems An Introduction Swaminathan Sivasubramanian Dependable Computing & Networking Laboratory swamis@iastate.edu Outline Introduction RTOS Issues and functionalities LynxOS
More information10 th AUTOSAR Open Conference
10 th AUTOSAR Open Conference Yuchen Zhou, Thomas E Fuhrman, Prathap Venugopal General Motors Scheduling Techniques for Automated Driving Systems using the AUTOSAR Adaptive Platform AUTOSAR Nov-2017 Agenda
More informationAn Implementation of the Behavior Annex in the AADL-toolset Osate2
2011 16th IEEE International Conference on Engineering of Complex Computer Systems An Implementation of the Behavior Annex in the AADL-toolset Osate2 Gilles Lasnier, Laurent Pautet Inst. TELECOM - TELECOM
More informationLINUX INTERNALS & NETWORKING Weekend Workshop
Here to take you beyond LINUX INTERNALS & NETWORKING Weekend Workshop Linux Internals & Networking Weekend workshop Objectives: To get you started with writing system programs in Linux Build deeper view
More informationThe AADL Behavioural annex 1
1 IRIT-CNRS ; Université de Toulouse, France Ellidis Software France-UK SEI CMU USA Wednesday March 24 th 2010 OXFORD UML-AADL 2010 Panel 1 This work was partly supported by the French AESE project Topcased
More informationModel Editing & Processing Tools. AADL Committee, San Diego February 4th, Pierre Dissaux. Ellidiss. Technologies w w w. e l l i d i s s.
Model Editing & Processing Tools AADL Committee, San Diego February 4th, 2015 Pierre Dissaux Technologies w w w. e l l i d i s s. c o m Independent Technology Provider: Software w w w. e l l i d i s s.
More informationHardware in the Loop Functional Verification Methodology
OMG's Third Software-Based Communications Workshop: Realizing the Vision Hardware in the Loop Functional Verification Methodology by Pascal Giard Jean-François Boland, Jean Belzile M.Ing. Student École
More informationMessage-Passing Shared Address Space
Message-Passing Shared Address Space 2 Message-Passing Most widely used for programming parallel computers (clusters of workstations) Key attributes: Partitioned address space Explicit parallelization
More informationModel driven Engineering & Model driven Architecture
Model driven Engineering & Model driven Architecture Prof. Dr. Mark van den Brand Software Engineering and Technology Faculteit Wiskunde en Informatica Technische Universiteit Eindhoven Model driven software
More informationQEMU and SystemC. Màrius Màrius Montón
QEMU and SystemC March March 2011 2011 QUF'11 QUF'11 Grenoble Grenoble Màrius Màrius Montón Outline Introduction Objectives Virtual Platforms and SystemC Checkpointing for SystemC Conclusions 2 Introduction
More informationAADL Graphical Editor Design
AADL Graphical Editor Design Peter Feiler Software Engineering Institute phf@sei.cmu.edu Introduction An AADL specification is a set of component type and implementation declarations. They are organized
More information2. HW/SW Co-design. Young W. Lim Thr. Young W. Lim 2. HW/SW Co-design Thr 1 / 21
2. HW/SW Co-design Young W. Lim 2016-03-11 Thr Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 1 / 21 Outline 1 Software Engineering Young W. Lim 2. HW/SW Co-design 2016-03-11 Thr 2 / 21 Based on Software
More informationGLOSSARY. VisualDSP++ Kernel (VDK) User s Guide B-1
B GLOSSARY Application Programming Interface (API) A library of C/C++ functions and assembly macros that define VDK services. These services are essential for kernel-based application programs. The services
More informationDependability Modeling Based on AADL Description (Architecture Analysis and Design Language)
Dependability Modeling Based on AADL Description (Architecture Analysis and Design Language) Ana Rugina, Karama Kanoun and Mohamed Kaâniche {rugina, kanoun, kaaniche}@laas.fr European Integrated Project
More informationCS A331 Programming Language Concepts
CS A331 Programming Language Concepts Lecture 12 Alternative Language Examples (General Concurrency Issues and Concepts) March 30, 2014 Sam Siewert Major Concepts Concurrent Processing Processes, Tasks,
More informationIntroduction to MLM. SoC FPGA. Embedded HW/SW Systems
Introduction to MLM Embedded HW/SW Systems SoC FPGA European SystemC User s Group Meeting Barcelona September 18, 2007 rocco.le_moigne@cofluentdesign.com Agenda Methodology overview Modeling & simulation
More informationSystem-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex)
System-level co-modeling AADL and Simulink specifications using Polychrony (and Syndex) AADL Standards Meeting June 6., 2011 Jean-Pierre Talpin, INRIA Parts of this presentation are joint work with Paul,
More informationLG2: Lecture Group 2: SystemC. Topic: SystemC Overview. LG2.1 - SC SystemC Components. LG2.2 - SC Example (Counter)
LG2: Lecture Group 2: SystemC. Topic: SystemC Overview LG2.1 - SC SystemC Components LG2.2 - SC Example (Counter) LG2.3 - SC SystemC Structural Netlist LG2.4 - SC SystemC Signals LG2.5 - SC Threads and
More informationSemantics-Based Integration of Embedded Systems Models
Semantics-Based Integration of Embedded Systems Models Project András Balogh, OptixWare Research & Development Ltd. n 100021 Outline Embedded systems overview Overview of the GENESYS-INDEXYS approach Current
More informationModel-Driven Analysis of Security, Reliability, Test, Privacy, Safety and Trust of IoE Services. Eugenio Villar University of Cantabria
Model-Driven Analysis of Security, Reliability, Test, Privacy, Safety and Trust of IoE Services Eugenio Villar University of Cantabria Agenda Introduction Single-Source Embedded Systems Design Model-driven
More informationSimulation Verification of multiple levels of constraints for system level designs in systemc
Simulation Verification of multiple levels of constraints for system level designs in systemc Piyush Ranjan Satapathy, Xi Chen and Harry C. Hsieh Department of Computer Science University of California,
More informationSystemC Modelling of the Embedded Networks
Saint Petersburg State University of Aerospace Instrumentation, Russia; Nokia Research Center and Nokia Devices, Finland. SystemC Modelling of the Embedded Networks Valentin Olenev, Yuriy Sheynin, Elena
More informationSystematic Embedded Software Generation from SystemC
Systematic Embedded Software Generation from F. Herrera, H. Posadas, P. Sánchez & E. Villar TEISA Dept., E.T.S.I. Industriales y Telecom., University of Cantabria Avda. Los Castros s/n, 39005 Santander,
More informationReconOS: Multithreaded Programming and Execution Models for Reconfigurable Hardware
ReconOS: Multithreaded Programming and Execution Models for Reconfigurable Hardware Enno Lübbers and Marco Platzner Computer Engineering Group University of Paderborn {enno.luebbers, platzner}@upb.de Outline
More informationBeiHang Short Course, Part 2: Description and Synthesis
BeiHang Short Course, Part 2: Operation Centric Hardware Description and Synthesis J. C. Hoe, CMU/ECE/CALCM, 2014, BHSC L2 s1 James C. Hoe Department of ECE Carnegie Mellon University Collaborator: Arvind
More informationUML&AADL 11 An Implementation of the Behavior Annex in the AADL-toolset OSATE2
UML&AADL 11 An Implementation of the Behavior Annex in the AADL-toolset OSATE2 Jérôme Hugues Gilles Lasnier Laurent Pautet Lutz Wrage jerome.hugues@isae.fr gilles.lasnier@telecom-paristech.fr laurent.pautet@telecom-paristech.fr
More informationAADL to build DRE systems, experiments with Ocarina. Jérôme Hugues, ENST
AADL to build DRE systems, experiments with Ocarina Jérôme Hugues, ENST ENST Research topic: Methods for DRE Building a DRE is still a complex issue: RT-CORBA, DDS are only partial solutions Still difficult
More informationOutline. Introduction. Survey of Device Driver Management in Real-Time Operating Systems
Survey of Device Driver Management in Real-Time Operating Systems Sebastian Penner +46705-396120 sebastian.penner@home.se 1 Outline Introduction What is a device driver? Commercial systems General Description
More informationAADL Subsets Annex Update
AADL Subsets Annex Update V. Gaudel, P. Dissaux, A. Plantec, F. Singhoff, J. Hugues*, J. Legrand University of Brest/UBO, Lab-Sticc, France Ellidiss Technologies, France *Institut Supérieur de l Aéronautique
More information0. Overview of this standard Design entities and configurations... 5
Contents 0. Overview of this standard... 1 0.1 Intent and scope of this standard... 1 0.2 Structure and terminology of this standard... 1 0.2.1 Syntactic description... 2 0.2.2 Semantic description...
More informationFPGAs: High Assurance through Model Based Design
FPGAs: High Assurance through Based Design AADL Workshop 24 January 2007 9:30 10:00 Yves LaCerte Rockwell Collins Advanced Technology Center 400 Collins Road N.E. Cedar Rapids, IA 52498 ylacerte@rockwellcollins.cm
More informationDie virtuelle Plattform:
Die virtuelle Plattform: Der Einsatz von Zynq fuer die Verifikation und das Debugging von konfigurierbaren Systemen Dr. Endric Schubert Missing Link Electronics Marlene-Dietrich-Straße 5 89231 Neu-Ulm
More informationIntroduction to SystemC
Introduction to SystemC Damien Hubaux - CETIC Outline?? A language A C++ library February 12, 2004 SystemC, an alternative for system modeling and synthesis? 2 Why SystemC? Needs Increasing complexity,
More informationPredicting Null-Pointer Dereferences in Concurrent Programs. Parthasarathy Madhusudan Niloofar Razavi Francesco Sorrentino
Predicting Null-Pointer Dereferences in Concurrent Programs After work by: Azadeh Farzan Parthasarathy Madhusudan Niloofar Razavi Francesco Sorrentino Overview The problem The idea The solution The evaluation
More informationA Frame Study for Post-Processing Analysis on System Behavior: A Case Study of Deadline Miss Detection
Journal of Computer Science 6 (12): 1505-1510, 2010 ISSN 1549-3636 2010 Science Publications A Frame Study for Post-Processing Analysis on System Behavior: A Case Study of Deadline Miss Detection Junghee
More informationEuropean Component Oriented Architecture (ECOA ) Collaboration Programme: Architecture Specification Part 2: Definitions
European Component Oriented Architecture (ECOA ) Collaboration Programme: Part 2: Definitions BAE Ref No: IAWG-ECOA-TR-012 Dassault Ref No: DGT 144487-D Issue: 4 Prepared by BAE Systems (Operations) Limited
More informationECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling
ECE 587 Hardware/Software Co-Design Spring 2018 1/20 ECE 587 Hardware/Software Co-Design Lecture 12 Verification II, System Modeling Professor Jia Wang Department of Electrical and Computer Engineering
More informationProcesses and Threads. Processes: Review
Processes and Threads Processes and their scheduling Threads and scheduling Multiprocessor scheduling Distributed Scheduling/migration Lecture 3, page 1 Processes: Review Multiprogramming versus multiprocessing
More information