Moby/plc { Graphical Development of. University of Oldenburg { Department of Computer Science. P.O.Box 2503, D Oldenburg, Germany

Size: px
Start display at page:

Download "Moby/plc { Graphical Development of. University of Oldenburg { Department of Computer Science. P.O.Box 2503, D Oldenburg, Germany"

Transcription

1 Moby/plc { Graphical Development of PLC-Automata??? Josef Tapken and Henning Dierks University of Oldenburg { Department of Computer Science P.O.Box 2503, D Oldenburg, Germany Fax: ftapken,dierksg@informatik.uni-oldenburg.de Abstract. Moby/plc is a graphical design tool for PLC-Automata, a special class of hierarchical real-time automata suitable for the description of distributed real-time systems that are implementable on a widely used hardware platform, so-called Programmable Logic Controllers (PLCs). In this paper we sketch the modelling language in use and some features of Moby/plc, like several validation methods and code generation. 1 Introduction Moby/plc is a graphical design tool for distributed real-time systems which is based upon a formal description technique called PLC-Automata [6]. This class of hierarchical real-time automata is suitable (but not restricted) to the description of the behaviour of Programmable Logic Controllers (PLC) that are often used to solve real-time controlling problems. The automata are tailored to a structural compilation into executable PLC-code and are provided with a formal denotational semantics in Duration Calculus [3] as well as an operational semantics in terms of Timed Automata [1]. Both semantics are consistent and allow formal reasoning about properties of PLC-Automata [7]. The language of PLC-Automata, developed in the UniForM-project [8], has been applied to real-world case studies of the industrial partner, which produces tram- and railway control systems. This paper gives a survey of Moby/plc by introducing its implemented modelling language (Sec. 2), and by describing some of its features (Sec. 3).? cspringer-verlag. This paper is published in A.P.Ravn, and H.Rischel, editors, Proceedings of FTRTFT'98, Volumn 1486, LNCS, Springer, 1998?? This research was partially supported by the German Ministry for Education and Research (BMBF) as part of the project UniForM under grant No. FKZ 01 IS 521 B3 and partially by the Leibniz Programme of the Deutsche Forschungsgemeinschaft (DFG) under grant No. Ol 98/1-1.

2 2 PLC-Automata Programmable Logic Controllers (PLC) are real-time controllers with a cyclic behaviour. In each cycle the PLC polls input values from sensors or other PLCs, computes the new local state, and generates output values for actuators (or other PLCs). To deal with real-time problems, PLCs are enriched by a convenient timer concept. A PLC-Automaton describes the behaviour of a PLC by an extended nite state machine with three categories of variables, namely input, local, and output variables. A transition is labelled by a condition on these variables and a list of assignments to local and output variables. In every cycle a PLC-Automaton updates its input variables from the environment and performs (exactly) one transition according to the actual state and values of variables. The execution of a transition may be prohibited according to a state label which consists of a time value d (2 IR0) and a Boolean expression over the input variables. A state can only be left if it is held for longer than for d time units or the state expression evaluates to false. In order to increase their expressiveness and structuring facilities PLC-Automata are enhanced by a hierarchy concept which is based on state renement, i.e. a state can represent a set of substates and its label can also restrict the outgoing transitions of the substates. A system specication consists of a network of PLC-Automata which communicate asynchronously with each other through channels. Each channel links an output variable of one automaton to an input variable of another, i.e. communication is performed implicitly by updating every cycle the input variables of a PLC-Automaton with the current values of the corresponding output variables. The system network may also be structured hierarchically. In [5] the implemented version of PLC-Automata is related to its formal denition. All extensions implemented in Moby/plc, like variables and dierent kinds of transitions, are interpreted as abbreviations and can be unfolded. Fig. 1 shows a small part of a case study on securing a Single-tracked Line Segment (SLS) in Moby/plc. The case study is a topic within the UniForMproject and deals with the correct control of a single-tracked railway line by distributed PLCs. The right window of Fig. 1 contains the description of the system network and the left window gives the behavioural description of one component in terms of a PLC-Automaton. For further informations about the case study see [5]. 3 The Moby/plc-Tool An overview of the main components which are currently implemented in the Moby/plc-tool is given in Fig. 2. The central part of the tool is an interactive graphical editor for specifying a real-time system (i). Since the architectural part as well as the behavioural part of a specication may be structured hierarchically the editor comprises several dierent subeditors, e.g. system editors to describe

3 Fig. 1. SLS case study in Moby/plc the network of PLC-Automata or editors to specify automata and subautomata (see Fig. 1). In Moby/plc there are three ways to validate a given specication (ii, iii, iv). A simulator (ii) is able to execute a single or a set of PLC-Automata and to visualize its results directly in the graphical specication. The simulator is designed to support the interactive simulation of small modules as well as extensive tests of the whole specication in background mode [9]. Special analysis algorithms (iii) which are based on the Duration Calculus semantics of PLC-Automata can be used to statically calculate certain properties of an automaton, e.g. its reaction time on a given combination of inputs. The Timed Automata semantics denes how to compile a PLC-Automaton into a Timed Automaton. In order to use existing model checking systems for Timed Automata, we have currently implemented two compilers (iv) into the format of the Kronos tool [4] and of Uppaal [2]. The second compiler exploits the fact that Uppaal is able to handle automata extended by variables. Furthermore, a given specication can be translated automatically by a structural compilation into a special programming language for PLCs called ST (Structured Text)(v). By the use of commercial compilers the ST-code can be transformed into runnable source code for PLCs.

4 Analysis (iii) Algorithms Graphical Editor (i) (ii) Simulator Model Checking Compiler (iv) Visualisation Code-Generation (v) ST-Code PLC-Code Fig. 2. Components of Moby/plc 4 Conclusion In this paper we have sketched the modelling language and the features of the design tool Moby/plc. Although Moby/plc is already usable there are several extensions we are planning to implement. E.g. we want to evaluate and visualize the results of background runs of the simulator. In this context we need a formal description of the environment of a system. This can e.g. be achieved by a non-deterministic variant of PLC-Automata. Furthermore, it seems to be promising to expand the static analysis by further algorithms which calculate interesting properties based on the structure of a PLC-Automaton. Currently a graphical editor for Object-Z specications is developed. This editor should be integrated into Moby/plc in order to use Object-Z for the description of data aspects in PLC-Automata. Acknowledgements. The authors thank H. Fleischhack, E.-R. Olderog, and the other members of the \semantics group" in Oldenburg for fruitful discussions on the subject of this paper. References 1. R. Alur and D.L. Dill. A theory of timed automata. Theoretical Computer Science, 126:183{235, J. Bengtsson, K.G. Larsen, F. Larsson, P. Pettersson, and Wang Yi. Uppaal { a Tool Suite for Automatic Verication of Real-Time Systems. In Hybrid Systems III, volume 1066 of LNCS, pages 232{243. Springer Verlag, Zhou Chaochen, C.A.R. Hoare, and A.P. Ravn. A Calculus of Durations. Inform. Proc. Letters, 40/5:269{276, C. Daws, A. Olivero, S. Tripakis, and S. Yovine. The tool Kronos. In Hybrid Systems III, volume 1066 of LNCS, pages 208{219. Springer Verlag, H. Dierks and J. Tapken. Tool-Supported Hierarchical Design of Distributed Real- Time Systems. In Euromicro Workshop on Real Time Systems, pages 222{229. IEEE, Henning Dierks. PLC-Automata: A New Class of Implementable Real-Time Automata. In ARTS'97, LNCS. Springer Verlag, May 1997.

5 7. Henning Dierks, Ansgar Fehnker, Angelika Mader, and Frits Vaandrager. Operational and Logical Semantics for Polling Real-Time Systems. In FTRTFT'98, LNCS. Springer Verlag, September B. Krieg-Bruckner, J. Peleska, E.-R. Olderog, et al. UniForM Universal Formal Methods Workbench. In Statusseminar des BMBF Softwaretechnologie, pages 357{ 378. BMBF, Berlin, Josef Tapken. Interactive and Compilative Simulation of PLC-Automata. In W. Hahn and A. Lehmann, editors, Simulation in Industry, ESS'97, pages 552 { 556. SCS, 1997.

Ν 1. Τ 5 Error X. Error

Ν 1. Τ 5 Error X. Error PLC-Automata: A New Class of Implementable Real-Time Automata? Henning Dierks?? University of Oldenburg, Germany Abstract. We introduce a new class of automata which are tailored for dealing with real-time

More information

Implementing Hierarchical Graph-Structures

Implementing Hierarchical Graph-Structures Implementing Hierarchical Graph-Structures Josef Tapken Faculty of Computer Science, University of Oldenburg P.O.Box 2503, 26111 Oldenburg, Germany Fax: +49 441 798-2965 tapken@informatik.uni-oldenburg.de

More information

The Moby/plc Tutorial. Henning Dierks, Hans Fleischhack, Josef Tapken. CvO-Universitat Oldenburg. 16th February 2001.

The Moby/plc Tutorial. Henning Dierks, Hans Fleischhack, Josef Tapken. CvO-Universitat Oldenburg. 16th February 2001. The Moby/plc Tutorial Henning Dierks, Hans Fleischhack, Josef Tapken CvO-Universitat Oldenburg 16th February 2001 Contents 1 Introduction 1 1.1 PLC-Automata............................ 1 1.2 Moby/plc..............................

More information

Proc. XVIII Conf. Latinoamericana de Informatica, PANEL'92, pages , August Timed automata have been proposed in [1, 8] to model nite-s

Proc. XVIII Conf. Latinoamericana de Informatica, PANEL'92, pages , August Timed automata have been proposed in [1, 8] to model nite-s Proc. XVIII Conf. Latinoamericana de Informatica, PANEL'92, pages 1243 1250, August 1992 1 Compiling Timed Algebras into Timed Automata Sergio Yovine VERIMAG Centre Equation, 2 Ave de Vignate, 38610 Gieres,

More information

Modeling a Production Cell as a Distributed Real-Time System with Cottbus Timed Automata

Modeling a Production Cell as a Distributed Real-Time System with Cottbus Timed Automata Modeling a Production Cell as a Distributed Real-Time System with Cottbus Timed Automata Dirk Beyer and Heinrich Rust? Lehrstuhl für Software Systemtechnik, BTU Cottbus Abstract. We build on work in designing

More information

Verifying Periodic Task-Control Systems. Vlad Rusu? Abstract. This paper deals with the automated verication of a class

Verifying Periodic Task-Control Systems. Vlad Rusu? Abstract. This paper deals with the automated verication of a class Verifying Periodic Task-Control Systems Vlad Rusu? Abstract. This paper deals with the automated verication of a class of task-control systems with periods, durations, and scheduling specications. Such

More information

COMP 763. Eugene Syriani. Ph.D. Student in the Modelling, Simulation and Design Lab School of Computer Science. McGill University

COMP 763. Eugene Syriani. Ph.D. Student in the Modelling, Simulation and Design Lab School of Computer Science. McGill University Eugene Syriani Ph.D. Student in the Modelling, Simulation and Design Lab School of Computer Science McGill University 1 OVERVIEW In the context In Theory: Timed Automata The language: Definitions and Semantics

More information

TIMES A Tool for Modelling and Implementation of Embedded Systems

TIMES A Tool for Modelling and Implementation of Embedded Systems TIMES A Tool for Modelling and Implementation of Embedded Systems Tobias Amnell, Elena Fersman, Leonid Mokrushin, Paul Pettersson, and Wang Yi Uppsala University, Sweden. {tobiasa,elenaf,leom,paupet,yi}@docs.uu.se.

More information

MODEL-BASED DESIGN OF CODE FOR PLC CONTROLLERS

MODEL-BASED DESIGN OF CODE FOR PLC CONTROLLERS Krzysztof Sacha Warsaw University of Technology, Nowowiejska 15/19, 00-665 Warszawa, Poland k.sacha@ia.pw.edu.pl Keywords: Abstract: Automatic program generation, Model verification, Finite state machine,

More information

A Test Case Generation Algorithm for Real-Time Systems

A Test Case Generation Algorithm for Real-Time Systems A Test Case Generation Algorithm for Real-Time Systems Anders Hessel and Paul Pettersson Department of Information Technology Uppsala University, P.O. Box 337 SE-751 05 Uppsala, Sweden {hessel,paupet}@it.uu.se

More information

Towards Promela verification using VerICS

Towards Promela verification using VerICS Part 2: Specification Towards Promela verification using VerICS Wojciech Nabia lek 1 and Pawe l Janowski 2 1 Institute of Computer Science, University of Podlasie ul. Sienkiewicza 51, 08-110 Siedlce, Poland

More information

erics: A Tool for Verifying Timed Automata and Estelle Specifications

erics: A Tool for Verifying Timed Automata and Estelle Specifications erics: A Tool for Verifying Timed Automata and Estelle Specifications Piotr Dembiński, Agata Janowska, Pawe l Janowski, Wojciech Penczek,5, Agata Pó lrola, Maciej Szreter,Bożena Woźna 4, and Andrzej Zbrzezny

More information

Editor. Analyser XML. Scheduler. generator. Code Generator Code. Scheduler. Analyser. Simulator. Controller Synthesizer.

Editor. Analyser XML. Scheduler. generator. Code Generator Code. Scheduler. Analyser. Simulator. Controller Synthesizer. TIMES - A Tool for Modelling and Implementation of Embedded Systems Tobias Amnell, Elena Fersman, Leonid Mokrushin, Paul Pettersson, and Wang Yi? Uppsala University, Sweden Abstract. Times is a new modelling,

More information

Specification and Analysis of Real-Time Systems Using Real-Time Maude

Specification and Analysis of Real-Time Systems Using Real-Time Maude Specification and Analysis of Real-Time Systems Using Real-Time Maude Peter Csaba Ölveczky1,2 and José Meseguer 1 1 Department of Computer Science, University of Illinois at Urbana-Champaign 2 Department

More information

Abstract formula. Net formula

Abstract formula. Net formula { PEP { More than a Petri Net Tool ABSTRACT Bernd Grahlmann and Eike Best The PEP system (Programming Environment based on Petri Nets) supports the most important tasks of a good net tool, including HL

More information

input interface memory

input interface memory Compact Timed Automata for PLC Programs H.X. Willems University of Nijmegen Computing Science Institute P.O.Box 9010 6500 GL Nijmegen, The Netherlands November 24, 1999 Abstract In this work a set of tools

More information

Timing Analysis of Distributed End-to-End Task Graphs with Model-Checking

Timing Analysis of Distributed End-to-End Task Graphs with Model-Checking Timing Analysis of Distributed End-to-End Task Graphs with Model-Checking Zonghua Gu Department of Computer Science, Hong Kong University of Science and Technology Abstract. Real-time embedded systems

More information

UPPAAL. Validation and Verication of Real Time Systems. Status & Developments y. Abstract

UPPAAL. Validation and Verication of Real Time Systems. Status & Developments y. Abstract UPPAAL Validation and Verication of Real Time Systems Status & Developments y Kim G Larsen z Paul Pettersson x Wang Yi x Abstract Uppaal is a tool box for validation (via graphical simulation) and verication

More information

Rapid Prototyping with APICES

Rapid Prototyping with APICES Rapid Prototyping with APICES Ansgar Bredenfeld GMD Institute for System Design Technology D-53754 Sankt Augustin, Germany bredenfeld@gmd.de http://set.gmd.de/apices APICES is a tool for very rapid development

More information

Verification of Java programs using networks of finite automata with discrete data.

Verification of Java programs using networks of finite automata with discrete data. Catholic University in Ružomberok Scientific Issues, Mathematica II, Ružomberok 2009 Verification of Java programs using networks of finite automata with discrete data. Bożena Woźna, Andrzej Zbrzezny Institute

More information

Timed Automata with Asynchronous Processes: Schedulability and Decidability

Timed Automata with Asynchronous Processes: Schedulability and Decidability Timed Automata with Asynchronous Processes: Schedulability and Decidability Elena Fersman, Paul Pettersson and Wang Yi Uppsala University, Sweden Abstract. In this paper, we exend timed automata with asynchronous

More information

A Boolean Expression. Reachability Analysis or Bisimulation. Equation Solver. Boolean. equations.

A Boolean Expression. Reachability Analysis or Bisimulation. Equation Solver. Boolean. equations. A Framework for Embedded Real-time System Design? Jin-Young Choi 1, Hee-Hwan Kwak 2, and Insup Lee 2 1 Department of Computer Science and Engineering, Korea Univerity choi@formal.korea.ac.kr 2 Department

More information

hal , version 1-9 Apr 2009

hal , version 1-9 Apr 2009 Author manuscript, published in "Computer Aided Verification 10th International Conference, CAV'98, Vancouver, BC : Canada (1998)" DOI : 10.1007/BFb0028779 Kronos: a model-checking tool for real-time systems?

More information

A Real-Time Animator for Hybrid Systems

A Real-Time Animator for Hybrid Systems A Real-Time Animator for Hybrid Systems Tobias Amnell, Alexandre David Wang Yi Department of Computer Systems, Uppsala University {adavid, tobiasa, yi} @docsuuse Abstract In this paper, we present a real

More information

An Introduction to UPPAAL. Purandar Bhaduri Dept. of CSE IIT Guwahati

An Introduction to UPPAAL. Purandar Bhaduri Dept. of CSE IIT Guwahati An Introduction to UPPAAL Purandar Bhaduri Dept. of CSE IIT Guwahati Email: pbhaduri@iitg.ernet.in OUTLINE Introduction Timed Automata UPPAAL Example: Train Gate Example: Task Scheduling Introduction UPPAAL:

More information

2 after reception of a message from the sender, do one of two things: either the message is delivered to the receiver, or it is lost. The loss of a me

2 after reception of a message from the sender, do one of two things: either the message is delivered to the receiver, or it is lost. The loss of a me Protocol Verification using UPPAAL: Exercises? Lab assistant: Alexandre David Department of Computer Systems (room 1237, mailbox 26), Uppsala University, Box 325, S751 05, Uppsala. Phone: 018-18 73 41.

More information

An MTBDD-based Implementation of Forward Reachability for Probabilistic Timed Automata

An MTBDD-based Implementation of Forward Reachability for Probabilistic Timed Automata An MTBDD-based Implementation of Forward Reachability for Probabilistic Timed Automata Fuzhi Wang and Marta Kwiatkowska School of Computer Science, University of Birmingham, Birmingham B15 2TT, United

More information

(b) extended UML state machine diagram. (a) UML state machine diagram. tr D2 tr D1 D2 D1 D2

(b) extended UML state machine diagram. (a) UML state machine diagram. tr D2 tr D1 D2 D1 D2 A Semantic Model for the State Machine in the Unied Modeling Language Kevin Compton 1, James Huggins 3, and Wuwei Shen 1? 1 EECS Department, University of Michigan 1301 Beal Avenue, Ann Arbor, MI 48109-2122

More information

User Interface Modelling Based on the Graph Transformations of Conceptual Data Model

User Interface Modelling Based on the Graph Transformations of Conceptual Data Model User Interface Modelling Based on the Graph Transformations of Conceptual Data Model Martin Molhanec Department of e-technology, Faculty of Electrical Engineering Czech Technical University in Prague Technická

More information

Applied Formal Methods - From CSP to Executable Hybrid Specifications

Applied Formal Methods - From CSP to Executable Hybrid Specifications Applied Formal Methods - From CSP to Executable Hybrid Specifications Jan Peleska Technologie-Zentrum Informatik TZI, Universität Bremen and Verified Systems International GmbH, jp@verified.de Overview

More information

Developing Uppaal over 15 Years

Developing Uppaal over 15 Years Developing Uppaal over 15 Years Gerd Behrmann 1, Alexandre David 2, Kim Guldstrand Larsen 2, Paul Pettersson 3, and Wang Yi 4 1 NORDUnet A/S, Copenhagen, Denmark 2 Department of Computer Science, Aalborg

More information

Dynamic Logic David Harel, The Weizmann Institute Dexter Kozen, Cornell University Jerzy Tiuryn, University of Warsaw The MIT Press, Cambridge, Massac

Dynamic Logic David Harel, The Weizmann Institute Dexter Kozen, Cornell University Jerzy Tiuryn, University of Warsaw The MIT Press, Cambridge, Massac Dynamic Logic David Harel, The Weizmann Institute Dexter Kozen, Cornell University Jerzy Tiuryn, University of Warsaw The MIT Press, Cambridge, Massachusetts, 2000 Among the many approaches to formal reasoning

More information

Graphical Tool For SC Automata.

Graphical Tool For SC Automata. Graphical Tool For SC Automata. Honours Project: 2000 Dr. Padmanabhan Krishnan 1 Luke Haslett 1 Supervisor Abstract SC automata are a variation of timed automata which are closed under complementation.

More information

Design Process Ontology Approach Proposal

Design Process Ontology Approach Proposal Design Process Ontology Approach Proposal Grzegorz J. Nalepa 1 and Weronika T. Furma«ska 1 Institute of Automatics, AGH University of Science and Technology, Al. Mickiewicza 30, 30-059 Kraków, Poland gjn@agh.edu.pl,

More information

A Modelling and Analysis Environment for LARES

A Modelling and Analysis Environment for LARES A Modelling and Analysis Environment for LARES Alexander Gouberman, Martin Riedl, Johann Schuster, and Markus Siegle Institut für Technische Informatik, Universität der Bundeswehr München, {firstname.lastname@unibw.de

More information

Combining Real-Time Model-Checking and Fault Tree Analysis

Combining Real-Time Model-Checking and Fault Tree Analysis Combining Real-Time and Fault Tree Analysis Andreas Schäfer MC University of Oldenburg Real-Time and Fault Tree Analysis p.1/17 Contents What is Fault Tree Analysis (FTA)? Duration Calculus with Liveness

More information

Modelling, Specification and Verification of an Emergency Closing System

Modelling, Specification and Verification of an Emergency Closing System From: FLAIRS-00 Proceedings. Copyright 2000, AAAI (www.aaai.org). All rights reserved. Modelling, Specification and Verification of an Emergency Closing System Werner Stephan and Georg Rock and Michael

More information

High-level Modeling with THORNs. Oldenburger Forschungs- und Entwicklungsinstitut fur. Informatik-Werkzeuge- und Systeme (Offis)

High-level Modeling with THORNs. Oldenburger Forschungs- und Entwicklungsinstitut fur. Informatik-Werkzeuge- und Systeme (Offis) High-level Modeling with THORNs Stefan Schof, Michael Sonnenschein, Ralf Wieting Oldenburger Forschungs- und Entwicklungsinstitut fur Informatik-Werkzeuge- und Systeme (Offis) Escherweg 2 D{26121 Oldenburg

More information

Extending Synchronous Languages for Generating Abstract Real-Time Models

Extending Synchronous Languages for Generating Abstract Real-Time Models Extending Synchronous Languages for Generating Abstract Real-Time Models G. Logothetis and K. Schneider University of Karlsruhe Institute for Computer Design and Fault Tolerance (Prof. Dr.-Ing. D. Schmid)

More information

THE REPRESENTATION OF PEARL TASKS AS TIMED STATE TRANSITION DIAGRAMS. Roman Gumzej, Matjaž Colnari

THE REPRESENTATION OF PEARL TASKS AS TIMED STATE TRANSITION DIAGRAMS. Roman Gumzej, Matjaž Colnari THE REPRESENTATION OF PEARL TASKS AS TIMED STATE TRANSITION DIAGRAMS Roman Gumzej, Matjaž Colnari University of Maribor Faculty of Electrical Eng. and Comp. Sci. Smetanova 17, 2000 Maribor, Slovenia tel.:

More information

An Analysis Tool for UML Models with SPT Annotations

An Analysis Tool for UML Models with SPT Annotations An Analysis Tool for UML Models with SPT Annotations John Håkansson, Leonid Mokrushin, Paul Pettersson, and Wang Yi Uppsala University Department of Information Technology P.O. Box 337, SE-75 05 Uppsala,

More information

Verification of a timed multitask system with UPPAAL

Verification of a timed multitask system with UPPAAL Verification of a timed multitask system with UPPAAL Houda Bel Mokadem, Béatrice Berard, Vincent Gourcuff, Jean-Marc Roussel, Olivier De Smet To cite this version: Houda Bel Mokadem, Béatrice Berard, Vincent

More information

RT-Studio: A tool for modular design and analysis of realtime systems using Interpreted Time Petri Nets

RT-Studio: A tool for modular design and analysis of realtime systems using Interpreted Time Petri Nets RT-Studio: A tool for modular design and analysis of realtime systems using Interpreted Time Petri Nets Rachid Hadjidj and Hanifa Boucheneb Abstract. RT-Studio (Real Time Studio) is an integrated environment

More information

Automated Test Generation using Model-Checking: An Industrial Evaluation

Automated Test Generation using Model-Checking: An Industrial Evaluation Automated Test Generation using Model-Checking: An Industrial Evaluation Eduard P. Enoiu 1, Adnan Čaušević 1, Thomas J. Ostrand 3, Elaine J. Weyuker 1, Daniel Sundmark 12, and Paul Pettersson 1 1 Mälardalen

More information

PLC-Automaton Composition

PLC-Automaton Composition PLC-Automaton Composition Honours Project: 1999 Andre Renaud Dr. Padmanabhan Krishnan 1 1 Supervisor Abstract Based on a discussion of timed automata and a subset of these called PLC automata, described

More information

capture cumulative changes over an interval, while in the HIOA model, the evolution of the continuous state variables over time is modeled using traje

capture cumulative changes over an interval, while in the HIOA model, the evolution of the continuous state variables over time is modeled using traje Developing Strategies for Specialized Theorem Proving about Untimed, Timed, and Hybrid I/O Automata? Sayan Mitra 1 and Myla Archer 2 1 MIT Laboratory for Computer Science, 200 Technology Square, Cambridge,

More information

A Framework-Solution for the. based on Graphical Integration-Schema. W. John, D. Portner

A Framework-Solution for the. based on Graphical Integration-Schema. W. John, D. Portner A Framework-Solution for the EMC-Analysis-Domain based on Graphical Integration-Schema W. John, D. Portner Cadlab - Analoge Systemtechnik, Bahnhofstrasse 32, D-4790 Paderborn, Germany 1 Introduction Especially

More information

[BGH+97] R. Breu, R. Grosu, F. Huber, B. Rumpe, W. Schwerin. Towards a Precise Semantics for Object-Oriented Modeling Techniques. In: Object-Oriented

[BGH+97] R. Breu, R. Grosu, F. Huber, B. Rumpe, W. Schwerin. Towards a Precise Semantics for Object-Oriented Modeling Techniques. In: Object-Oriented Towards a Precise Semantics for Object-Oriented Modeling Techniques? Ruth Breu, Radu Grosu, Franz Huber, Bernhard Rumpe, Wolfgang Schwerin Institut fur Informatik Technische Universitat Munchen email:

More information

A Global Algorithm for Model-Based Test Suite Generation

A Global Algorithm for Model-Based Test Suite Generation A Global Algorithm for Model-Based Test Suite Generation Anders Hessel 1 and Paul Pettersson 1,2 1 Department of Information Technology, Uppsala University, P.O. Box 337, SE-751 05 Uppsala, Sweden. E-mail:

More information

Modeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal

Modeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal Modeling and Verification of Priority Assignment in Real-Time Databases Using Uppaal Martin Kot Martin Kot Center for Applied Cybernetics, Department of Computer Science, FEI, Center for Applied VSBCybernetics,

More information

Rance Cleaveland The Concurrency Factory is an integrated toolset for specication, simulation,

Rance Cleaveland The Concurrency Factory is an integrated toolset for specication, simulation, The Concurrency Factory Software Development Environment Rance Cleaveland (rance@csc.ncsu.edu) Philip M. Lewis (pml@cs.sunysb.edu) y Scott A. Smolka (sas@cs.sunysb.edu) y Oleg Sokolsky (oleg@ccc.com) y

More information

Reasoning about Timed Systems Using Boolean Methods

Reasoning about Timed Systems Using Boolean Methods Reasoning about Timed Systems Using Boolean Methods Sanjit A. Seshia EECS, UC Berkeley Joint work with Randal E. Bryant (CMU) Kenneth S. Stevens (Intel, now U. Utah) Timed System A system whose correctness

More information

Utilizing Static Analysis for Programmable Logic Controllers

Utilizing Static Analysis for Programmable Logic Controllers Sébastien Bornot Ralf Huuck Ben Lukoschus Lehrstuhl für Softwaretechnologie Universität Kiel Preußerstraße 1 9, D-24105 Kiel, Germany seb rhu bls @informatik.uni-kiel.de Yassine Lakhnech Verimag Centre

More information

want turn==me wait req2==0

want turn==me wait req2==0 Uppaal2k: Small Tutorial Λ 16 October 2002 1 Introduction This document is intended to be used by new comers to Uppaal and verification. Students or engineers with little background in formal methods should

More information

Modelling and Formal Verification of Timing Aspects in Large PLC Programs

Modelling and Formal Verification of Timing Aspects in Large PLC Programs NOTICE: this is the author s version of a work that was accepted for publication on The 9th World Congress of the International Federation of Automatic Control. Changes resulting from the publishing process,

More information

Reconciling Dierent Semantics for Concept Denition (Extended Abstract) Giuseppe De Giacomo Dipartimento di Informatica e Sistemistica Universita di Ro

Reconciling Dierent Semantics for Concept Denition (Extended Abstract) Giuseppe De Giacomo Dipartimento di Informatica e Sistemistica Universita di Ro Reconciling Dierent Semantics for Concept Denition (Extended Abstract) Giuseppe De Giacomo Dipartimento di Informatica e Sistemistica Universita di Roma \La Sapienza" Via Salaria 113, 00198 Roma, Italia

More information

SCHEDULING LACQUER PRODUCTION BY REACHABILITY ANALYSIS - A CASE STUDY 1

SCHEDULING LACQUER PRODUCTION BY REACHABILITY ANALYSIS - A CASE STUDY 1 SCHEDULING LACQUER PRODUCTION BY REACHABILITY ANALYSIS - A CASE STUDY 1 Gerd Behrmann Ed Brinksma Martijn Hendriks Angelika Mader Aalborg University, Denmark University of Twente, The Netherlands University

More information

Modelling and Analysis of a Collision Avoidance Protocol. Using SPIN and UPPAAL. Henrik Ejersbo Jensen, Kim G. Larsen, and Arne Skou

Modelling and Analysis of a Collision Avoidance Protocol. Using SPIN and UPPAAL. Henrik Ejersbo Jensen, Kim G. Larsen, and Arne Skou DIMACS Series in Discrete Mathematics and Theoretical Computer Science Volume 00, 19xx Modelling and Analysis of a Collision Avoidance Protocol Using SPIN and UPPAAL Henrik Ejersbo Jensen, Kim G. Larsen,

More information

EL6483: Basic Concepts of Embedded System ModelingSpring and Hardware-In-The-Loo

EL6483: Basic Concepts of Embedded System ModelingSpring and Hardware-In-The-Loo : Basic Concepts of Embedded System Modeling and Hardware-In-The-Loop Simulation Spring 2016 : Basic Concepts of Embedded System ModelingSpring and Hardware-In-The-Loo 2016 1 / 26 Overall system : Basic

More information

MANY real-time applications need to store some data

MANY real-time applications need to store some data Proceedings of the International Multiconference on Computer Science and Information Technology pp. 673 678 ISBN 978-83-60810-14-9 ISSN 1896-7094 Modeling Real-Time Database Concurrency Control Protocol

More information

Efficient representation for formal verification of PLC programs *

Efficient representation for formal verification of PLC programs * Efficient representation for formal verification of PLC programs * Vincent Gourcuff, Olivier De Smet and Jean-Marc Faure LURPA ENS de Cachan, 61 avenue du Prés. Wilson, F-94235 Cachan Cedex, France Email:

More information

Timed Automata From Theory to Implementation

Timed Automata From Theory to Implementation Timed Automata From Theory to Implementation Patricia Bouyer LSV CNRS & ENS de Cachan France Chennai january 2003 Timed Automata From Theory to Implementation p.1 Roadmap Timed automata, decidability issues

More information

Practical Model-based Testing With Papyrus and RT-Tester

Practical Model-based Testing With Papyrus and RT-Tester Practical Model-based Testing With Papyrus and RT-Tester Jan Peleska and Wen-ling Huang University of Bremen Verified Systems International GmbH Fourth Halmstad Summer School on Testing, 2014-06-11 Acknowledgements.

More information

AN ABSTRACTION TECHNIQUE FOR REAL-TIME VERIFICATION

AN ABSTRACTION TECHNIQUE FOR REAL-TIME VERIFICATION AN ABSTRACTION TECHNIQUE FOR REAL-TIME VERIFICATION Edmund M. Clarke, Flavio Lerda, Muralidhar Talupur Computer Science Department Carnegie Mellon University Pittsburgh, PA 15213 {flerda,tmurali,emc}@cs.cmu.edu

More information

DISCRETE-event dynamic systems (DEDS) are dynamic

DISCRETE-event dynamic systems (DEDS) are dynamic IEEE TRANSACTIONS ON CONTROL SYSTEMS TECHNOLOGY, VOL. 7, NO. 2, MARCH 1999 175 The Supervised Control of Discrete-Event Dynamic Systems François Charbonnier, Hassane Alla, and René David Abstract The supervisory

More information

User 1 User 2 User 3. Master Slave 1 Slave 2 Slave 3. Ethernet

User 1 User 2 User 3. Master Slave 1 Slave 2 Slave 3. Ethernet Modelling and Analysis of a Collision Avoidance Protocol using SPIN and UPPAAL Henrik Ejersbo Jensen Kim G. Larsen Arne Skou BRICS, Aalborg University, Denmark, E-mail: fejersbo,kgl,askg@iesd.auc.dk. Abstract

More information

TiPEX: A Tool Chain for Timed Property Enforcement During execution

TiPEX: A Tool Chain for Timed Property Enforcement During execution TiPEX: A Tool Chain for Timed Property Enforcement During execution Srinivas Pinisetty, Yliès Falcone, Thierry Jéron, Hervé Marchand To cite this version: Srinivas Pinisetty, Yliès Falcone, Thierry Jéron,

More information

Semantic Processing of Sensor Event Stream by Using External Knowledge Bases

Semantic Processing of Sensor Event Stream by Using External Knowledge Bases Semantic Processing of Sensor Event Stream by Using External Knowledge Bases Short Paper Kia Teymourian and Adrian Paschke Freie Universitaet Berlin, Berlin, Germany {kia, paschke}@inf.fu-berlin.de Abstract.

More information

Program Design in PVS. Eindhoven University of Technology. Abstract. Hoare triples (precondition, program, postcondition) have

Program Design in PVS. Eindhoven University of Technology. Abstract. Hoare triples (precondition, program, postcondition) have Program Design in PVS Jozef Hooman Dept. of Computing Science Eindhoven University of Technology P.O. Box 513, 5600 MB Eindhoven, The Netherlands e-mail: wsinjh@win.tue.nl Abstract. Hoare triples (precondition,

More information

opaal: A Lattice Model Checker

opaal: A Lattice Model Checker opaal: A Lattice Model Checker Andreas Engelbredt Dalsgaard, René Rydhof Hansen, Kenneth Yrke Jørgensen, Kim Gulstrand Larsen, Mads Chr. Olesen, Petur Olsen, and Jiří Srba Department of Computer Science,

More information

Appears in Proc. IEEE Int l Conf. on Robotics and Automation San Francisco, CA April 22-28, 2000

Appears in Proc. IEEE Int l Conf. on Robotics and Automation San Francisco, CA April 22-28, 2000 Appears in Proc. IEEE Int l Conf. on Robotics and Automation San Francisco, CA April 22-28, 2000 Using Model Checking to Guarantee Safety in Automatically-Synthesized Real-Time Controllers David J. Musliner,

More information

Extensions of the algorithm to deal with hybrid systems, controller synthesis and continuous disturbances are described in section 4 along with severa

Extensions of the algorithm to deal with hybrid systems, controller synthesis and continuous disturbances are described in section 4 along with severa Approximate Reachability Analysis of Piecewise-Linear Dynamical Systems? Eugene Asarin 1, Olivier Bournez 2, Thao Dang 1, and Oded Maler 1 1 Verimag, Centre Equation, 2, av. de Vignate, 38610 Gieres, France

More information

13 AutoFocus 3 - A Scientific Tool Prototype for Model-Based Development of Component-Based, Reactive, Distributed Systems

13 AutoFocus 3 - A Scientific Tool Prototype for Model-Based Development of Component-Based, Reactive, Distributed Systems 13 AutoFocus 3 - A Scientific Tool Prototype for Model-Based Development of Component-Based, Reactive, Distributed Systems Florian Hölzl and Martin Feilkas Institut für Informatik Technische Universität

More information

This full text version, available on TeesRep, is the post-print (final version prior to publication) of:

This full text version, available on TeesRep, is the post-print (final version prior to publication) of: This full text version, available on TeesRep, is the post-print (final version prior to publication) of: Dong, J. S. et. al. (2006) 'HighSpec: A tool for building and checking OZTA models', 28th international

More information

Towards Dependable Development Tools for Embedded Systems A Case Study in Software Verification*

Towards Dependable Development Tools for Embedded Systems A Case Study in Software Verification* From: FLAIRS-00 Proceedings. Copyright ' 2000, AAAI (www.aaai.org). All rights reserved. Towards Dependable Development Tools for Embedded Systems A Case Study in Software Verification* Uwe Petermanu Dept.

More information

Pet: An Interactive Software Testing Tool

Pet: An Interactive Software Testing Tool Pet: An Interactive Software Testing Tool Elsa Gunter, Robert Kurshan, and Doron Peled Bell Laboratories 600 Mountain Ave. Murray Hill, NJ 07974 Abstract. We describe here the Pet (standing for path exploration

More information

Managing test suites for services

Managing test suites for services Managing test suites for services Kathrin Kaschner Universität Rostock, Institut für Informatik, 18051 Rostock, Germany kathrin.kaschner@uni-rostock.de Abstract. When developing an existing service further,

More information

The UniForM Workbench, a Universal Development Environment for Formal Methods

The UniForM Workbench, a Universal Development Environment for Formal Methods The UniForM Workbench, a Universal Development Environment for Formal Methods Bernd Krieg-Brückner 1, Jan Peleska 1, Ernst-Rüdiger Olderog 2, Alexander Baer 3 1 Bremen Institute of Safe Systems, University

More information

History: Combinational Logic! single FSM! Hierarchy. Facilities for managing networks of FSMs MISII. Facilities for handling latches

History: Combinational Logic! single FSM! Hierarchy. Facilities for managing networks of FSMs MISII. Facilities for handling latches FSM Introduction History: Combinational Logic! single FSM! Hierarchy of FSM's. Sequential Circuit Optimization (single machine) SIS Facilities for managing networks of FSMs MISII Facilities for handling

More information

Incremental Design and Formal Verification with UML/RT in the FUJABA Real-Time Tool Suite

Incremental Design and Formal Verification with UML/RT in the FUJABA Real-Time Tool Suite Incremental Design and Formal Verification with UML/RT in the FUJABA Real-Time Tool Suite Sven Burmester, Holger Giese, Martin Hirsch, and Daniela Schilling Software Engineering Group, University of Paderborn,

More information

Synchronization Expressions: Characterization Results and. Implementation. Kai Salomaa y Sheng Yu y. Abstract

Synchronization Expressions: Characterization Results and. Implementation. Kai Salomaa y Sheng Yu y. Abstract Synchronization Expressions: Characterization Results and Implementation Kai Salomaa y Sheng Yu y Abstract Synchronization expressions are dened as restricted regular expressions that specify synchronization

More information

arxiv: v3 [cs.fl] 5 Mar 2017

arxiv: v3 [cs.fl] 5 Mar 2017 A novel type of Automata for dynamic, heterogeneous and random architectures arxiv:1702.02240v3 [cs.fl] 5 Mar 2017 Weijun ZHU School of Information Engineering, Zhengzhou University, Zhengzhou, 450001,

More information

CSP-OZ-DC: A COMBINATION OF SPECIFICATION TECHNIQUES FOR PROCESSES, DATA AND TIME

CSP-OZ-DC: A COMBINATION OF SPECIFICATION TECHNIQUES FOR PROCESSES, DATA AND TIME Nordic Journal of Computing 9(2002), 301 334 CSP-OZ-DC: A COMBINATION OF SPECIFICATION TECHNIQUES FOR PROCESSES, DATA AND TIME JOCHEN HOENICKE ERNST-RÜDIGER OLDEROG Department of Computing Science, University

More information

Computing least common subsumers for FLE +

Computing least common subsumers for FLE + Computing least common subsumers for FLE + Sebastian Brandt and Anni-Yasmin Turhan Theoretical Computer Science, TU Dresden, Germany Email: {brandt, turhan}@tcs.inf.tu-dresden.de Abstract Transitive roles

More information

An Online Model-Checking Framework for Timed Automata

An Online Model-Checking Framework for Timed Automata An Online Model-Checking Framework for Timed Automata Applying Formal Verification to Medical Cyber-Physical Systems Vom Promotionsausschuss der Technischen Universität Hamburg-Harburg zur Erlangung des

More information

Towards Validated Real-Time Software

Towards Validated Real-Time Software Towards Validated Real-Time Software Valérie BERTIN, Michel POIZE, Jacques PULOU France Télécom - Centre National d'etudes des Télécommunications 28 chemin du Vieux Chêne - BP 98-38243 Meylan cedex - France

More information

A Hierarchical Approach to Workload. M. Calzarossa 1, G. Haring 2, G. Kotsis 2,A.Merlo 1,D.Tessera 1

A Hierarchical Approach to Workload. M. Calzarossa 1, G. Haring 2, G. Kotsis 2,A.Merlo 1,D.Tessera 1 A Hierarchical Approach to Workload Characterization for Parallel Systems? M. Calzarossa 1, G. Haring 2, G. Kotsis 2,A.Merlo 1,D.Tessera 1 1 Dipartimento di Informatica e Sistemistica, Universita dipavia,

More information

State Identification In The Hybrid Automata Description Of Dynamical Systems

State Identification In The Hybrid Automata Description Of Dynamical Systems State Identification In The Hybrid Automata Description Of Dynamical Systems ISABELLA KOTINI, GEORGE HASSAPIS Dept. of Electrical and Computer Engineering Aristotle University of Thessaloniki 54006, Thessaloniki

More information

A Note on Fairness in I/O Automata. Judi Romijn and Frits Vaandrager CWI. Abstract

A Note on Fairness in I/O Automata. Judi Romijn and Frits Vaandrager CWI. Abstract A Note on Fairness in I/O Automata Judi Romijn and Frits Vaandrager CWI P.O. Box 94079, 1090 GB Amsterdam, The Netherlands judi@cwi.nl, fritsv@cwi.nl Abstract Notions of weak and strong fairness are studied

More information

AGG: A Graph Transformation Environment for Modeling and Validation of Software

AGG: A Graph Transformation Environment for Modeling and Validation of Software AGG: A Graph Transformation Environment for Modeling and Validation of Software Gabriele Taentzer Technische Universität Berlin, Germany gabi@cs.tu-berlin.de Abstract. AGG is a general development environment

More information

MeDoc Information Broker Harnessing the. Information in Literature and Full Text Databases. Dietrich Boles. Markus Dreger y.

MeDoc Information Broker Harnessing the. Information in Literature and Full Text Databases. Dietrich Boles. Markus Dreger y. MeDoc Information Broker Harnessing the Information in Literature and Full Text Databases Dietrich Boles Markus Dreger y Kai Grojohann z June 17, 1996 Introduction. MeDoc is a two-year project sponsored

More information

Real-time Testing with Timed Automata Testers and Coverage Criteria

Real-time Testing with Timed Automata Testers and Coverage Criteria Real-time Testing with Timed Automata Testers and Coverage Criteria Moez Krichen and Stavros Tripakis VERIMAG Centre Equation, 2, avenue de Vignate, 38610 Gières, France. www-verimag.imag.fr. Abstract.

More information

Siegfried Loer and Ahmed Serhrouchni. Abstract. SPIN is a tool to simulate and validate Protocols. PROMELA, its

Siegfried Loer and Ahmed Serhrouchni. Abstract. SPIN is a tool to simulate and validate Protocols. PROMELA, its DIMACS Series in Discrete Mathematics and Theoretical Computer Science Volume 00, 19xx Creating Implementations from PROMELA Models Siegfried Loer and Ahmed Serhrouchni Abstract. SPIN is a tool to simulate

More information

Stochastic Games for Verification of Probabilistic Timed Automata

Stochastic Games for Verification of Probabilistic Timed Automata Stochastic ames for Verification of Probabilistic Timed Automata Marta Kwiatkowska, ethin Norman, and David Parker Oxford University Computing Laboratory, Parks Road, Oxford, OX1 3QD Abstract. Probabilistic

More information

Skill. Robot/ Controller

Skill. Robot/ Controller Skill Acquisition from Human Demonstration Using a Hidden Markov Model G. E. Hovland, P. Sikka and B. J. McCarragher Department of Engineering Faculty of Engineering and Information Technology The Australian

More information

Turn Indicator Model Overview

Turn Indicator Model Overview Turn Indicator Model Overview Jan Peleska 1, Florian Lapschies 1, Helge Löding 2, Peer Smuda 3, Hermann Schmid 3, Elena Vorobev 1, and Cornelia Zahlten 2 1 Department of Mathematics and Computer Science

More information

Dr. Ing. Cornelia Zahlten. Prof. Dr. Jan Peleska. Concepts and Implementation. Hard Real-Time Test Tools

Dr. Ing. Cornelia Zahlten. Prof. Dr. Jan Peleska. Concepts and Implementation. Hard Real-Time Test Tools Hard Real-Time Test Tools Concepts and Implementation Prof. Dr. Jan Peleska Centre for Computing Technologies, University of Bremen, Germany Dr. Ing. Cornelia Zahlten Verified Systems International GmbH,

More information

In this presentation,...

In this presentation,... Hard Real-Time Test Tools Concepts and Implementation Prof. Dr. Jan Peleska Centre for Computing Technologies, University of Bremen, Germany Dr. Ing. Cornelia Zahlten Verified Systems International GmbH,

More information

Kronos: A Model-Checking Tool for Real-Time Systems*

Kronos: A Model-Checking Tool for Real-Time Systems* Kronos: A Model-Checking Tool for Real-Time Systems* Marius Bozga ], Conrado Daws 1, Oded Maler 1, Alfredo Olivero 2, Stavros Tripakis 1 and Sergio Yovine 3 ~ 1 VERIMAG, Centre ]~quation, 2 avenue de Vignate,

More information

Movement PLANNER T1(0,001/100) / TRAJECTORY WORKING IDLE DONE(300)/ - CONTROLLER SHUTDOWN(300)/ -

Movement  PLANNER T1(0,001/100) / TRAJECTORY WORKING IDLE DONE(300)/ - CONTROLLER SHUTDOWN(300)/ - UML-Extensions for Quantitative Analysis? Konstantinos Kosmidis 1 and Huszerl Gabor 2 1 University of Erlangen{Nuremberg, Dept. of Computer Science III Martensstrasse 3, D{91058 Erlangen, Germany kk@cs.fau.de

More information