UMBC. contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. contain displacement added to IP.

Transcription

1 Procedures: CALL: Pushes the address of the instruction following the CALL instruction onto the stack. RET: Pops the address. SUM PROC NEAR USES BX CX DX ADD AX, BX ADD AX, CX MOV AX, DX RET SUM ENDP NEAR CALL: Similar to NEAR jump instruction, e.g. 2nd and 3rd bytes of instruction contain displacement added to IP. FAR CALL: Similar to FAR jump instruction, e.g. 2nd and 3rd bytes of instruction contain new IP while 4th and 5th bytes contain CS. CALL BX and CALL [BX] versions also exist. 1 (March 27, :41 pm)

2 Interrupts: Hardware generated CALL: I/O Device Software generated CALL: Internally derived from an instruction or exception. We will look at both of these. Interrupt Vectors: Real Mode: A 4 byte number stored in the first 1024 bytes of memory. Protected Mode: A interrupt descriptor table is used instead. Each descriptor is 8 bytes long. There are 256 interrupt vectors. Intel reserves the Interrupts are user definable. Vectors 1-6, 7, 9, 16 and 17 function in real and protected mode. The rest function only in protected mode. 2 (March 27, :41 pm)

3 Interrupt Vectors: Number Address Microprocessor Function All Divide error All Single step B All NMI pin 3 0C-0F All Breakpoint All Interrupt on overflow Pentium Bound instruction (print screen) B Pentium Invalid opcode 7 1C-1F Pentium Coprocessor emulation Pentium Double fault (clock tick) Coprocessor segment overrun (keyboard) A 28-2B Pentium Invalid task state segment (IRQ2) B 2C-2F Pentium Segment not present (IRQ3) C Pentium Stack fault (IRQ4) D Pentium General protection fault (IRQ5) E 38-3B Pentium Page fault (IRQ6) F 3C-3F Reserved (IRQ7) Pentium Floating-point error (Video) SX Alignment check interrupt F Pentium Machine check exception 13-1F 50-7F --- Reserved 3 (March 27, :41 pm)

4 Interrupt Instructions. Real mode: Fetches a vector from the vector table (address of ISR). Protected mode: Fetches an interrupt descriptor (contains addr of ISR). Similar to a FAR CALL: pushes both IP/EIP and CS onto stack. 3 types are available: INT There are 256 software interrupt instructions. The INT instruction takes a numeric operand: Real mode: It s multiplied by 4 to get address of vector. Protected mode: It s multiplied by 8 (descriptors are 8 bytes long). 4 (March 27, :41 pm)

5 INT Instruction. Processing sequence for an INT instruction: Push FLAGS. Clear T and I flag bits (hardware interrupts disabled). Push CS. Fetch new value for CS from interrupt vector. Push IP/EIP. Fetches new value of IP/EIP from vector. Jump to new location. INT instruction is 2 bytes long. Replaces FAR CALL, which is 5 bytes long. Commonly used to call system functions. Decouples programs from system function addresses. IRET(Real)/IRETD(Protected): Undoes call: POP IP/EIP, POP CS, POP FLAGS Popping FLAGS restores T and I bits. 5 (March 27, :41 pm)

6 Interrupt Instructions. 2nd type: INTO Interrupt on overflow. Conditional software interrupt that tests the overflow flag (O). If O=0, INTO does nothing. If O=1, the procedure at interrupt vector 4 is called. 3rd type: INT3 Designed to function like a breakpoint to debug software. It is a 1 byte instruction. Form of an ISR: ISR PROC FAR... IRET ;Pops EIP, CS and FLAGS ISR ENDP 6 (March 27, :41 pm)

7 Hardware Interrupt Control. STI: Places a 1 into the I flag, this enables interr upts. CLI: Places a 0 there, disabling interrupts. Miscellaneous Machine Instructions: STC (set carry), CLC (clear carry) and CMC (complement carry) In addition to propagating carry and borrow in multiple-word/double-word addition, these are used to return error conditions in system calls. C = 1: Error occurred. C = 0: No error occurred. HLT Stops instruction execution. Three ways to resume execution: interrupt, hardware reset or DMA operation. Used to synchronize hardware interrupts with system software. 7 (March 27, :41 pm)

8 Miscellaneous Machine Instructions. LOCK Prefi x: Appended to an instruction. Toggle the LOCK pin, disabling external bus masters and other peripherials. ENTER/LEAVE Used with stack frames, which provide a mechanism to pass stack parameters and allocate storage for local variables for procedures. ENTER pushes BP, and loads BP with the uppermost address of stack frame. Stack variables can then be accessed through the BP register. LEAVE restores previous values of BP and SP, e.g. MOV SP BP POP BP 8 (March 27, :41 pm)

9 ENTER/LEAVE: EAX EBX ECX EDX ESP EBP EDI ESI CS DS ES SS F F F C F F F A ENTER 8, 0 1) Push old BP *10H old SP 2) Set BP FFFA 3) Allocate Stack Frame FFF2 + 3FFFC Stack Seg Old BP 3FFFC 3FFFA 3FFF8 3FFF6 3FFF4 3FFF2 9 (March 27, :41 pm)

10 ENTER/LEAVE: ENTER 4, 0 MOV AX, DATA1 MOV [BP-4], AX MOV AX, DATA2 MOV [BP-2], AX CALL SYS MOV AX, [BP-4] MOV RES1, AX MOV AX, [BP-2] MOV RES2, AX LEAVE ;Save parameters on the stack. ;System call that uses stack ;parameters ;Get results... ;Other code continues here. SYS PROC NEAR PUSHA MOV AX, [BP-4] MOV BX, [BP-2] (March 27, :41 pm)