EKT222 Miroprocessor Systems Lab 5

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1 LAB 5: Interrupts Objectives: 1) Ability to define interrupt in 8085 microprocessor 2) Ability to understanding the interrupt structure in the 8085 microprocessor 3) Ability to create programs using the interrupt 4) Ability to execute and demonstrate simple instructions 5) Ability to analyze the 8085 register and memory map conditions Equipments: 1. Computer station with Windows OS and MY simulation program Instruction Sets (Assembly Code) Instruction Sets (Machine Code) Introduction What is an Interrupt? A hardware interrupt is a CPU facility which permits spurious asynchronous events to suspend program execution and instead execute a software module to service the event. The connection to the processor which allows external devices to signal a request for service is called an interrupt pin. The software module that the processor executes in response to an interrupt is called an interrupt service routine (ISR). The interrupt mechanism is such that after completion of the ISR the processor returns to execution of the main program Maskable Interrupt vs Non-maskable Interrupt A non-maskable interrupt will always, if asserted, interrupt the processor. There is no software mechanism to prevent the processor being interrupted by a nonmaskable interrupt. A maskable interrupt, if asserted, will only interrupt the processor if it is enabled ( unmasked ). Maskable interrupts can be enabled ( unmasked ) or disabled ( masked ) by software. Most maskable interrupts automatically become disabled (masked) after an interrupt has occurred. It requires further software commands to re-enable maskable interrupts. 1

2 Interrupt in 8085 Microprocessor The 8085 microprocessor has five (5) interrupt source input. They are TRAP, RST7.5, RST6.5, RST5.5 and INTR. TRAP is non-maskable and the others are maskable. During reset, all the maskable interrupt are disable, so the microprocessor only responds to TRAP. For maskable interrupt to be effective, it s must be enabled under program control. Only three (3) of this interrupt can be used using our 8085 development system: RST7.5, RST6.5 and RST5.5. The RST6.5 and RST5.5 are level sensitive while RST7.5 is rising edge sensitive. When the microprocessor is interrupted by the external device, it will respond to the interruption by completing their current instruction, saving the program counter of the next instruction to be executed onto the stack and then jumping to the following addresses based on the type of interrupt request. These addresses are located in the ROM space. TRAP RST5.5 RST6.5 RST H 002CH 0034H 003CH Table 1 shows the 8085 Interrupt details in term of interrupt pin, direct/vectored, maskable/non-maskable, address ISR and priority based. Table 1: 8085 Interrupt 2

3 Two program steps are required to enable the RST7.5, RST6.5, RST5.5 interrupts: Setting the interrupt masks using SIM instruction Enabling all interrupt using EI instruction The SIM instruction is used to implement the masking process of the 8085 interrupts RST7.5, RST6.5 and RST5.5. Figure 1 shows the instruction interprets the accumulator contents. SOD SOE X R7.5 MSE M7.5 M6.5 M5.5 Figure 1: Instruction interprets SOD Serial Output Data: Bit D7 of Accumulator is latched into the SOD output line and made available to serial peripheral if bit D6 = 1 SOE Serial Output Enable: If this bit = 1, it enables the serial output. To implement serial output, this bit needs to be enabled. X Don t care R7.5 Reset RST7.5: If this bit = 1, RST7.5 flip-flop is reset. This is an additional control to reset RST7.5. MSE Mask Set Enable: If this bit is high, it enables the function of bits D2, D1 and D0. This is a master control over all the interrupt masking bits. If this bit is low, bits D2, D1 and D0 do not have any effect on the masks. M7.5 D2 = 0, RST7.5 is enabled D2=1, RST7.5 is masked or disabled M6.5 D1 = 0, RST6.5 is enabled D1=1, RST6.5 is masked or disabled M5.5 D0 = 0, RST5.5 is enabled D0=1, RST5.5 is masked or disabled Note: SOD and SOE are irrelevant for interrupt setting. For example, the following instruction sequence enables RST6.5 and disables RST7.5 and RST5.5: please refer Figure 1 to make sure right settings. z MVI A, B SIM EI 3

4 Exercises Connect the circuit as shown in Figure 2 and write the following program. Test the program using the 8085 development system by pressing the pushbutton switch connected to RST6.5. Figure 1: Instruction interprets 4

5 Example Programming : ORG 0000H JMP START ORG 0034H JMP ISR6_5 START: LXI SP, 3FF0H MVI A, 80H OUT 83H MVI A, B SIM EI ; B ; b7 mode definition control byte ; b6-b5 00 is for mode 0, basic I/O ; b4 0 Port A as output ; b3 0 Port C upper as output ; b2 0 mode 0 ; b1 0 Port B as output ; b0 0 Port C lower as output ; set data to control register ; set mask B ; b7-b6 00 is for SOD/SOE - not relevant ; b5 0 n/c = no connection ; b4 1 R7.5 is reset ; b3 0 MSE = Mask setting enabled ; b2 1 M7.5 is enabled ; b1 0 M6.5 is masked or disabled ; b0 1 M5.5 is enabled ; Set interrupt masking ; Enable interrupt START: LXI H, TABLE ; Initialize HL reg to the data table MVI B, 10 ; Set reg B as a counter NEXT: MOV A, M ; Copy data from data table OUT 80H ; send data to PortA@80H CALL DELAY ; call delay INX H ; increment table pointer DCR B ; decrement counter JNZ NEXT ; if counter not zero, do next JMP START ; if coounter zero, start all over again ;define data table byte data TABLE: DFB B, B, B, B, B DFB B, B, B, B, B ;continue next pages 5

6 ;delay routine 1 DELAY: MVI D, 5 LOOP1: MVI E, 20 LOOP: DCR E JNZ LOOP DCR D JNZ LOOP1 RET ;delay routine 2 DELAY2: MVI D, 1 LOOP1b: MVI E, 10 LOOPb: DCR E JNZ LOOPb DCR D JNZ LOOP1b RET ; Interrupt Service Routine RST6.5 ISR6_5: PUSH PSW ; store reg AF to stack area PUSH B ; store reg BC to stack area PUSH D ; store reg DE to stack area MVI A, 0 ; inbitialize A reg to 0 MVI B, 15 ; initialize b reg at 15 as counter REPEAT: CMA ; complement the value in A reg OUT 82H ; send data in a reg to Port C@82H CALL DELAY2 ; call delay2 DCR B ; decrement counter B JNZ REPEAT ; do repeat if counter not zero POP D ; retrieve data in stack area to DE reg POP B ; retrieve data in stack area to BC reg POP PSW ; retrieve data in stack area to AF reg EI ; re enable interrupt RET ; return to main program END 6

7 Task 1. Connect another pushbutton switch to the RST5.5 pin. Modify your existing program to make the LED blink 20 times when the pushbutton switch is pressed. 7

Interrupt is a process where an external device can get the attention of the microprocessor. Interrupts can be classified into two types:

8085 INTERRUPTS 1 INTERRUPTS Interrupt is a process where an external device can get the attention of the microprocessor. The process starts from the I/O device The process is asynchronous. Classification