CS 251, Winter 2018, Assignment % of course mark

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1 CS 25, Winter 28, Assignment 4.. 3% of corse mark De Wednesday, arch 7th, 4:3P Lates accepted ntil Thrsday arch 8th, am with a 5% penalty. (6 points) In the diagram below, the mlticycle compter from the corse notes is eecting the instrction 396 lw $2,($6) in the ID state. The ID/EX register bank will be written to at the end of the clock cycle. In the figre below, there are si dark lines, each above one of the lines in the path. Above each dark line write the vale on the line; if the vale on the line can not be determined from the information given, write?. IF/ID ID/EX EX/E E/ 4 reslt Shift left 2 PC ress register register 2 Registers 2 register Zero ALU ALU reslt ress Data 6 Sign etend CONTROL

2 2. (4 points) Describe 3 differences between the lticycle path and the Single Cycle path. In addition to the 3 differences, discss how the individal instrction eection time has changed in the lticycle path. 3. ( points) Consider the following IPS code seqence: lw $, ($2) 4 addi $3, $, -5 8 sb $, $3, $ 2 sw $, ($3) (a) (5 pts) In the diagram below, each row is labeled with an eected instrction. ark all dependencies by drawing straight lines (similar to the figre in the corse notes: Pipelining page or Fig of the tet) between when the reslt is stored in the register file and when it needs to be taken from the register file. Assme that the code is to rn on the pipelined path of Fig. 4.5 of the 5th edition; this path implements neither stalling nor forwarding. For each dependency, label it either as a hazard or as a non-hazard. 2

3 (b) (5 pts) odify the code to remove the hazards by inserting a minimm nmber of NOPs. Line # Code 3

4 4. (6 points) odify the pipelined path provided on the net page to incorporate the jmp instrction as stdied in the Single Cycle path. a) (4 points) the jmp instrction to the pipeline stage where it is most efficient. Yo may add new control lines, mltipleors or additional components as needed. arks will be dedcted for gross inefficiency. Note: the jmp instrction will work eactly as it did in the Single Cycle path. Yo need to generate the jmp target address and allow this to pdate PC as was shown in the Single Cycle path. The following eection shows eamples of instrctions seqences that are possible with jmp. We want to implement the jmp instrction and modify PC with the jmp target address as soon as possible to avoid errant instrctions beginning eection. Yo do not need to implement any flshing. Yo may assme that nwanted instrctions following the jmp or following the branch are flshed. j 35 beq $2, $, -5 beq $2, $, -5 4 add $4, $3, $2 4 add $4, $3, $2 4 add $4, $3, $2 8 sb $6, $7, $8 8 j 35 8 addi $4,$4, -4 2 addi $4, $4, -4 2 addi $4, $4, -4 2 j 35 6 lw $3, ($2) 6 lw $3, ($2) 6 lw $3, ($2) Yo do not need to consider the case where branch is immediately followed by jmp. Yo do need to consider the cases listed above. b) (2 points) State the vale of any new control bits as needed for the jmp instrction added in part(a). Also, state the vale of the new control bits for all other instrctions sing the path. 4

5 PC [2 6] emtoreg ALUOp Branch RegDst ALUSrc [5 ] reslt Registers register 2 register register 2 Sign etend ALU reslt Zero ALU control Shift left 2 Reg em Control ALU [5 ] 6 EX IF/ID PCSrc ID/EX EX/E E/ em ress Data 5ress

6 5. ( points) This qestion refers to the pipelined path withot forwarding, shown below and in Figre 4.5 in the tetbook. Consider the instrctions add $, $3, $5 4 sw $4, 4($8) 8 sb $4, $, $4 2 beq $, $2, 6 Consider the pipeline when the add instrction is in the stage, the 4 sw instrction is in the E stage, the 8 sb instrction is in the EX stage, and the 2 beq instrction is in the ID stage. In the figre below, label all of the control signals (inclding both those coming directly ot of the control nit and those coming ot of the pipeline registers) with their appropriate vales, sing don t cares where appropriate. In this figre, the instrctions have been drawn above the appropriate set of pipeline registers. We have also filled in the soltion for the stage, and given the names of the control signals whose vales yo need to determine for the other three stages. PCSrc beq $,$2,6 sb $4,$,$4 sw $4, 4($8) add $,$3,$5 Control ID/EX EX/E E/ IF/ID EX PC 4 ress register register 2 Registers 2 register Reg Shift left 2 reslt ALUSrc Zero ALU ALU reslt Branch ress em Data emtoreg 6 32 [5 ] Sign etend 6 ALU control em [2 6] [5 ] RegDst ALUOp emtoreg= Branch= em= RegDst= ALUOp= ALUSrc= Reg= em= emtoreg= Branch= em= RegDst= ALUOp= ALUSrc= Reg= em= emtoreg= Reg= Branch= em= em= Reg= emtoreg= 6

7 6. (5 points) This qestion refers to the pipelined path with forwarding in Figre 4.56 of the tetbook and also given in the corse notes. Consider the instrctions add $, $2, $4 4 add $2, $4, $ 8 sb $3, $2, $ Consider the sitation when the add instrction is in the stage, the 4 add instrction is in the E stage, and the 8 sb instrction is in the EX stage. In the figre below, trace back each of the two inpts to the ALU throgh the UXes back to the appropriate set of pipeline registers. (i.e., trace a path from the ALU back to the pipeline registers where the vales are stored). Yo may se bold dark or zigzag lines to clearly indicate yor work. IF/ID Control sb $3,$2,$ add $2,$4,$ add $,$2,$4 ID/EX EX EX/E E/ PC Registers ALU Data IF/ID.RegisterRs IF/ID.RegisterRt IF/ID.RegisterRt IF/ID.RegisterRd Rs Rt Rt Rd Forwarding nit EX/E.RegisterRd E/.RegisterRd 7

8 7. (7 points) This qestion refers to the pipelined path withot forwarding, shown below and in Figre 4.5 in the tetbook. Consider the instrctions add $, $3, $5 4 lw $4, 4($8) 8 beq $, $2, 6 2 sb $4, $, $4 Consider the pipeline when the add instrction is in the stage, the 4 lw instrction is in the E stage, the 8 beq instrction is in the EX stage, and the 2 sb instrction is in the ID stage. In the figre below, state the decimal vales on the nmbered blank lines -7. In this figre, the instrctions have been drawn above the appropriate set of pipeline stages. Note: The blank lines do not refer to control bits. Line #2 refers to read register, line #5 refers to the address going into. All other line nmbers refer to the decimal vale on the line immediately below or beside it. Yo may also assme each register i contains the vale + i. 8

9 8. (3 points) This qestion refers to the pipelined path from the previos qestion on this assignment. State how many bits wide the Intermediate Register ID/EX mst be in order to store all the reqired and control bits. Yo mst show yor work. 9

10 itional eercises for pipeline architectre: Eercise 4-9, 4-, 4-3, 4-4.