AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall
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1 AccelDSP tutorial 2 (Matlab.m to HDL for Xilinx) Ronak Gandhi Syracuse University Fall AccelDSP Getting Started Tutorial Introduction This tutorial exercise will guide you through the process of transforming a MATLAB floatingpoint model into a hardware module that can be implemented in a Xilinx FPGA. The design is a general purpose FIR filter. Installation The AccelDSP Synthesis Tool is designed to work in an integrated flow with MATLAB and downstream RTL synthesis, simulation, and implementation tools. This tutorial takes you step-bystep through this flow. Before you begin, verify that you have the AccelDSP Synthesis Tool installed, MATLAB. An HDL simulator (ISE Simulator or ModelSim SE), RTL synthesis tool like XST or Synplify Pro. Tutorial Exercise 1. Examine the MATLAB Floating-Point Model Your MATLAB design must conform to a minimum set of coding style guidelines. The basic guidelines for the FIR filter. For this tutorial, you can assume that the FIR filter conforms to the guidelines. For a more complete discussion about style requirements, refer the manual 2. Create an AccelDSP Project In this step, you will create/open an AccelDSP project and analyze the Floating Point Model. Invoke the AccelDSP Synthesis Tool by double-clicking on the desktop icon. a. Close the Tip of the Day window, then follow the directions below. b. Click in the Project icon in ISE window c. Click on Create New Project/ Open Existing Project d. Create/Select file from directory by browsing e. Browse to Destination folder where you want to create project
2 3. Set the Target Technology and Tool Options Verify that the target technology and the AccelDSP tool options are set correctly by selecting the pulldown menu Project > Project Options AccelDSP Synthesis supports a wide range of Xilinx devices. Set and/or verify the Project Options shown below: Frequency (MHz): 100 Technology: Spartan3E Device: XC3C500E Package:FG320 Speed Grade: -4 RTL Simulation: <select HDL simulator> RTL Synthesis: XST To save these settings, select the pulldown menu File > Save> Save Project. You can also set this parameter if they appear on the tool bar but make sure to save the changes.
3 4. Verify the Floating-Point Model The AccelDSP Synthesis Tool provides a direct link to MATLAB so you don t have to leave the tool to run a MATLAB simulation. If you have already verified the floating point model, you may skip this step by clicking on the black down-arrowhead next to the icon and selecting the Skip Verify floating point option. a. To verify that your floating point design passes a MATLAB simulation, click on the Verify Floating Point icon, as shown below: b. Examine plot for your design. You will use this as the reference plot for comparing future results. (Avoid closing down the windows). Since you will be comparing this golden plot to a generated fixed-point plot in Step 7, you should set the option called Run Second MATLAB for Fixed-Point as shown below: 5. Analyze the Floating-Point Model The Analyze icon appears in the AccelDSP Flow bar after the Verify Floating Point step is complete (or skipped). a. To analyze the floating-point model, click on the Analyze icon as shown below:
4 During the Analyze step, the MATLAB files are analyzed by AccelDSP and all the files associated with the design are listed in the Project Explorer window as shown below. 6. Generation Fixed point Model a. Click on the Generate Fixed Point icon to generate an equivalent fixed-point design. The fixed-point design tree is displayed in the Project Explorer window as shown below.
5 During the Generate Fixed Point process, the streaming loop and the top-level design function are identified. Default assumptions are made about design objects in your design like variables and loops. For future reference, you can right-click on these objects, select Properties, then examine the properties that are automatically assigned. If need be, you can change the properties before generating the RTL model. Also note that you can view and change the quantization parameters on variables from the Generate Fixed Point Report. 7. Verify the Fixed-Point Model Click on the Verify Fixed Point icon to start the MATLAB verification process. MATLAB is automatically invoked on the fixed-point model. NOTE: It may take a few moments to invoke MATLAB and run the simulation. The fixedpoint plot is displayed when the simulation is finished. Compare your results from the results with results obtained from Step.4 Visually compare the fixed-point plot with the floating-point plot. If you are satisfied with the results, you are ready to proceed to synthesis. If the fixed-point plot deviates too much from the floating-point plot, you may need to adjust the quantizer properties on some design variables, then repeat the verification process. When you are satisfied with the fixed-point verification results, you are ready to generate the RTL design. As shown below, close the MATLAB windows that were opened by the AccelDSP Synthesis Tool. 8. Generate the RTL Design Click the Generate RTL icon in the AccelDSP Flow bar as shown below: The results are summarized in the generated report. You can also expand the VHDL or Verilog folder to view the generated HDL files and the associated Testbench files.
6 9. Verify the RTL Model Click on Verify RTL as shown below. If you have not yet selected an HDL simulator tool, you will be prompted to do so. The AccelDSP Synthesis Tool causes the simulation tool to compile the Testbench and simulate the RTL model. When the simulation is finished, a 'PASSED' message is shown in the transcript window. 10. Synthesize the RTL Model Once you verify the RTL Model, you are ready to transform the model into a gate-level netlist. Assuming that you have an RTL synthesis tool installed, do the following: a. Select the Synthesize RTL icon in the AccelDSP Flow Bar b. If the tool prompts you to select an RTL Synthesis Tool, select your tool from the Project Options dialog box, then click Apply. The RTL synthesis step starts and when finished, a message similar to the following appears in the Tcl Console window: #(I-SYNTH-0002): Synthesis of RTL design for language 'VHDL' using tool 'XST' PASSED As shown below, examine the contents of the newly-created folder for the RTL synthesis tool. You are now ready to finish the design implementation by clicking on Implement which invokes ISE on these files.
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