ECE 313 Computer Organization EXAM 2 November 9, 2001

Transcription

1 ECE 33 Computer Organization EA 2 November 9, 2 This exam is open book and open notes. You have 5 minutes. Credit for problems requiring calculation will be given only if you show your work. Choose and work four of the five problems, and cross out the problem that you choose not to work. Only four problems will be graded even if you do not cross out a problem.. Floating Point Representation 25 Points a) Translate the decimal value 7.75 into single-precision floating point representation and show your answer in the space provided below b) Translate the number shown below in IEEE single-precision floating point format into its decimal equivalent and writes its value in the space provided below Value of number: Page of 6

2 ECE 33 Computer Organization EA 2 November 9, 2 2. Single-Cycle Processor Design 25 Points odify the single-cycle datapath and control to implement the jal (jump and link) instruction that is used for subprogram calls. The register transfer description for this instruction is as follows: Reg[3] <- PC + 4; PC <- (Instruction[25:] << 2) ark the necessary changes to the datapath and control on the diagrams shown below. PC 4 ADDR ADD Instruction RD jmpaddr I[25:] op I[3: Control nit Instruction I 6 WD <<2 Op RN RN2 WN RD Register File RegWrite 28 Control CONCAT op 6 I[3:26] funct 6I[5:] 5 5 RD2 6 E T N D 32 RegDst 32 PC+4[3-28] Src <<2 Operation 3 ADD Zero PCSrc Jump Branch emwrite ADDR Data WD emread RD emtor Instr RegDst Src emtoreg Reg Write Control Table em Read em Write Branch Op Op jr Page 2 of 6

3 ECE 33 Computer Organization EA 2 November 9, 2 3. Single-Cycle Processor Performance 25 Points The timing calculations performed on page 374 of the book assumed that the delay of the control units and multiplexers are negligible. In this problem we will consider the impact on timing of when the delays of the control units are not neglible. Specifically, suppose that in Figure 5.29 on p. 372, the block marked control has a delay and the block marked control has a delay Y. Further assume that The output will be stable 2ns after its control and data inputs are stable A multipliexer output is stable ns after its select and data inputs are stable Calculate the longest path through the single-cycle processor design when: (a) = ns, Y = ns (b) = 2ns, Y = ns 4. ulti-cycle Processor Design 25 Points odify the multi-cycle processor datapath and control to implement the jal (jump and link register) instruction. The register transfer description is the same as in the Problem 2. ark your changes on the attached schematic diagram and state diagram. How many clock cycles are required to execute the jump register instruction? Page 3 of 6

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5 ECE 33 Computer Organization EA 2 November 9, 2 ulticycle Design State Diagram Start Instruction Fetch emread SrcA = IorD = IRWrite SrcB = Op = PCWrite PCSource = Instruction decode / register fetch SrcA = SrcB = Op = (OP = BEQ ) address computation SrcA = SrcB = Op = Branch Execution Completion SrcA = SrcB = Op = SrcA = SrcB = Op = PCWriteCond PCSource = Jump Completion PCWrite PCSource = OP = LW ) emread IorD = access (OP = ( SW ) access 5 7 emwrite IorD = RegDst = RegWrite emtoreg = R-type completion Writeback step RegWrite emtoreg= RegDst = Page 5 of 6

6 ECE 33 Computer Organization EA 2 November 9, 2 4. icroprogrammed Design 25 Points Extend the microprogrammed implementation of the multicycle design discussed in lecture and the book to implement the addi instruction as in Homework Problem 5.5. Show any modifications to the microprogram (e.g., added microinstructions) and dispatch ROs (jump tables) by modifying the tables shown below. Label control SRC SRC2 Register control PCWrite control Sequencing Fetch Add PC 4 Read PC Seq Add PC Extshft Read Dispatch em Add A Extend Dispatch 2 LW2 Read Seq Write DR Fetch SW2 Write Fetch Rformat Func code A B Seq Write Fetch BEQ Subt A B Out-cond Fetch JP Jump address Fetch Dispatch RO Dispatch RO 2 Op Opcode name Value Op Opcode name Value R-format lw jmp sw beq lw sw Page 6 of 6