Reducing the cost of FPGA/ASIC Verification with MATLAB and Simulink

Transcription

1 Reducing the cost of FPGA/ASIC Verification with MATLAB and Simulink Graham Reith Industry Manager Communications, Electronics and Semiconductors MathWorks 2015 The MathWorks, Inc. 1

2 Who are MathWorks? 2

3 Motivation Algorithm development often starts in MATLAB & Simulink Mathematical algorithms, complex logic and state machines MATLAB & Simulink provide a means to Simulate across multiple domains Develop bit-true and cycle-accurate simulations Improve quality of testing early in design process These models are also valuable to implementation and verification activities Reference models for downstream verification s as the source for implementation RTL Why repeat work that has already been done? More effort Increases risk of errors introduced through manual translation 3

4 Agenda -Based Design for FPGA and ASIC Generating HDL Code from MATLAB and Simulink For prototyping and production Verifying HDL Designs with MATLAB and Simulink Co-simulation with HDL simulators FPGA-in-the-Loop verification Verifying HDL Designs outside MATLAB and Simulink Generating code for integration with SystemC/TLM and SystemVerilog/DPI-C 4

5 -Based Design for FPGA and ASIC RESEARCH REQUIREMENTS ALGORITHM DESIGN Environment s Digital s Analog s RF s Timing and Control Logic Algorithms ALGORITHM IMPLEMENTATION C/C++ HDL RF & Analog MCU DSP FPGA ASIC Transistor ALGORITHM TEST & VERIFICATION multi-domain systems Explore and optimize system behavior Collaborate across multidisciplinary teams Generate bit-accurate models Explore and optimize implementation tradeoffs Generate efficient code INTEGRATION Verify designs to detect errors earlier in development Reuse testbenches Automate regression testing 5

6 It s about Collaboration Usually, many engineers get involved in different parts of the design flow: Systems Verification Algorithms Firmware Etc. Each brings valuable expertise from their discipline -Based Design aids collaboration across the project integrating the workflow providing the backbone of a common modelling environment 6

7 Algorithm A Typical Structure Data Source Environment Analysis Algorithmic System-level Testbench Algorithm interacts with outside environment through other components. Algorithm is stimulated with data Algorithm performance is analysed. 7

8 Algorithm Verification at the Level Data Source Environment Analysis Algorithmic System-level Testbench Simulink Verification & Validation Coverage results for tests that have been simulated Interfaces to Requirements Management systems Simulink Design Verifier Generation of tests to deliver coverage Identification of unreachable code Formal proof methods against objectives 8

9 Algorithm Algorithm Development Generation of HDL Source Code Data Source HDL Coder Generation of synthesible RTL HDL (VHDL or Verilog) Analysis Environment Support for MATLAB Simulink Stateflow Algorithmic System-level Testbench RTL HDL (VHDL, Verilog) HDL Coder Workflow Advisor Guides through process Preparing model for generation of HDL Configuring HDL Generation options Integrated with FPGA synthesis tools for timing annotation on model Configurations for turnkey FPGA targets and IP Core generation 9

10 Simulink Library Support for HDL Generation HDL Supported Blocks ~180 blocks supported Core Simulink Basic and Array Arithmetic, Look-Up Tables, Signal Routing (Mux / Demux, Delays, Selectors), Logic & Bit Operations, Dual and single port RAMs, FIFOs, CORDICs, Busses Digital Signal Processing NCOs, FFTs, Digital Filters (FIR, IIR, Multirate, Adaptive, Multi-channel), Rate Changes (Up & Down Sample), Statistics (Min / Max) Communications Pseudo-random Sequence Generators, Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders, Reed Solomon Encoders / Decoders, CRC Generator / Detector 10

11 MATLAB & Stateflow for HDL Generation HDL Supported Blocks MATLAB Relevant subset of the MATLAB language for modeling and generating HDL implementations Useful MATLAB Function Block Design Patterns for HDL Stateflow ing FSMs (Mealy, Moore) Different modeling paradigms (Graphical Methods, State Transition Tables, Truth Tables) Integrate MATLAB code 11

12 Critical Path Highlighting and Design Review Feedback in Simulink Review results in synthesis tools 12

13 Algorithm Algorithm Verification Data-driven Verification of HDL Source Code Data Source Analysis Algorithmic System-level Testbench Environment Stand-alone HDL testbench Stand-alone Executable in any 3 rd -party HDL simulator Self-contained Instantiated algorithmic RTL HDL (DUT) Input stimuli stream at DUT top-level interface Expected output stream at DUT top-level interface Self-testing Checks on bit and cycle accuracy Handwritten or generated code input stimuli RTL HDL (VHDL, Verilog) == With HDL Coder, RTL HDL and standalone testbenches are created automatically expected outputs Stand-alone HDL Testbench 13

14 Algorithm Algorithm Verification Co-simulation for Verification of HDL Source Code Data Source Environment Co-simulation with 3 rd -party HDL simulator Reuse of existing testbench in MATLAB/Simulink Analysis == Co-Sim Algorithmic System-level Testbench HDL code execution in 3 rd -party HDL simulator Flexible HDL sources Handwritten or generated code RTL HDL (VHDL, Verilog) cosimwizard (HDL Verifier), HDL Workflow Advisor (HDL Coder) HDL Verifier Automated generation of co-simulation infrastructure Automatic handshaking Combined analysis and debugging in both simulators 3 rd -party HDL Simulator 14

15 Algorithm Algorithm Verification FPGA-in-the-Loop Verification of HDL Source Code Data Source Environment FIL simulation with FPGA development board Reuse of existing testbench in MATLAB/Simulink Analysis == FIL Algorithmic System-level Testbench filwizard (HDL Verifier), HDL Workflow Advisor (HDL Coder) HDL Verifier HDL code execution on FPGA Flexible HDL sources Handwritten or generated code Automated generation of co-simulation infrastructure Encapsulation of algorithm within GBit Ethernet MAC, or via JTAG Automatic handshaking 15

16 Integrating with other Verification Activities Verification is the single biggest cost in hardware design Investment in developing simulations for verification SystemVerilog and UVM test frameworks SystemC/TLM virtual platforms Shift towards model-based verification Enabling techniques like Constrained Random testing Rather than recreate a behavioural model, we can reuse the assets developed in the system models in MATLAB & Simulink Maintains connection with earlier part of the flow Removes risk of manual error in test framework Avoids duplicating effort 16

17 Algorithm System Verification Reuse of models in SystemVerilog Testbench Data Source Environment Code generation translates models to other languages (e.g. C, HDL) Implementation code Verification models Analysis Algorithmic System-level Testbench For verification, C code generation is convenient analog and digital models Wider block and langauge support for C generation DPI-C DPI-C DPI-C DPI-C SystemVerilog Testbench Environment HDL Verifier Embedded Coder HDL Verifier extends code generation tools to provide wrappers for SystemVerilog DPI-C SystemC TLM 17

18 Example: Generating DPI-C code Configure model as fixed-step discrete Select target file for Embedded Coder: systemverilog_dpi_ert.tlc Generated files: DPI-C wrapper of C version of algorthm Makefile for DPI-C SystemVerilog module definition Testbench to verify generated module against model data C Source and Header files DPI-C wrapper Source and Heade SystemVerilog Testbench Reference IO Data gcc and VC makefiles SystemVerilog Module DO files to Run testbench Testbench 18

19 Summary and Next Steps Improving integration across the complete design flow is delivering significant benefit to companies already. STARC (Japanese semiconductor consortium) reported 50% reduction in project timescale Consider how you are creating your verification models today Does it already exist in MATLAB? Does MATLAB provide a quick way of producing a reference? Consider how closely verification activities are connected to other parts of the design flow How can collaboration be increased? Reuse of test vectors, sharing of code? Improving quality of testing earlier? Contact MathWorks to discuss and review! Graham.Reith@mathworks.co.uk 19