Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim

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1 Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim AN Subscribe Send Feedback

2 Contents Contents Conventions Glossary Introduction Design Configuration and Usage Other Debug/Pipelining Switches Error Vector Design Considerations Document Revision History

3 1 Intel Xeon with FPGA IP Asynchronous Core Cache Interface (CCI-P) Shim 1.1 Conventions 1.2 Glossary This document uses the following conventions: #: Precedes a command that indicates the command is to be entered as root. $: Indicates a command is to be entered as a user. This font: Filenames, commands, and keywords are printed in this font. Long command lines are printed in this font. Although some very long command lines may wrap to the next line, the return is not considered part of the command; do not press enter. <variable_name>: Indicates the placeholder text that appears between the angle brackets is to be replaced with an appropriate value. Do not enter the angle brackets. Table 1. Acronyms Acronyms Expansion Description AFU Accelerator Functional Unit (AFU) Hardware Accelerator implemented in FPGA logic that accelerates or intends to accelerate an application kernel. ASE Intel Accelerator Functional Unit (AFU) Simulation Environment (ASE) The ASE provides a consistent transaction level hardware interface and software API that allows users to develop productionquality AFU RTL and software host applications that can then be run on the real FPGA system without modification. CCI-P Core Cache Interface (CCI-P) CCI-P is the hardware-side signaling interface between the AFU and the FPGA Interface Unit (FIU). 1.3 Introduction The Asynchronous CCI-P Shim is an Intel FPGA Basic Building Blocks that can be used to attach AFU that do not operate at the CCI-P interface clock frequency (pclk) of 400 MHz. It can be considered to be a CCI-P compliant clock-crossing bridge. In this document, the Asynchronous CCI-P shim is be referred to as ccip_async_shim. This BBB package consists of three directories: Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered

4 HW: contains RTL files of ccip_async_shim module. par: contains Synopsys* Design Constraints (SDC) files for place and route. Sample: contains samples on how to use ccip_async_shim in an AFU design. 1.4 Design The ccip_async_shim consists of five asynchronous FIFOs instantiated from the Intel FPGA IP library. Figure 1. Block Diagram Blue Bitstream (Runs at 400 MHz) ccip_async_shim c0tx_afifo AFU Clock Domain (Runs at Arbitrary Clock) CCI-P Interface to/from Blue Bitstream c1tx_afifo c2tx_afifo c0rx_afifo CCI-P Interface to/from AFU Design c1rx_afifo The Dual Clock FIFO component is called dcfifo. The ccip_async_shim module is expected to be used in between a CCI-P interface that operates at 400 MHz (pclk) and an AFU design that operates at some arbitrary frequency (uclk_usr). Table 2. Asynchronous CCI-P Instantiations Instantiation Operation Description C0tx_afifo Read Request Write at uclk_usr asynchronous clock connected to the shim. Read at pclk Carries Read Request (header, valid bit) Back pressure signal (C0TxAlmFull) is connected to c0tx_afifo write count Note: Read Responses for Multi-line requests may generate multiple 1, 2, or 4 responses. C1tx_afifo Write Request Write Fence Request Write at uclk_usr Read at pclk Carries Data, Header bit, and Valid bit. Back pressure signal (C1TxAlmFull) is connected to c1tx_afifo write count C2tx_afifo MMIO Read Response Write at uclk_usr Read at pclk continued... 4

5 Instantiation Operation Description Takes in MMIO Header, valid bit and MMIO read data. No backpressure. C0rx_afifo C1rx_afifo MMIO Write Request MMIO Read Request Read Responses UMsg Write Response Write Fence Response Write at pclk Read at uclk_usr Carries Data, Header bit, and Valid bit. No backpressure. Note: Read responses may be multiline and AFIFO must be deep enough to accommodate for them. Write at pclk Read at uclk_usr Carries Header bit, and Valid bit. No backpressure. 1.5 Configuration and Usage The ccip_async_shim exposes the following switches for sizing purpose: Table 3. Verilog Switches Verilog Switch Description Default C0TX_DEPTH_RADIX C1TX_DEPTH_RADIX C2TX_DEPTH_RADIX Controls depth of c0tx_afifo, 8 (Depth = 256) Depth = 2 C0TX_DEPTH_RADIX Controls depth of c1tx_afifo, 8 (Depth = 256) Depth = 2 C1TX_DEPTH_RADIX Controls depth of c2tx_afifo, 8 (Depth = 256) Depth = C2TX_DEPTH_RADIX C0RX_DEPTH_RADIX C1RX_DEPTH_RADIX Controls depth of c0rx_afifo, Depth = 2 C0RX_DEPTH_RADIX The RX radix must be double than the TX radix. Controls depth of c1rx_afifo, Depth = 2 C1RX_DEPTH_RADIX The RX radix must be double than the TX radix. 10 (Depth = 1024) 10 (Depth = 1024) Note: CCI-P Asynchronous Shim (ccip_async_shim) must be sized appropriately before use. Failure to do so might cause transactions to be dropped. You must analyze the production and consumption behavior of the AFU before sizing the Intel FPGA Basic Building Blocks to requirements. 5

6 1.5.1 Other Debug/Pipelining Switches Error Vector DEBUG_ENABLE: Enables an array of counters that maintain a running tally of incoming and outgoing CCI-P transactions. When in simulation, these counters may be observed in Synopsys/Mentor Graphics* Waveform viewers When running In-System, these counters may be connected to Signal Tap and a running tally can be observed there. ENABLE_EXTRA_PIPELINE: Enables an extra pipeline stage in the read path of the FIFO, potentially allowing for some timing improvement at the expense of adding extra latency. An error vector async_shim_error (five wires long, one each for each Intel FPGA dcfifo) to indicate that the FIFO has been written when full. Note: This vector does not detect all possible error conditions. It cannot be read from software and is readable only through Signal Tap or Simulation Design Considerations If Read Requests are expected to be multi-line, then you must allocate enough depth to c0rx_afifo. This is because each read request can generate 1, 2 or 4 read responses. The default setting for c0rx_afifo is four times c0tx_afifo. Although, you must make appropriate design decisions by analyzing production and consumption rates of the AFU. It is possible to simulate Intel FPGA Basic Building Blocks, as they are considered as components of a green-bitstream in ASE. An assertion warning statement may be generated for some erroneous conditions. When building bitstreams with ccip_async_shim, the Intel Quartus Prime project must include the SDC file available inside the par directory. A sample QSF addition file and import settings are also included as a reference. Also, see the samples supplied along with the Intel FPGA Basic Building Blocks to see how the module can be instantiated and integrated with AFU designs. 1.6 Document Revision History Table 4. Document Revision History Date Version Changes October Initial release. 6

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