CSE 2021 Computer Organization. Hugh Chesser, CSEB 1012U W12-M

Transcription

1 CSE 22 Computer Organization Hugh Chesser, CSEB 2U W2-

2 Graphical Representation Time add $s, $t, $t IF ID E E Decode / Execute emory Back fetch from / stage into the instruction register file. Shading in each block indicates the element is used for in the instruction. Since is not accessed in an add instruction, it is not shaded. 2. Shading on the left half of the block indicates that the element is being written. During instruction fetch, the instruction is read so the right half of IF block is shaded. 3. Shading on the right half of the block indicates that the element is being read. During write back stage, the register file is written so the left half of the block is shaded. W2-2

3 Activity 2 Using the graphical representation, show that the following swap procedure has a pipeline hazard. Reorder the instructions to avoid pipeline stalls. lw $t, ($t) lw $t2, ($t) sw $t2, ($t) sw $t, ($t) lw $t, ($t) lw $t2, ($t) $t loaded $t2 loaded sw $t2, ($t) $t2 stored sw $t, ($t) $t stored W2-3

4 Agenda Topics:. Pipeline path and Control Patterson:.5 W2-

5 Pipelined path () IF/ID ID/E E/E E/ ress Regsiter ress IF: Fetch ID: Decode / file read E: Execute / W2- ress Calculation E: emory Access : back 5

6 Pipelined path (2) In pipelined path, each instruction is broken in five steps: IF ( Fetch), ID ( Decode and register file read), E (Execution or address calculation), E ( emory Access), and ( Back). Each of the above step takes one clock cycle. s and advance forward by from left to right. flows from right to left only in two cases. back stage placing the in the register file 2. Selection of the value for between ( + ) and branch target address s in between different stages store the store values to be used by next stage Name of registers are based on the two pipelined stages that the registers separate Each pipelining register has a different size: IF/ID register is 6 bits wide; ID/E register is 28 bits wide; E/E register is 97 bits wide; and E/ is 6 bits wide There are no pipeline registers at the end of the write-back stage as is written directly into or register file or the. W2-6

7 How pipelining works (): Example lw $s, ($s2) path for Fetch (IF) IF/ID ID/E E/E E/ ress Regsiter ress IF: Fetch W2-7

8 How pipelining works (2): Example lw $s, ($s2) path for Decode and File (ID) IF/ID ID/E E/E E/ ress Regsiter ress ID: Decode / file read W2-8

9 How pipelining works (3): Example lw $s, ($s2) path for Execute / ress Calculation (E) IF/ID ID/E E/E E/ ress Regsiter ress E: Execute / W2- ress Calculation 9

10 How pipelining works (): Example lw $s, ($s2) path for emory Access (E) IF/ID ID/E E/E E/ ress Regsiter ress W2- E: emory Access

11 How pipelining works (5): Example lw $s, ($s2) path for Back () IF/ID ID/E E/E E/ ress Regsiter ress W2- : back

12 How pipelining works (6): Example lw $s, ($s2) Complete path for lw instruction IF/ID ID/E E/E E/ ress Regsiter ress IF: Fetch ID: Decode / file read E: Execute / W2- ress Calculation E: emory Access : back 2

13 ultiple Clock Cycle Pipeline Diagram Time (in clock cycles) Program execution order CC CC 2 CC 3 CC CC 5 CC 6 lw $s, ($s2) I Reg D Reg IF/ID ID/E E/E E/ fetch decode Execution access back Activity 3: Using the graphical representation, show that the multiple clock cycle pipeline diagram of the following two instructions lw $t,($t) sub $s,$s,$s2 W2-3

14 Pipelined Control () Src Control ID/E E/E E/ IF/ID E ress register register 2 s 2 register Reg Src Branch em ress emtoreg [5 ] control em [2 6] [5 ] W2- RegDst Op

15 Pipelined Control (2) Control lines in pipelined implementation is divided into five groups according to the pipeline stage. Fetch: No control needed as the write control of and read control of instruction is always asserted. 2. Decode/ File : No controls needed as the register file in being read during each instruction. 3. Execution/ress Calculation: Control signals are Src, RegDst, and Op. For lw/sw instructions, Src =, RegDst = and Op =. For R-type instructions, Src =, RegDst =, and Op =.. emory Access: Control signals are Branch, em, and em. For lw instruction, em = and Branch = em =. For sw instruction, em = and Branch = em =. For branch instructions, Branch = and emwrite = em =. For R-type instructions, Branch = em = em =. 5. Back: Control signals are emtoreg. For lw instructions, emtoreg =. For R-type instructions, emtoreg =. Pipeline registers are ed to include the control signals for each stage of an instruction. W2-5

16 Activity Show the following instructions going through the pipeline: lw $, 2($) sub $,$2,$3 and $2,$,$5 or $3,$6,$7 and $,$8,$9 W2-6

17 Activity : Clock Cycle # IF : lw $, 2($) ID : before< > E : before< 2> E : be fore< 3> W B: before < > IF/ID ID/E E/E E/ Control E ress register register 2 s 2 register Reg Src Branch ress em emtoreg [5 ] control em C lo ck [2 6] [5 ] RegDst W2- Op 7

18 Activity : Clock Cycle # 2 IF : sub $, $2, $3 ID : lw $, 2($ ) E : before < > E : be fore<2> W B : be fore < 3> IF/ID ID/E E/E E/ lw Control E ress Reg register register 2 s 2 register $ $ Src Branch em ress emtoreg 2 [5 ] 2 control em C lo c k 2 [2 6] [5 ] RegDst W2- Op 8

19 Activity : Clock Cycle # 3 IF : and $2, $, $ 5 ID : sub $, $ 2, $3 E : lw $,... E : before< > W B : be fore< 2> IF/ID ID/E E/E E/ sub Control E ress 2 3 register register 2 s 2 register Reg $2 $3 $ Src Branch em ress emtoreg [5 ] 2 control em C lock 3 [2 6] [5 ] RegDst W2- Op 9

20 Activity : Clock Cycle # IF : or $ 3, $6, $7 ID : and $ 2, $2, $3 E : sub $,... E : lw $,... W B: be fore< > IF/ID ID/E E/E E/ and Control E ress 5 Reg register register 2 $ $2 s $5 $3 2 register Src Branch em ress emtoreg [5 ] control em C lo ck 2 [2 6] [5 ] 2 RegDst W2- Op 2

21 Activity : Clock Cycle # 5 IF: add $, $8, $9 ID: or $3, $6, $7 E: and $2,... E: sub $,... : lw $,... IF/ID ID/E E/E E/ or Control E ress 6 7 register register 2 s 2 register Reg $6 $7 $ $5 Src Branch em ress emtoreg [5 ] control em Clock 5 3 [2 6] [5 ] 3 2 RegDst W2- Op 2