Designing a Pipelined CPU
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1 Designing a Pipelined CPU CSE 4, S2'6
2 Review -- Single Cycle CPU CSE 4, S2'6
3 Review -- ultiple Cycle CPU CSE 4, S2'6
4 Review -- Instruction Latencies Single-Cycle CPU Load Ifetch /Dec Exec em Wr ultiple Cycle CPU Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch /Dec Exec em Wr Ifetch /Dec Exec Wr CSE 4, S2'6
5 Instruction Latencies and Throughput Single-Cycle CPU Load Ifetch /Dec Exec em Wr ultiple Cycle CPU Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Load Ifetch /Dec Exec em Wr Pipelined CPU Cycle Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Load Ifetch /Dec Exec em Wr Load Ifetch /Dec Exec em Wr Load Ifetch /Dec Exec em Wr Load Ifetch /Dec Exec em Wr CSE 4, S2'6
6 Pipelining Advantages Higher maximum throughput Higher utilization of CPU resources But, more complicated path, more complex control(?) CSE 4, S2'6
7 Pipelining Advantages CPU Design Technology Single-Cycle CPU ultiple-cycle CPU Pipelined CPU Control Logic Combinational Logic FS or icroprogram Peak Throughput CSE 4, S2'6
8 Pipelining in odern CPUs CPU Datapath Arithmetic Units System Buses Software (at multiple levels) etc... CSE 4, S2'6
9 A Pipelined Datapath IF: Instruction fetch ID: Instruction decode and register fetch EX: Execution and effective address calculation E: emory access WB: Write back CSE 4, S2'6
10 Pipelined Datapath
11 Execution in a Pipelined Datapath CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 CC9 lw lw IF ID EX E WB I I D IF ID EX E WB D lw I D lw I D lw I D CSE 4, S2'6 steady state
12 ixed Instructions in the Pipeline CC CC2 CC3 CC4 CC5 CC6 lw I D add I CSE 4, S2'6
13 Pipeline Principles All instructions that share a pipeline must have the same stages in the same order. therefore, add does nothing during em stage sw does nothing during WB stage All intermediate values must be latched each cycle. There is no functional block reuse IF ID EX E WB I D CSE 4, S2'6
14 Pipelined Datapath Instruction Fetch Instruction Decode/ ister Fetch Execute/ ress Calculation emory Access Write Back registers! IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
15 The Pipeline in Execution add $, $, $2 Instruction Decode/ ister Fetch Execute/ ress Calculation emory Access Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
16 The Pipeline in Execution lw $2, ($4) add $, $, $2 Execute/ ress Calculation emory Access Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
17 The Pipeline in Execution sub $5, $4, $ lw $2, ($4) add $, $, $2 emory Access Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
18 The Pipeline in Execution Instruction Fetch sub $5, $4, $ lw $2, ($4) add $, $, $2 Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
19 The Pipeline in Execution Instruction Fetch Instruction Decode/ ister Fetch sub $5, $4, $ lw $2, ($4) add $, $, $2 IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
20 The Pipeline in Execution Instruction Fetch Instruction Decode/ ister Fetch Execute/ ress Calculation sub $5, $4, $ lw $2, ($4) IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
21 The Pipeline, with controls But.
22 Pipelined Control can t use microprogram. FS not really appropriate. Combinational logic! signals generated once, but follow instruction through the pipeline CSE 4, S2'6
23 Pipelined Control instruction control IF/ID ID/EX EX/E E/WB CSE 4, S2'6
24 Pipelined Control Signals Execution Stage Control Lines emory Stage Control Lines Write Back Stage Control Lines Instruction Dst Op Op Src Branch em emwrite Write emto R-Format lw sw x x beq x x CSE 4, S2'6
25 The Pipeline with Control Logic CSE 4, S2'6
26 Is it really that easy? What happens when... add $3, $, $ lw $8, ($3) sub $, $8, $7 CSE 4, S2'6
27 The Pipeline in Execution lw $8, ($3) add $3, $, $ Execute/ ress Calculation emory Access Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
28 The Pipeline in Execution sub $, $8, $7 lw $8, ($3) add $3, $, $ emory Access Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
29 The Pipeline in Execution add $, $, $2 sub $, $8, $7 lw $8, ($3) add $3, $, $ Write Back IF/ID ID/EX EX/ E E /W B 4 Shift left2 PC ress Instruction register register2 isters 2 register 6 Sign extend 32 Zero ress Data CSE 4, S2'6
30 Data Hazards When a is needed in the pipeline before it is available, a hazard occurs. R2 Available CC CC2 CC3 CC4 CC5 CC6 CC7 CC8 sub $2, $, $3 I D and $2, $2, $5 I D or $3, $6, $2 R2 Needed I D add $4, $2, $2 I D sw $5, ($2) I D CSE 4, S2'6
31 Pipelining Key Points ET = IC * CPI * CT We achieve high throughput without reducing instruction latency. Pipelining exploits a special kind of parallelism (parallelism between functionality required in different cycles). Pipelining uses combinational logic (and registers to propogate) to generate control signals. Pipelining creates potential hazards. CSE 4, S2'6
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