SOPC LAB1. I. Introduction. II. Lab contents. 4-bit count up counter. Advanced VLSI Due Wednesday, 01/08/2003
|
|
- Violet Rosemary Cook
- 5 years ago
- Views:
Transcription
1 SOPC LAB1 I. Introduction The purpose of this lab is to familiarize you with all the items in the kit. This tutorial tells you how to develop FPGA system in Quartus II. You are ready to begin using the Nios Development Kit to create your own design. Once you finish your design, you should measure your signal by using LA (Logic Analyzer) and PG (Pattern Generator). II. Lab contents At lab1 you have to design a 4-bit (0 ~ 15) positive edge trigger count up counter. It can load input value when Load = 1 and clear output value when Reset = 1. When Enable = 1 it has output value. So we have 4-input data pins, 4-input control pins (Clock, Reset, Load, and Enable), and 4-output data pins. Use Quartus II to compile your design and download it to APEX20K (we take it as a FPGA board in this Lab). Verify your design by PG and LA. Reset Load Data_in 4 Enable 4-bit count up counter 4 Data_out Clock 12/25/2002 ACCESS IC LAB P. 1
2 Clock Reset Enable Load Data_out H/L/ No Change (Hold) 1 Clear 0 0 No Change (Hold) 0 1 Data_in Count (Increment) III. Tutorial 1. Start the Quartus II Software In this section, you start the Quartus II software and begin creating your project. To start the Quratus II software, use the following methods: Choose Start menu programs Altera Quaruts II <version> 2. Create a project Before you begin, you must create a new Quartus II project. To crate a new project, perform the following steps: (1) Choose File New Project Wizard. (2) Click Next. (3) Specify the working directory for your project. This walkthrough uses the directory C:\my documents\avlsi\<your id no.>\lab1. (4) Specify the name of the project and the top-level design entity. This lab 12/25/2002 ACCESS IC LAB P. 2
3 uses My_project. (5) Click Finish. 3. Create a New.bdf In this step you create a new BDF called My_project.bdf. This file is the top-level design entity of the counter project. To create a new BDF, follow these steps: (1) Choose File New. The Device Design Files tab of the New dialog box appears automatically. (2) In the Device Design Files tab, select Block Diagram / Schmatic file. (3) Click OK. A new Block Editor window appears. (4) Choose File Save As (5) The Save As dialog box automatically displays the project directory C:\my documents\avlsi\<your id no.>\lab1. You will save the file into this directory. (6) In the File name box, type counter as the name of the BDF, if necessary. (7) Make sure Add file to current project is turned on. (8) Click Save. The file is saved and added to the project. Leave the.bdf 12/25/2002 ACCESS IC LAB P. 3
4 open for the remainder of the Design Entry section. 4. Add the Symbol to the BDF In this section you create a new symbol for your Verilog code and add it to your BDF. Follow these steps to add the symbol: (1) Click the Block tool in the Block Editor Toolbar. (2) Click and drag on the block diagram counter.bdf. You can see the block symbol on the diagram. (3) Right click on the Block symbol and choose Block Property. A Block Property window shows. (4) In the Name box, Type counter as the name of the block. (5) Choose I/O and type your I/O pin Name and Type. When you input one pin, click Add to display on Existing block I/Os section. (6) When input all pins, click OK. (7) Right click on the Block symbol and select AutoFit to adjust your block symbol size. 12/25/2002 ACCESS IC LAB P. 4
5 5. Add Pins & Primitives Before you do compilation, you have to enter input, output, and bidirectional pins. Perform the following steps: (1) Click the Symbol Tool button on the Block Editor toolbar. The Symbol dialog box appears. (2) In the libraries list of the Symbol dialog box, click the + icon to expand the C:\quartus\library folder. Expand the primitives folder and then expand the pin folder. (3) In the pin folder, select the input primitive. (4) Click OK. (5) Click an empty space five times to insert a total of 5 INPUT pin symbols. (6) Repeat steps (3) through (4) to inset 1 OUTPUT pin symbol. (7) Double-click the pin symbol that you entered. The General tab of the Pin Properties dialog box appears. (8) Type pin name in the Pin name(s) box. Repeat this until all the pins has it pin name. (9) Move the input pin to touch the Block Symbol, and then move away. You can see they make connection. Repeat this until all the pins have connected. Of course you can use the wire or bus in the Block Editor toolbar to draw the line. 12/25/2002 ACCESS IC LAB P. 5
6 6. Create a Verilog file Now you can write your Verilog code in the block diagram. To write your Verilog code, follow the steps: (1) Right click on the Block symbol and select Create Design file from Selected Block. The Create Design File tab appears automatically. (2) Choose Verilog HDL and input file counter.v in the File name tap. Click OK. (3) You can see the counter.v file that has some information and it creates Module counter and Port Declaration automatically. Write your Verilog code into this file. (4) Repeat steps (1) through (3) to create VHDL code if you are familiar with it. (5) Choose File Save. 12/25/2002 ACCESS IC LAB P. 6
7 7. Create compiler settings You can create Compiler settings to control the compilation process. The compiler settings specify the compilation focus, the type of compilation to perform, the device to target, and other options. This section includes the following steps: (1) Choose Processing Compile Mode (2) Choose Processing Compiler Settings (3) View the Compiler General Settings. It displays only the default compiler general settings created by the Quartus II software when the project was initially created. (4) Specify the Chips & Devices. In the family list, select APEX 20KE then you can see many types listed in the Available devices. Choose EP20K200EFC484-2X for our FPGA design. Under Target device, select Specific device selected in Available device list. You can go to step 8 to do Pin Assignment. (5) Select Mode. In the Compilation level, choose Full compilation, including programming file generation and actual timing data. In compilation speed/disk usage tradeoff, choose Smart compilation/mode disk space. (6) Click Synthesis & Fitting. In the Timing-driven compilation, choose Optimize timing and Optimize I/O cell register placement for timing. (7) Specify Verification. Choose Run timing analysis. (8) Choose Processing Start compilation. You also click the compile toolbar button. (9) When compilation completes, you can view the results in the counter Compilation Report windows. If the Compiler displays any error messages, you should correct them in your design and recompile it until it is error-free. (10) You can select Pin-Out File in the Results for My_project to check if the pin assignment is correct. 12/25/2002 ACCESS IC LAB P. 7
8 8. Specify the Pin Assignments You have to assign your pins in order that we can use LA & PG to verify your design. To verify the pin assignments, follow these steps. (1) Choose Processing Compiler Settings (2) Click the Chips & Devices tab. (3) Click Assign Pins. The Pin Assignments dialog box appears with the new pin assignments listed in the Available Pins & Existing Assignments list. (4) You can see the Connector JP11 in the Figure 1. We use these pins to input and output our values. You also can use other pins that showed in our slides. Choose K1 in the Available Pins & Existing Assignments list. (5) Input Clock (your pin name in the Verilog or VHDL code, for example) in the Pin name. Click Add. (6) Repeat this step until all the pin names are in the Available Pins & Existing Assignments list. (7) Click OK. 12/25/2002 ACCESS IC LAB P. 8
9 Figure 1 9. Create simulate settings You can create Simulate settings to control the simulation process. The simulate settings specify the simulation focus, the type of simulation to perform, time period, and other options. Before you begin, you have to create a new waveform file. Follow these steps to start simulation: 12/25/2002 ACCESS IC LAB P. 9
10 (1) Choose File New. The Device Design Files tab of the New dialog box appears automatically (2) Click Other Files. (3) In the Other Files tab, select Vector Waveform File. (4) Click OK. Then the Waveform Editor Window shows. (5) Choose Time End time. The New Time dialog box appears. You can input the whole time that you want to see. Input 200, for example. Then click OK. (6) Choose View Auxiliary Windows Node Finder. The Node Finder block shows. Select Pins: all in the Filter tab and you can see the counter in the Look tab. (7) Click Start. You can see the I/O pin name display in the Nodes Found. Select the I/O ports you want, and drag them to the Name block of the Waveform. (8) Close Node Finder block. You can see the pins you select display on the Name block and they have their initial value. (9) Next we assign the values on each I/O pins. Right click on the name and choice value count value. The Count Value block shows. Input your test pattern in the Counting block. Keeping doing this until you specify all the input pins values. (10) Choose File Save As. In the File name box, type My_project as the name of the waveform. (11) Choose Processing Simulation. (12) Choose Processing Simulator Settings. View the simulator General Settings. It displays only the default compiler general settings created by the Quartus II software when the project was initially created. (13) Select Time/Vectors. In the simulation period, choose Run simulation 12/25/2002 ACCESS IC LAB P. 10
11 until all vector stimuli are used. (14) Click Mode. In the simulation mode, choose Timing. (15) Specify Options. Choose simulation coverage reporting. (16) Choose Process Run simulation. Then you can see the waveforms in the block and know if it works correctly. 10. Download our program Once you have properly connected and set up the ByteBlasterMV cable to transmit configuration data over the JTAG port, you can configure the APEX device on the Nios development board with your design. To configure the APEX device on the Nios Development board with the counter design, follow these steps: (1) Choose Process Open Programmer. The Programmer window opens a blank Chain Description File (.cdf). (2) Choose File Save AS. (3) In the Save As dialog box, type My_project.cdf in the File name box. (4) Click Save. (5) In the Mode list of the Programmer window, make sure JTAG is selected. (6) Under Programming Hardware, click Setup. The Hardware Setup dialog box appears. (7) In the Hardware Type list, select ByteBlasterMV. (8) In the Port list, select the port that is connect to the ByteBlasterMV cable. Click OK. (9) Click Close to exit the Hardware Setup window. (10) Click Add File. The Select Programming File dialog box appears. (11) Specify the My_project.sof file in the File name box. (12) Click Open. The SOF is listed in the Programmer window. (13) In the Programmer window, turn on Program/Configure. See figure. (14) On the Nios development board, make sure switch SW8 is in the CONNECT position, and that switches SW9 and SW10 are in the BYPASS position. Figure illustrates the correct configuration of the JTAG switches: 12/25/2002 ACCESS IC LAB P. 11
12 (15) Click Start. The Programmer begins to download the configuration data to the APEX device. The Progress filed displays the percentage of data that is downloaded. A message appears when the configuration is complete. 11. Connect Pattern Generator (PG) and Logic Analyzer (LA) Now we connect PG and LA to our Board in order to verify our code. Perform the following steps: (1) Connect the probe of the PG and LA to the input and output pins, respectively, of APEX20K that we defined in step 8. Check carefully with your pin connections and ground also connect to board. (2) Execute the PG. (3) Set work frequency in environment parameter setting. Be sure that 12/25/2002 ACCESS IC LAB P. 12
13 the frequency is not so fast that LA cannot sample it. We set it 20MHz. (4) Set all input pins in signal menu and edit their waveforms. (5) Execute the LA. (6) Set trigger level in trigger level setting. (7) Set all output pins in signal menu. (8) Set sampling frequency. Make sure that the sampling frequency is four times or more the work frequency so that the LA can sample it. We set it 100MHz. (9) Set trigger condition in trigger parameter settings. (10) Push sampling data in the LA. (11) Push output waveform in the PG. (12) Push stop sampling data in the LA. You can see the output waveform. IV. Demands 1. Show your Verilog code (4-bit positive edge trigger counter). 2. Show your Pin-out file. (You can go your My_project directory and find the file.) 3. Show your simulation waveform diagram under the Quartus II simulation mode. 4. Show your result by PG and LA. V. Bonus Is there possible to make your design run at more high frequency? If we can, how do you make it? If not, why? Please discuss this more. 12/25/2002 ACCESS IC LAB P. 13
NIOS CPU Based Embedded Computer System on Programmable Chip
NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems NIOS-II SoPC: PART-II 1 Introduction This lab has been constructed to introduce the development of dedicated
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
1 Objectives NIOS CPU Based Embedded Computer System on Programmable Chip EE8205: Embedded Computer Systems This lab has been constructed to introduce the development of dedicated embedded system based
More informationContents. Appendix B HDL Entry Tutorial 2 Page 1 of 14
Appendix B HDL Entry Tutorial 2 Page 1 of 14 Contents Appendix B HDL Entry Tutorial 2...2 B.1 Getting Started...2 B.1.1 Preparing a Folder for the Project...2 B.1.2 Starting Quartus II...2 B.1.3 Creating
More informationUniversity of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring Lab 1: Using Nios 2 processor for code execution on FPGA
University of Massachusetts Amherst Computer Systems Lab 2 (ECE 354) Spring 2007 Lab 1: Using Nios 2 processor for code execution on FPGA Objectives: After the completion of this lab: 1. You will understand
More informationTutorial on Quartus II Introduction Using Schematic Designs
Tutorial on Quartus II Introduction Using Schematic Designs (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD
More informationUniversity Program 3 Kit
University Program 3 Kit VLSI Tutorial : LEDs & Push Buttons Version 02.00 System Level Solutions Inc. (USA) 14702 White Cloud Ct. Morgan Hill, CA 95037 2 System Level Solutions Copyright 2003-2005 System
More informationTutorial on Quartus II Introduction Using Verilog Code
Tutorial on Quartus II Introduction Using Verilog Code (Version 15) 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD flow
More informationChapter 2 Getting Hands on Altera Quartus II Software
Chapter 2 Getting Hands on Altera Quartus II Software Contents 2.1 Installation of Software... 20 2.2 Setting Up of License... 21 2.3 Creation of First Embedded System Project... 22 2.4 Project Building
More informationQUARTUS II Altera Corporation
QUARTUS II Quartus II Design Flow Design Entry Timing Constraints Synthesis Placement and Routing Timing, Area, Power Optimization Timing and Power Analyzer Optimized Design 2 Can I still use a Processor?
More informationCPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND:
CPE 200L LABORATORY 4: INTRODUCTION TO DE2 BOARD DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Getting familiar with DE2 board installation, properties, usage.
More informationECE 3610 Microprocessing Systems Lab #1 Verilog Design of the TOC Using Quartus II
ECE 3610 Microprocessing Systems Lab #1 Verilog Design of the TOC Using Quartus II This lab manual presents an introduction to the Quartus II Computer Aided Design (CAD) system. This manual gives step-by-step
More informationTUTORIALS FOR MAX3000A CPLD DEVICES
TUTORIALS FOR MAX3000A CPLD DEVICES WEL LAB 6-BIT-UP-DOWN-COUNTER CONTENTS: INTRODUCTION.. GETTING STARTED. DESIGN ENTRY. PIN ASSIGNMENT. PROGRAMMING CPLD DEVICE. REFERENCES. WEL LAB, IIT BOMBAY Page 2
More informationUNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC180A DIGITAL SYSTEMS I Winter 2015
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC180A DIGITAL SYSTEMS I Winter 2015 LAB 1: Introduction to Quartus II Schematic Capture and ModelSim Simulation This
More informationEMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 6: Quartus II Tutorial and Practice. Name: Date:
EXPERIMENT # 6: Quartus II Tutorial and Practice Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn how to
More informationNIOS CPU Based Embedded Computer System on Programmable Chip
NIOS CPU Based Embedded Computer System on Programmable Chip 1 Lab Objectives EE8205: Embedded Computer Systems NIOS-II SoPC: PART-I This lab has been constructed to introduce the development of dedicated
More informationTutorial for Altera DE1 and Quartus II
Tutorial for Altera DE1 and Quartus II Qin-Zhong Ye December, 2013 This tutorial teaches you the basic steps to use Quartus II version 13.0 to program Altera s FPGA, Cyclone II EP2C20 on the Development
More informationUniversity of Florida EEL 3701 Dr. Eric M. Schwartz Madison Emas, TA Department of Electrical & Computer Engineering Revision 1 5-Jun-17
Page 1/14 Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate and two inverters under the Quartus environment. Upon completion
More informationQuartus II Introduction Using Schematic Design
Quartus II Introduction Using Schematic Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented
More informationQuartusII.doc 25/02/2005 Page 1
1 Start Icon... 2 1.1 The Quartus II Screen... 2 2 Project creation... 2 3 Schematic entry... 5 3.1 Create new drawing... 5 3.2 Symbol selection... 7 3.3 Placement of an AND gate... 8 3.4 Deleting a symbol...
More informationUsing Synplify Pro, ISE and ModelSim
Using Synplify Pro, ISE and ModelSim VLSI Systems on Chip ET4 351 Rene van Leuken Huib Lincklaen Arriëns Rev. 1.2 The EDA programs that will be used are: For RTL synthesis: Synplicity Synplify Pro For
More informationSCHEMATIC DESIGN IN QUARTUS
SCHEMATIC DESIGN IN QUARTUS Consider the design of a three-bit prime number detector. Figure 1 shows the block diagram and truth table. The inputs are binary signals A, B, and C while the output is binary
More informationFPGA Introductory Tutorial: Part 1
FPGA Introductory Tutorial: Part 1 This tutorial is designed to assist in learning the basics of the Altera Quartus II v9.0 software. Part 1 of the tutorial will cover the basics of creating a Project,
More informationEE 231 Fall Lab 1: Introduction to Verilog HDL and Altera IDE
Lab 1: Introduction to Verilog HDL and Altera IDE Introduction In this lab you will design simple circuits by programming the Field-Programmable Gate Array (FPGA). At the end of the lab you should be able
More informationTerasic DE0 Field Programmable Gate Array (FPGA) Development Board
Lecture FPGA-01 DE0 FPGA Development Board and Quartus II 9.1 FPGA Design Software Terasic DE0 Field Programmable Gate Array (FPGA) Development Board 1 May 16, 2013 3 Layout and Components of DE0 May 16,
More informationViCoN-Bot Tutorial. Users Guide Summer 2002 Version 1.0. Jeff Vickers Kwabena Bosompem Kevin Walker Andre Moore
ViCoN-Bot Tutorial Users Guide Summer 2002 Version 1.0 Jeff Vickers Kwabena Bosompem Kevin Walker Andre Moore Introduction This document gives instructions on how to make the ViCoN-Bot traverse a track
More informationCHAPTER 1 INTRODUCTION... 1 CHAPTER 2 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY CHAPTER 4 COMPILE AND VERIFY YOUR DESIGN...
CONTENTS CHAPTER 1 INTRODUCTION... 1 1.1 DESIGN FLOW... 1 1.2 BEFORE YOU BEGIN... 2 1.3 WHAT YOU WILL LEARN... 6 CHAPTER 2 ASSIGN THE DEVICE... 7 2.1 ASSIGN THE DEVICE... 7 CHAPTER 3 DESIGN ENTRY... 11
More informationLab 2: Introduction to Verilog HDL and Quartus
Lab 2: Introduction to Verilog HDL and Quartus September 16, 2008 In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At
More informationTUTORIALS FOR MAX3000A CPLD DEVICES
TUTORIALS FOR MAX3000A CPLD DEVICES WEL LAB BCD DECODER CONTENTS: INTRODUCTION.. GETTING STARTED. DESIGN ENTRY. PIN ASSIGNMENT. PROGRAMMING CPLD DEVICE. REFERENCES. WEL LAB, IIT BOMBAY Page 2 Introduction:
More informationAltera Quartus II Tutorial ECE 552
Altera Quartus II Tutorial ECE 552 Quartus II by Altera is a PLD Design Software which is suitable for high-density Field-Programmable Gate Array (FPGA) designs, low-cost FPGA designs, and Complex Programmable
More informationQuick Tutorial for Quartus II & ModelSim Altera
Quick Tutorial for Quartus II & ModelSim Altera By Ziqiang Patrick Huang Hudson 213c Ziqiang.huang@duke.edu Download & Installation For Windows or Linux users : Download Quartus II Web Edition v13.0 (ModelSim
More informationChapter 2: Hardware Design Flow Using Verilog in Quartus II
Chapter 2: Hardware Design Flow Using Verilog in Quartus II 2.1 Introduction to Quartus II System Development Software This chapter is an introduction to the Quartus II software that will be used for analysis
More informationQuartus II Introduction Using Verilog Design
Quartus II Introduction Using Verilog Design This tutorial presents an introduction to the Quartus R II CAD system. It gives a general overview of a typical CAD flow for designing circuits that are implemented
More informationLab 6: Integrated the Decoder with Muti-bit Counter and Programming a FPGA
Lab 6: Integrated the Decoder with Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design
More informationEE 231 Fall EE 231 Lab 2
EE 231 Lab 2 Introduction to Verilog HDL and Quartus In the previous lab you designed simple circuits using discrete chips. In this lab you will do the same but by programming the CPLD. At the end of the
More informationUniversity of Florida EEL 3701 Dr. Eric M. Schwartz Department of Electrical & Computer Engineering Revision 0 12-Jun-16
Page 1/14 Quartus Tutorial with Basic Graphical Gate Entry and Simulation Example Problem Given the logic equation Y = A*/B + /C, implement this equation using a two input AND gate, a two input OR gate
More information2 nd Year Laboratory. Experiment: FPGA Design with Verilog. Department of Electrical & Electronic Engineering. Imperial College London.
Department of Electrical & Electronic Engineering 2 nd Year Laboratory Experiment: FPGA Design with Verilog Objectives By the end of this experiment, you should know: How to design digital circuits using
More informationECSE-323 Digital System Design. Lab #1 Using the Altera Quartus II Software Fall 2008
1 ECSE-323 Digital System Design Lab #1 Using the Altera Quartus II Software Fall 2008 2 Introduction. In this lab you will learn the basics of the Altera Quartus II FPGA design software through following
More informationEXPERIMENT 1. INTRODUCTION TO ALTERA
EXPERIMENT 1. INTRODUCTION TO ALTERA I. Introduction I.I Objectives In this experiment, you will learn computer aided digital design and verification of it using Field Programmable Gate Arrays (FPGA).
More informationLaboratory 4 Design a Muti-bit Counter and Programming a FPGA
Laboratory 4 Design a Muti-bit Counter and Programming a FPGA For your report: The problem written in English The flowchart or function table to solve the problem if it is necessary The design entry included
More informationDesign Verification Using the SignalTap II Embedded
Design Verification Using the SignalTap II Embedded Logic Analyzer January 2003, ver. 1.0 Application Note 280 Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera
More informationEngineering 303 Digital Logic Design Spring 2017
Engineering 303 Digital Logic Design Spring 2017 LAB 1 Introduction to Combo Logic and Quartus Deliverables: 0) A Simple Verilog Combinatorial Circuit 1) A Simple Block Diagram Combinatorial Circuit 2)
More informationLaboratory Exercise 8
Laboratory Exercise 8 Memory Blocks In computer systems it is necessary to provide a substantial amount of memory. If a system is implemented using FPGA technology it is possible to provide some amount
More informationECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004
Goals ECE 491 Laboratory 1 Introducing FPGA Design with Verilog September 6, 2004 1. To review the use of Verilog for combinational logic design. 2. To become familiar with using the Xilinx ISE software
More informationEMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 7: VHDL and DE2 Board. Name: Date:
EXPERIMENT # 7: VHDL and DE2 Board Name: Date: Equipment/Parts Needed: Quartus II R Web Edition V9.1 SP2 software by Altera Corporation USB drive to save your files Objective: Learn how to create and modify
More informationBoard-Data Processing. VHDL Exercises. Exercise 1: Basics of VHDL Programming. Stages of the Development process using FPGA s in Xilinx ISE.
Board-Data Processing VHDL Exercises Exercise 1: Basics of VHDL Programming Stages of the Development process using FPGA s in Xilinx ISE. Basics of VHDL VHDL (Very High Speed IC Hardware description Language)
More informationCOSC 3215 Embedded Systems Laboratory
COSC 3215 Embedded Systems Laboratory Lab 5 The Altera, Verilog and QuartusII Introduction This lab is an introduction to the Altera FPGA development board and the accompanying FPGA programming environment
More informationUNIVERSITI MALAYSIA PERLIS
UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT 124 LABORATORY MODULE INTRODUCTION TO QUARTUS II DESIGN SOFTWARE : INTRODUCTION TO QUARTUS II DESIGN SOFTWARE OBJECTIVES To
More informationQuartus. Tutorial. Programmable Logic Development System
Quartus Programmable Logic Development System Tutorial Altera Corporation 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Version 1999.10 Revision 2 November 1999 P25-04732-01
More informationIntroduction. Design Hierarchy. FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow
FPGA Compiler II BLIS & the Quartus II LogicLock Design Flow February 2002, ver. 2.0 Application Note 171 Introduction To maximize the benefits of the LogicLock TM block-based design methodology in the
More informationSignalTap II with Verilog Designs. 1 Introduction. For Quartus II 13.1
SignalTap II with Verilog Designs For Quartus II 13.1 1 Introduction This tutorial explains how to use the SignalTap II feature within Altera s Quartus II software. The SignalTap II Embedded Logic Analyzer
More informationUniversity of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual
University of Massachusetts Amherst Computer Systems Lab 1 (ECE 354) LAB 1 Reference Manual Lab 1: Using NIOS II processor for code execution on FPGA Objectives: 1. Understand the typical design flow in
More information1 Introduction 2. 2 Background 3. 3 Getting Started 4. 4 Starting a New Project 6. 5 Design Entry Using VHDL Code 13
Quartus Prime Introduction Using VHDL Designs For Quartus Prime 17.0 Contents 1 Introduction 2 2 Background 3 3 Getting Started 4 3.1 Quartus Prime Online Help................................................................................................
More informationDKAN0011A Setting Up a Nios II System with SDRAM on the DE2
DKAN0011A Setting Up a Nios II System with SDRAM on the DE2 04 November 2009 Introduction This tutorial details how to set up and instantiate a Nios II system on Terasic Technologies, Inc. s DE2 Altera
More informationQuartus II Introduction Using Verilog Designs. 1 Introduction. For Quartus II 12.0
Quartus II Introduction Using Verilog Designs For Quartus II 12.0 1 Introduction This tutorial presents an introduction to the Quartus II CAD system. It gives a general overview of a typical CAD flow for
More informationChipScope Demo Instructions
UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Overview ChipScope is an embedded, software based logic analyzer. By inserting an intergrated
More informationLaboratory 4 Design a Muti-bit Counter
Laboratory 4 Design a Muti-bit Counter Background A. Approach I: Design 3-bit counter with and clear T-type flip-flop is shown in Figure 1. A T flip-flop is obtained from a JK flip-flop by tying the J
More informationJune 2003, ver. 1.2 Application Note 198
Timing Closure with the Quartus II Software June 2003, ver. 1.2 Application Note 198 Introduction With FPGA designs surpassing the multimillion-gate mark, designers need advanced tools to better address
More informationAN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board
AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents Partially Reconfiguring
More informationDOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA
DOWNLOADING DESIGNS TO THE ALTERA DE10-LITE FPGA Consider the design of a three-bit prime number detector completed in the MSOE schematic entry tutorial. Figure 1 shows the block diagram and truth table.
More informationVerilog Design Entry, Synthesis, and Behavioral Simulation
------------------------------------------------------------- PURPOSE - This lab will present a brief overview of a typical design flow and then will start to walk you through some typical tasks and familiarize
More informationECE 4305 Computer Architecture Lab #1
ECE 4305 Computer Architecture Lab #1 The objective of this lab is for students to familiarize with the FPGA prototyping system board (Nexys-2) and the Xilinx software development environment that will
More informationUniversity of California, Davis Department of Electrical and Computer Engineering. Lab 1: Implementing Combinational Logic in the MAX10 FPGA
1 University of California, Davis Department of Electrical and Computer Engineering EEC180B DIGITAL SYSTEMS II Winter Quarter 2018 Lab 1: Implementing Combinational Logic in the MAX10 FPGA Objective: This
More informationA Beginner's Guide to MAX+plus II
A Beginner's Guide to MAX+plus II Author: Jacinda Clemenzi - Last Updated: December 20, 2001 Last Revised: Frank Honoré - January 23, 2004 The purpose of this guide is to provide a tutorial that will help
More informationSimulating a Design Circuit Using Qsim
Simulating a Design Circuit Using Qsim 1. Start Qsim From version 11.1, Quartus II provides another simulating tool called Qsim. Qsim is bundled with both subscript edition and web edition of Quartus II.
More informationXilinx ChipScope ICON/VIO/ILA Tutorial
Xilinx ChipScope ICON/VIO/ILA Tutorial The Xilinx ChipScope tools package has several modules that you can add to your Verilog design to capture input and output directly from the FPGA hardware. These
More information16. Design Debugging Using In-System Sources and Probes
June 2012 QII53021-12.0.0 16. Design Debugging Using In-System Sources and Probes QII53021-12.0.0 This chapter provides detailed instructions about how to use the In-System Sources and Probes Editor and
More informationExercise 1 In this exercise you will review the DSSS modem design using the Quartus II software.
White Paper DSSS Modem Lab Background The direct sequence spread spectrum (DSSS) digital modem reference design is a hardware design that has been optimized for the Altera APEX DSP development board (starter
More informationXilinx Schematic Entry Tutorial
Overview Xilinx Schematic Entry Tutorial Xilinx ISE Schematic Entry & Modelsim Simulation What is circuit simulation and why is it important? Complex designs, short design cycle Simultaneous system design
More informationDesign Flow Tutorial
Digital Design LU Design Flow Tutorial Jakob Lechner, Thomas Polzer {lechner, tpolzer}@ecs.tuwien.ac.at Department of Computer Engineering University of Technology Vienna Vienna, October 8, 2010 Contents
More information9. Building Memory Subsystems Using SOPC Builder
9. Building Memory Subsystems Using SOPC Builder QII54006-6.0.0 Introduction Most systems generated with SOPC Builder require memory. For example, embedded processor systems require memory for software
More informationChip Design with FPGA Design Tools
Chip Design with FPGA Design Tools Intern: Supervisor: Antoine Vazquez Janusz Zalewski Florida Gulf Coast University Fort Myers, FL 33928 V1.9, August 28 th. Page 1 1. Introduction FPGA is abbreviation
More informationIntroduction to the Altera SOPC Builder Using Verilog Design
Introduction to the Altera SOPC Builder Using Verilog Design This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the Nios II processor
More informationSimulating Nios II Embedded Processor Designs
Simulating Nios II Embedded Processor Designs May 2004, ver.1.0 Application Note 351 Introduction The increasing pressure to deliver robust products to market in a timely manner has amplified the importance
More informationEE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09
EE 367 Logic Design Lab #1 Introduction to Xilinx ISE and the ML40X Eval Board Date: 1/21/09 Due: 1/28/09 Lab Description Today s lab will introduce you to the Xilinx Integrated Software Environment (ISE)
More informationUsing SOPC Builder. with Excalibur Devices Tutorial. 101 Innovation Drive San Jose, CA (408)
Using SOPC Builder with Excalibur Devices Tutorial 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 http://www.altera.com Document Version: 1.0 Document Date: July 2002 Copyright Excalibur Devices
More information13. LogicLock Design Methodology
13. LogicLock Design Methodology QII52009-7.0.0 Introduction f Available exclusively in the Altera Quartus II software, the LogicLock feature enables you to design, optimize, and lock down your design
More informationCHAPTER 1 Introduction of the tnano Board CHAPTER 2 tnano Board Architecture CHAPTER 3 Using the tnano Board... 8
CONTENTS CHAPTER 1 Introduction of the tnano Board... 2 1.1 Features...2 1.2 About the KIT...4 1.3 Getting Help...4 CHAPTER 2 tnano Board Architecture... 5 2.1 Layout and Components...5 2.2 Block Diagram
More informationEstimating Nios Resource Usage & Performance
Estimating Nios Resource Usage & Performance in Altera Devices September 2001, ver. 1.0 Application Note 178 Introduction The Excalibur Development Kit, featuring the Nios embedded processor, includes
More informationActel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial
Actel Libero TM Integrated Design Environment v2.3 Structural Schematic Flow Design Tutorial 1 Table of Contents Design Flow in Libero TM IDE v2.3 Step 1 - Design Creation 3 Step 2 - Design Verification
More informationExperiment VERI: FPGA Design with Verilog (Part 1)
Experiment VERI: Department of Electrical & Electronic Engineering 2nd Year Laboratory Experiment VERI: FPGA Design with Verilog (Part 1) (webpage: www.ee.ic.ac.uk/pcheung/teaching/e2_experiment /) Objectives
More informationDebugging Nios II Systems with the SignalTap II Logic Analyzer
Debugging Nios II Systems with the SignalTap II Logic Analyzer May 2007, ver. 1.0 Application Note 446 Introduction As FPGA system designs become more sophisticated and system focused, with increasing
More informationXilinx Vivado/SDK Tutorial
Xilinx Vivado/SDK Tutorial (Laboratory Session 1, EDAN15) Flavius.Gruian@cs.lth.se March 21, 2017 This tutorial shows you how to create and run a simple MicroBlaze-based system on a Digilent Nexys-4 prototyping
More informationXilinx Tutorial Basic Walk-through
Introduction to Digital Logic Design with FPGA s: Digital logic circuits form the basis of all digital electronic devices. FPGAs (Field Programmable Gate Array) are large programmable digital electronic
More informationLab 2 EECE473 Computer Organization & Architecture University of Maine
Lab 2: Verilog Programming Instructor: Yifeng Zhu 50 Points Objectives: 1. Quatus II Programming assignment: PIN assignments, LEDs, switches; 2. Download and test the design on Altera DE2 board 3. Create
More informationAN 839: Design Block Reuse Tutorial
AN 839: Design Block Reuse Tutorial for Intel Arria 10 FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents Contents
More informationAN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board
AN 825: Partially Reconfiguring a Design on Intel Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 17.1 Subscribe Send Feedback Latest document on the web: PDF HTML Contents
More informationTutorial 2 Implementing Circuits in Altera Devices
Appendix C Tutorial 2 Implementing Circuits in Altera Devices In this tutorial we describe how to use the physical design tools in Quartus II. In addition to the modules used in Tutorial 1, the following
More informationIntroduction to the Altera SOPC Builder Using Verilog Designs. 1 Introduction
Introduction to the Altera SOPC Builder Using Verilog Designs 1 Introduction This tutorial presents an introduction to Altera s SOPC Builder software, which is used to implement a system that uses the
More informationCircuit design with configurable devices (FPGA)
1 Material Circuit design with configurable devices (FPGA) Computer with Xilinx's ISE software installed. Digilent's Basys2 prototype board and documentation. Sample design files (lab kit). Files and documents
More informationCSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools
CSE P567 - Winter 2010 Lab 1 Introduction to FGPA CAD Tools This is a tutorial introduction to the process of designing circuits using a set of modern design tools. While the tools we will be using (Altera
More informationAN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board
AN 826: Hierarchical Partial Reconfiguration Tutorial for Stratix 10 GX FPGA Development Board Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF
More informationEE 1315 DIGITAL LOGIC LAB EE Dept, UMD
EE 1315 DIGITAL LOGIC LAB EE Dept, UMD EXPERIMENT # 1: Logic building blocks The main objective of this experiment is to let you familiarize with the lab equipment and learn about the operation of the
More informationBoard Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit)
Board Update Portal based on Nios II Processor with EPCQ (Arria 10 GX FPGA Development Kit) Date: 1 December 2016 Revision:1.0 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY,
More informationBanks, Jasmine Elizabeth (2011) The Spartan 3E Tutorial 1 : Introduction to FPGA Programming, Version 1.0. [Tutorial Programme]
QUT Digital Repository: http://eprints.qut.edu.au/ This is the author version published as: This is the accepted version of this article. To be published as : This is the author s version published as:
More informationAN 818: Static Update Partial Reconfiguration Tutorial
AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX Updated for Intel Quartus Prime Design Suite: 18.1 Subscribe Latest document on the web: PDF HTML Contents Contents 1. Static
More informationPRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory.
PRELAB! Read the entire lab, and complete the prelab questions (Q1- Q3) on the answer sheet before coming to the laboratory. 1.0 Objectives In this lab you will get familiar with the concept of using the
More informationUsing ChipScope. Overview. Detailed Instructions: Step 1 Creating a new Project
UNIVERSITY OF CALIFORNIA AT BERKELEY COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCE Using ChipScope Overview ChipScope is an embedded, software based logic analyzer. By
More informationAN 818: Static Update Partial Reconfiguration Tutorial
AN 818: Static Update Partial Reconfiguration Tutorial for Intel Stratix 10 GX FPGA Development Updated for Intel Quartus Prime Design Suite: 18.0 Subscribe Send Feedback Latest document on the web: PDF
More informationProgrammable Logic Design I
Programmable Logic Design I Introduction In labs 11 and 12 you built simple logic circuits on breadboards using TTL logic circuits on 7400 series chips. This process is simple and easy for small circuits.
More information