CSF Cache Introduction. [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]

Transcription

1 CSF Cache Introduction [Adapted from Computer Organization and Design, Patterson & Hennessy, 2005]

2 Review: The Memory Hierarchy Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology Increasing distance from the processor in access time Processor 4-8 bytes (word) L1$ 8-32 bytes (block) L2$ 1 to 4 blocks Main Memory Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM Secondary Memory 1,024+ bytes (disk sector = page) (Relative) size of the memory at each level

3 The Memory Hierarchy: Why Does it Work? Temporal Locality (Locality in Time): apple Keep most recently accessed data items closer to the processor Spatial Locality (Locality in Space): apple Move blocks consisting of contiguous words to the upper levels To Processor From Processor Upper Level Memory Blk X Lower Level Memory Blk Y

4 The Memory Hierarchy: Terminology Hit: data is in some block in the upper level (Blk X) Hit Rate: the fraction of memory accesses found in the upper level Hit Time: Time to access the upper level which consists of RAM access time + Time to determine hit/miss To Processor Upper Level Memory Lower Level Memory From Processor Blk X Blk Y Miss: data is not in the upper level so needs to be retrieve from a block in the lower level (Blk Y) Miss Rate = 1 - (Hit Rate) Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor Hit Time << Miss Penalty

5 How is the Hierarchy Managed? registers apple memory by compiler (programmer?) cache apple main memory by the cache controller hardware main memory apple disks by the operating system (virtual memory) virtual to physical address mapping assisted by the hardware (TLB) by the programmer (files)

6 Cache Two questions to answer (in hardware): Q1: How do we know if a data item is in the cache? Q2: If it is, how do we find it? Direct mapped For each item of data at the lower level, there is exactly one location in the cache where it might be - so lots of items at the lower level must share locations in the upper level Address mapping: (block address) modulo (# of blocks in the cache) First consider block sizes of one word

7 Caching: A Simple First Example Cache Index Valid Tag Q1: Is it there? Data Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache 0000xx 0001xx 0010xx 0011xx 0100xx 0101xx 0110xx 0111xx 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx Main Memory Two low order bits define the byte in the word (32-b words) Q2: How do we find it? Use next 2 low order memory address bits the index to determine which cache block (i.e., modulo the number of blocks in the cache) (block address) modulo (# of blocks in the cache)

8 Caching: A Simple First Example Cache Index Valid Tag Q1: Is it there? Data Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache 0000xx 0001xx 0010xx 0011xx 0100xx 0101xx 0110xx 0111xx 1000xx 1001xx 1010xx 1011xx 1100xx 1101xx 1110xx 1111xx Main Memory Two low order bits define the byte in the word (32b words) Q2: How do we find it? Use next 2 low order memory address bits the index to determine which cache block (i.e., modulo the number of blocks in the cache) (block address) modulo (# of blocks in the cache)

9 Direct Mapped Cache Consider the main memory word reference string Start with an empty cache - all blocks initially marked as not valid

10 Direct Mapped Cache Consider the main memory word reference string Start with an empty cache - all blocks initially marked as not valid miss 1 miss 2 miss 3 miss 00 Mem(0) 00 Mem(0) 00 Mem(0) 00 Mem(0) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(2) 00 Mem(2) 00 Mem(3) 4 miss 3 hit 4 hit 15 miss Mem(0) 01 Mem(4) 01 Mem(4) 01 Mem(4) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(1) 00 Mem(2) 00 Mem(2) 00 Mem(2) 00 Mem(2) 00 Mem(3) 00 Mem(3) 00 Mem(3) Mem(3) 15 8 requests, 6 misses

11 MIPS Direct Mapped Cache Example One word/block, cache size = 1K words Byte offset Hit Tag Index Data Index Valid Tag 20 Data 32 What kind of locality are we taking advantage of?

12 Handling Cache Hits Read hits (I$ and D$) this is what we want! Write hits (D$ only) allow cache and memory to be inconsistent - write the data only into the cache block (write-back the cache contents to the next level in the memory hierarchy when that cache block is evicted ) - need a dirty bit for each data cache block to tell if it needs to be written back to memory when it is evicted require the cache and memory to be consistent - always write the data into both the cache block and the next level in the memory hierarchy (write-through) so don t need a dirty bit - writes run at the speed of the next level in the memory hierarchy so slow! or can use a write buffer, so only have to stall if the write buffer is full

13 Write Buffer for Write-Through Caching Processor Cache DRAM Write buffer between the cache and main memory Processor: writes data into the cache and the write buffer Memory controller: writes contents of the write buffer to memory The write buffer is just a FIFO Typical number of entries: 4 write buffer Works fine if store frequency (w.r.t. time) << 1 / DRAM write cycle Memory system designer s nightmare When the store frequency (w.r.t. time) 1 / DRAM write cycle leading to write buffer saturation - One solution is to use a write-back cache; another is to use an L2 cache (next lecture)

14 Review: Why Pipeline? For Throughput! To avoid a structural hazard need two caches on-chip: one for instructions (I$) and one for data (D$) Time (clock cycles) I n s t r. O r d e r Inst 0 Inst 1 Inst 2 Inst 3 Inst 4 ALU I$ Reg D$ Reg ALU I$ Reg D$ Reg ALU I$ Reg D$ Reg ALU I$ Reg D$ Reg ALU I$ Reg D$ Reg To keep the pipeline running at its maximum rate both I$ and D$ need to satisfy a request from the datapath every cycle. What happens when they can t do that?

15 Another Reference String Mapping Consider the main memory word reference string Start with an empty cache - all blocks initially marked as not valid

16 Another Reference String Mapping Consider the main memory word reference string Start with an empty cache - all blocks initially marked as not valid miss 4 miss 0 miss 4 miss Mem(0) 00 Mem(0) 01 Mem(4) Mem(0) 4 0 miss 4 miss 0 miss 4 miss Mem(4) Mem(0) 01 Mem(4) 0 00 Mem(0) 8 requests, 8 misses Ping pong effect due to conflict misses - two memory locations that map into the same cache block

17 Sources of Cache Misses Compulsory (cold start or process migration, first reference): First access to a block, cold fact of life, not a whole lot you can do about it If you are going to run millions of instruction, compulsory misses are insignificant Conflict (collision): Multiple memory locations mapped to the same cache location Solution 1: increase cache size Solution 2: increase associativity (next lecture) Capacity: Cache cannot contain all blocks accessed by the program Solution: increase cache size

18 Handling Cache Misses Read misses (I$ and D$) stall the entire pipeline, fetch the block from the next level in the memory hierarchy, install it in the cache and send the requested word to the processor, then let the pipeline resume Write misses (D$ only) 1. stall the pipeline, fetch the block from next level in the memory hierarchy, install it in the cache (which may involve having to evict a dirty block if using a write-back cache), write the word from the processor to the cache, then let the pipeline resume or (normally used in write-back caches) 2. Write allocate just write the word into the cache updating both the tag and data, no need to check for cache hit, no need to stall or (normally used in write-through caches with a write buffer) 3. No-write allocate skip the cache write and just write the word to the write buffer (and eventually to the next memory level), no need to stall if the write buffer isn t full; must invalidate the cache block since it will be inconsistent (now holding stale data)

19 Multiword Block Direct Mapped Cache Four words/block, cache size = 1K words Hit Byte offset Data Tag 20 Index 8 Block offset Index Valid Tag 20 Data What kind of locality are we taking advantage of? 32

20 Taking Advantage of Spatial Locality Let cache block hold more than one word Start with an empty cache - all blocks initially marked as not valid

21 Taking Advantage of Spatial Locality Let cache block hold more than one word Start with an empty cache - all blocks initially marked as not valid miss 00 Mem(1) Mem(0) 1 hit 2 00 Mem(1) Mem(0) miss 00 Mem(1) Mem(0) 00 Mem(3) Mem(2) 3 hit 4 miss 3 hit Mem(1) Mem(0) 00 Mem(3) Mem(2) 00 Mem(1) Mem(0) 00 Mem(3) Mem(2) 01 Mem(5) Mem(4) 00 Mem(3) Mem(2) 4 hit 15 miss 01 Mem(5) Mem(4) 00 Mem(3) Mem(2) 8 requests, 4 misses 1101 Mem(5) Mem(4) Mem(3) Mem(2)

22 Miss Rate vs Block Size vs Cache Size Miss rate goes up if the block size becomes a significant fraction of the cache size because the number of blocks that can be held in the same size cache is smaller (increasing capacity misses)

23 Block Size Tradeoff Larger block sizes take advantage of spatial locality but If the block size is too big relative to the cache size, the miss rate will go up Larger block size means larger miss penalty - Latency to first word in block + transfer time for remaining words Miss Rate Exploits Spatial Locality Fewer blocks compromises Temporal Locality Miss Penalty Average Access Time Increased Miss Penalty & Miss Rate Block Size Block Size Block Size In general, Average Memory Access Time = Hit Time + Miss Penalty x Miss Rate

24 Multiword Block Considerations Read misses (I$ and D$) Processed the same as for single word blocks a miss returns the entire block from memory Miss penalty grows as block size grows - Early restart datapath resumes execution as soon as the requested word of the block is returned - Requested word first requested word is transferred from the memory to the cache (and datapath) first Nonblocking cache allows the datapath to continue to access the cache while the cache is handling an earlier miss Write misses (D$) Can t use write allocate or will end up with a garbled block in the cache (e.g., for 4 word blocks, a new tag, one word of data from the new block, and three words of data from the old block), so must fetch the block from memory first and pay the stall time

25 Cache Summary The Principle of Locality: Program likely to access a relatively small portion of the address space at any instant of time - Temporal Locality: Locality in Time - Spatial Locality: Locality in Space Three major categories of cache misses: Compulsory misses: sad facts of life. Example: cold start misses Conflict misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! Capacity misses: increase cache size Cache design space total size, block size, associativity (replacement policy) write-hit policy (write-through, write-back) write-miss policy (write allocate, write buffers)