MICROPROGRAMMED CONTROL
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1 1 MICROPROGRAMMED CONTROL Control Memory Sequencing Microinstructions Microprogram Example Design of Control nit Microinstruction Format Nanostorage and Nanoprogram
2 2 Implementation of Control nit COMPARISON OF CONTROL NIT IMPLEMENTATIONS Control nit Implementation Combinational Logic Circuits (Hard-wired) Memory Control Data I R Status F/Fs Control nit's State Timing State Ins. Cycle State Combinational Logic Circuits Control Points CP Microprogram M e m o r y Control Data I R Status F/Fs Next Address Generation Logic C S A R Control Storage ( -program memory) C S D R } D C P s CP
3 3 TERMINOLOGY Microprogram / Microcode (corresponding to one CP instruction) - Consists of microinstructions - Program stored in memory that generates all control signals required to execute the instruction set correctly Microinstruction - Contains a control word and a sequencing word Control Word - All control information required for one clock cycle Sequencing Word - Information needed to decide the next microinstruction address Control Memory (Control Storage: CS) - Storage for microprogram. Generally ROM Writeable Control Memory (Writeable Control Storage:WCS) - CS whose contents can be modified -> microprogram -> Instruction set Dynamic Microprogramming - Computer system whose control unit is implemented with a microprogram in WCS - Microprogram can be changed by a system programmer or a user
4 4 TERMINOLOGY Sequencer (Microprogram Sequencer) A Microprogram Control nit that determines the Microinstruction Address to be executed in the next clock cycle Sequencing Capabilities Required in a Control Storage - Incrementing of the control address register - nconditional and conditional branches - A mapping process from the bits of the machine instruction to an address for control memory - A facility for subroutine call and return
5 5 MICROINSTRCTION SEQENCING Sequencing Instruction code Mapping logic Status bits Branch logic MX select Multiplexers Control address register (CAR) Subroutine register (SBR) Incrementer Control memory (ROM) select a status bit Branch address Microoperations
6 6 CONDITIONAL BRANCH Sequencing Conditional Branch If Condition is true, then Branch (address from the next address field of the current microinstruction) else Fall Through Conditions to Test: O(overflow), N(negative), Z(zero), C(carry), etc. nconditional Branch Fixing the value of one status bit at the input of the multiplexer to 1
7 7 MAPPING OF INSTRCTIONS Sequencing Direct Mapping OP-codes of Instructions ADD 0000 AND 0001 LDA 0010 STA 0011 BN Address ADD Routine AND Routine LDA Routine STA Routine BN Routine Control Storage Mapping Bits 10 xxxx 010 Address ADD Routine AND Routine LDA Routine STA Routine BN Routine
8 8 MAPPING OF INSTRCTIONS TO MICROROTINES Sequencing Mapping from the OP-code of an instruction to the address of the Microinstruction which is the starting microinstruction of its execution microprogram Machine Instruction Mapping bits Microinstruction address OP-code Address 0 x x x x Mapping function implemented by ROM or PLA OP-code Mapping memory (ROM or PLA) Control address register Control Memory
9 MICROPROGRAM Computer Configuration 9 EXAMPLE Microprogram MX 10 0 AR 10 0 PC Address Memory 2048 x 16 MX 6 0 SBR 6 0 CAR 15 0 DR Control memory 128 x 20 Control unit Arithmetic logic and shift unit 15 0 AC
10 10 MACHINE INSTRCTION FORMAT Microprogram Machine instruction format I Opcode Address 0 Sample machine instructions Symbol OP-code Description ADD 0000 AC AC + M[EA] BRANCH 0001 if (AC < 0) then (PC EA) STORE 0010 M[EA] AC EXCHANGE 0011 AC M[EA], M[EA] AC EA is the effective address Microinstruction Format F1 F2 F3 CD BR AD F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field
11 11 Microprogram MICROINSTRCTION FIELD DESCRIPTIONS - F1,F2,F3 F1 Microoperation Symbol 000 None NOP 001 AC AC + DR ADD 010 AC 0 CLRAC 011 AC AC + 1 INCAC 100 AC DR DRTAC 101 AR DR(0-10) DRTAR 110 AR PC PCTAR 111 M[AR] DR WRITE F2 Microoperation Symbol 000 None NOP 001 AC AC - DR SB 010 AC AC DR OR 011 AC AC DR AND 100 DR M[AR] READ 101 DR AC ACTDR 110 DR DR + 1 INCDR 111 DR(0-10) PC PCTDR F3 Microoperation Symbol 000 None NOP 001 AC AC DR XOR 010 AC AC COM 011 AC shl AC SHL 100 AC shr AC SHR 101 PC PC + 1 INCPC 110 PC AR ARTPC 111 Reserved
12 12 Microprogram MICROINSTRCTION FIELD DESCRIPTIONS - CD, BR CD Condition Symbol Comments 00 Always = 1 nconditional branch 01 DR(15) I Indirect address bit 10 AC(15) S Sign bit of AC 11 AC = 0 Z Zero value in AC BR Symbol Function 00 CAR AD if condition = 1 CAR CAR + 1 if condition = 0 01 CALL CAR AD, SBR CAR + 1 if condition = 1 CAR CAR + 1 if condition = 0 10 RET CAR SBR (Return from subroutine) 11 MAP CAR(2-5) DR(11-14), CAR(0,1,6) 0
13 13 SYMBOLIC MICROINSTRCTIONS Microprogram Symbols are used in microinstructions as in assembly language A symbolic microprogram can be translated into its binary equivalent by a microprogram assembler. Sample Format five fields: Label: label; micro-ops; CD; BR; AD may be empty or may specify a symbolic address terminated with a colon Micro-ops: consists of one, two, or three symbols separated by commas CD: one of {, I, S, Z}, where : nconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR: AD: one of {, CALL, RET, MAP} one of {Symbolic address, NEXT, empty}
14 14 Microprogram SYMBOLIC MICROPROGRAM - FETCH ROTINE During FETCH, Read an instruction from memory and decode the instruction and update PC Sequence of microoperations in the fetch cycle: AR PC DR M[AR], PC PC + 1 AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0 Symbolic microprogram for the fetch cycle: FETCH: ORG 64 PCTAR READ, INCPC DRTAR NEXT NEXT MAP Binary equivalents translated by an assembler Binary address F1 F2 F3 CD BR AD
15 15 SYMBOLIC MICROPROGRAM Microprogram Control Storage: bit words The first 64 words: Routines for the 16 machine instructions (as 4 bits in op code field) The last 64 words: sed for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, the first address for the 16 routines are 0( ), 4( ), 8, 12, 16, 20,..., 60 Partial Symbolic Microprogram Label Microops CD BR AD ADD: ORG 0 NOP READ ADD I CALL INDRCT NEXT FETCH BRANCH: OVER: ORG 4 NOP NOP NOP ARTPC S I CALL OVER FETCH INDRCT FETCH STORE: EXCHANGE: FETCH: INDRCT: ORG 8 NOP ACTDR WRITE ORG 12 NOP READ ACTDR, DRTAC WRITE ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR I I CALL CALL MAP RET INDRCT NEXT FETCH INDRCT NEXT NEXT FETCH NEXT NEXT NEXT INDRCT: when I=1, say, for ADD at 0 address, and to get Effective Address of data a branch to INDRCT (a subroutine) occurs and SBR return address ( 1 in this case). RET from subroutine INDRCT CAR SBR
16 16 BINARY MICROPROGRAM Microprogram Address Binary Microinstruction Micro Routine Decimal Binary F1 F2 F3 CD BR AD ADD BRANCH STORE EXCHANGE FETCH INDRCT This microprogram can be implemented using ROM
17 PCTAR DRTAR Microprogrammed Control 17 DESIGN OF CONTROL NIT - DECODING MICROOPERATIONAL FIELDS- Design of Control nit F1 microoperation fields F2 F3 3 x 8 decoder DRTAC ADD From PC 3 x 8 decoder From DR(0-10) AND Load 3 x 8 decoder Arithmetic logic and shift unit AC AC DR Few functions are shown as outputs of 3 decoders Note: Instead of using gates to generate control signals for ADD, AND, and DRTAC these will become now outputs of MX Select 0 1 Multiplexers Load AR Clock
18 S 1 S 0 Address Source 00 CAR + 1, In-Line 01 SBR RETRN 10 CS(AD), Branch or CALL 11 MAP 18 MICROPROGRAM SEQENCER - NEXT MICROINSTRCTION ADDRESS LOGIC - Address source selection External (MAP) S S 1 0 Branch, CALL Address MX1 RETRN form Subroutine In-Line SBR Incrementer L Subroutine CALL Design of Control nit Clock CAR Control Storage MX-1 selects an address from one of four sources and routes it into a CAR - In-Line Sequencing CAR Branch, Subroutine Call CS(AD) - Return from Subroutine Output of SBR - New Machine instruction MAP
19 19 MICROPROGRAM SEQENCER - CONDITION AND BRANCH CONTROL - Design of Control nit From CP 1 I S Z MX2 Select Test BR field of CS T I 0 I 1 Input logic L L(load SBR with PC) for subroutine Call S 0 for next address S 1 selection CD Field of CS Input Logic I 0 I 1 T Meaning Source of Address S 1 S 0 L 000 In-Line CAR CS(AD) In-Line CAR CALL CS(AD) and SBR <- CAR x RET SBR x MAP DR(11-14) 11 0 S 0 = I 0 S 1 = I 0 I 1 + I 0 T L = I 0 I 1 T
20 20 Design of Control nit MICROPROGRAM SEQENCER External (MAP) I I 0 T Input logic L S 1 1 S 0 MX1 SBR Load 1 I SZ MX2 Test Incrementer Select Clock CAR Control memory Microops CD BR AD......
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1 MICROPROGRAMMED CONTROL Control Memory Sequencing Microinstructions Microprogram Example Design of Control nit Microinstruction Format Nanostorage and Nanoprogram 2 Implementation of Control nit COMPARISON
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1 MICROPROGRAMMED CONTROL Control Memory Sequencing Microinstructions Microprogram Example Design of Control nit Microinstruction Format Nanostorage and Nanoprogram External input (IR) Next address generator
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