EDA-BASED DESIGN PRACTICAL LABORATORY SESSION No. 3

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1 LABORATOIRE DE SYSTEMES MICROELECTRONIQUES EPFL STI IMM LSM ELD Station nº 11 CH-1015 Lausanne Téléphone : Fax : Site web : lsm@epfl.ch lsm.epfl.ch EDA-BASED DESIGN TP-2005/2006: EDABD2005-TP03.doc v1.4 LSM November 2005 EDA-BASED DESIGN PRACTICAL LABORATORY SESSION No. 3 First Name Family Name Date Evaluation Document Visa Evaluation Design Visa THIS REPORT MUST BE DELIVERED NO LATER THAN November 8 th, OBJECTIVES The goal of this session is to learn how to use the DRC (Design Rules Checking) tool, the LVS (Layout Versus Schematic) tool and to use the analog simulator for the extracted circuit simulation. You will first practice with a copied faulty cell which is a bad implementation of your last week s TP. Then you will correct the errors of the NAND2 gate you have designed last week PREREQUISITES Start the Cadence Design Environment under your existing project directory (as described in laboratory session no.1, section 1.3). Copy the faulty cell called NAND2_FAULTY from EDATP library to TP01 library (as described in laboratory session no.1, section 1.4). Open the layout view of the NAND2_FAULTY cell by double clicking the layout view in the library manager. 1/19

2 2. RUNNING ASSURA DRC In this section you will learn how to check a layout for Design Rules. Design rules define the physical limits of a processing technology and are specific to the process you are using. You can find the design rules for AMS 0.35um process in the manual that has been distributed to you. Run Assura DRC Select the Run DRC command in the Assura menu (Fig. 1). Click the Set switches button (Fig. 2). Select the following options by pressing the CTRL key: [grids], [no_antenna], [no_coverage], [no_erc], [no_generated_layers] (Fig. 3). Then click OK. Click OK in the Run Assura DRC window; this will start the DRC process. Click Yes on the Notification window to view the results of the DRC run (Fig. 4). Figure 1: Run DRC command in Assura menu. 2/19

3 Figure 2: DRC setup window (Run Assura DRC window). Figure 3: Set switches options. Figure 4: Notification window. 3/19

4 Visualize the layout errors After clicking OK the Error Layer Window (ELW) will pop-up (because of design rule violations in the layout). In ELW you can see different design rule violations in the layout (Fig. 5). By clicking the [ ] and [ ] arrows, you can move between different types of errors. By clicking the [ ] and [ ] arrows, you can select the same kind of error in different places. The errors are displayed and emphasized in the layout view. Figure 5: Error Layer Window. Correct the layout errors Go to and examine the first error in the layout window using the arrows. This error is caused by insufficient coverage of the diffusion area by pplus region. Go to the other end of the region where the coverage is sufficient. While you are viewing the left side of the region, measure the distance from the pplus region to the diffusion region. For measuring the distance in the layout view, use the ruler tool, which you can access through Window/Create Ruler (Fig. 6). The value you have just measured does not violate the design rules so it can be used to correct the error on the other side. Q1. From the design rules manual find the design rule identifier (such as M1.S1) for the first error and write it in the box below. 4/19

5 Figures 6, 7: Using the ruler and stretch tools. After measuring the distance, using the stretch tool (Edit/Stretch) stretch the pplus region to cover the diffusion region (Fig. 7) Go to and correct the other errors by moving the pieces (Edit/Move command (Fig. 8)) or changing the widths of lines using the stretch tool. If you are moving some pieces, please also remember to move the pins and labels attached to those pieces. Figure 8: Move. 5/19

6 After correcting the errors run DRC again. If you were able to correct all the errors, you should get a notification window telling you have no DRC errors (Fig. 9). If you still see some errors examine and correct the errors until you remove all of them. Figure 9: DRC notification s window. 3. LAYOUT VERSUS SCHEMATIC (LVS) In this section you will learn how to run Assura LVS on the NAND2_FAULTY cell to verify that the layout fits to the schematic. Open the NAND2_FAULTY layout by double clicking the layout view on the library manager. Run a LVS Select Run LVS... on the Assura menu. Verify the field of the Run Assura LVS window (Fig. 10). Click [OK]. A Progress window is opened (Fig. 11). If you want to see the details of the LVS run, you can click the [Watch Log File] button. After some time, the NAND2_FAULTY has completed successfully! window is opened. Click [Yes] to enter the LVS debug environment (Fig. 12). 6/19

7 Figure 10: "Run Assura LVS" menu. Figure 11: "Progress" window. 7/19

8 Figure 12: LVS notification s window. Display the LVS errors. On the LVS Debug window, click on NAND2_FAULTY{TP01} NAND2_FAULTY{TP01} to display the summary of the LVS errors. Double click on Nets 1 error. (Fig. 13) A schematic window and a Nets Mismatch Tool window are opened. Select avc8, avc6 and click [Zoom] to emphasize the errors with a zoom ([Probe] emphasizes the errors without zooming). (Fig. 14) A Selection List window is opened. Select the net you want to display and click [OK]. (Fig. 15) On the Virtuoso Layout Editing window, the Net with an error is emphasized (outline with a different color). (Fig. 16) Correct all the connection errors (see laboratory session no.2, section 5). Run the LVS again (as described above) until all the errors are removed. The LVS Debug window should show a result like as in Fig. 17 if the circuit is LVS clean. 8/19

9 Figure 13: LVS debug window. Figure 14: Nets Mismatch window. Figure 15: Selection list window. 9/19

10 Figure 16: Layout window with LVS error emphasized. Figure 17: LVS clean window. 10/19

11 4. RUNNING ASSURA RCX In this section you will learn how to run Assura RCX for creating an extracted view of the layout. The extracted view of a layout consists of parasitic and wiring capacitances and resistances (if selected) in addition to the elements in the schematic view. The extracted view will later be used for post-layout simulation. Run Assura RCX Run Assura RCX from the menu Assura/Run RCX. After running the command you will see the RCX configuration window (Fig. 18). Make sure the View is av_extracted. On the configuration window select the Extraction tab and set the Ref Node value to VSS (Fig. 19). After you have made the change click OK and run the extraction. Figures 18, 19: RCX Run Form and Extraction Options. After the extraction has finished successfully, in the Library Manager under the NAND2_FAULTY cell, double click the av_extracted view to view the extraction results. You should see a result like shown in Fig. 20. Examine this view and make sure that the extra capacitances that were not in the layout view are correctly extracted. 11/19

12 Figure 20: Extracted View. 5. POST LAYOUT SIMULATION Throughout this section you will learn how to run a post layout simulation from the extracted netlist. You will compare the extracted simulation results with the schematic simulation results PREREQUISITES Open the NAND2_tb schematic from last week TP by double clicking the schematic view on the library manager. Change the name of the NAND2 cell to NAND2_FAULTY. Select the NAND2 symbol by click on it in the schematic view. In the Edit menu, select Properties then Objects... (Fig. 21). In the Edit Objects Properties window, change Cell Name field to NAND2_FAULTY (Fig. 22) Then click OK. 12/19

13 Figure 21: "Edit/Properties/Objects..." menu. Figure 22: "Edit/Properties/Objects..." field. 13/19

14 5.2. DC ANALYSIS Open the simulation environment (as described in laboratory session no.2, section 4). Load the DC simulation setup that you have saved on last week TP (session no.2, section 4.2). In Session menu, select Load State... In the Loading State window, select dc_a in State Name. Click OK. Select the extracted netlist to be simulated. In Setup menu, select Environment... In the Switch View List field, add av_extracted at the beginning of the list (Fig. 23) Click OK. Figure 23: "Environment Options field. 14/19

15 Generate a netlist and visualize the layout capacitance. In Session menu, select Simulation/Netlist/Create. The netlist will appear on a pop-up window. Make sure that the parasitic and interconnect capacitances are in the netlist. Q2. What is the order of magnitude of the parasitic and interconnect capacitances? Give a range. Run the extracted simulation Select the schematic netlist to be simulated In Setup menu, select Environment In the Switch View List field, remove av_extracted from the beginning of the list Click OK. Run the schematic simulation. Q3. Compare and comment extracted and schematic simulation results. Why are there no significant differences between two results? 15/19

16 5.3. TRANSIENT ANALYSIS Load the transient simulation setup that you have saved during last week s TP (session no.2, section 4.2). In Session menu, select Load State... In the Loading State window, select tran in State Name. Click OK. Re-select the extracted netlist to be simulated In Setup menu, select Environment... In the Switch View List field, add av_extracted at the beginning of the list (Fig. 23). Click OK. Run the extracted simulation Q4. Fill in the table with your measurement results. Report your measurement results from last week s TP also (schematic simulation: session no.2, section 4.2, Q4.) A B Z Gate Delay [ps] Extracted simulation Schematic simulation Table. 1. Possible gate transitions of a NAND2 gate. 16/19

17 Q5. Explain the differences between the schematic and extracted simulation results. Evaluate the current consumption of the extracted cell Select Tools/Calculator... in the Analog Design Environment window. Click [it] button in the Calculator window. Click on the VDD pin in the NAND2_tb schematic view. Select average on Special Functions in the Calculator window. Click on [abs] button in the Calculator window. (Fig. 24). Select Output/Setup... in the Analog Design Environment window. Click on Get Expression (Fig. 25) Click OK. 17/19

18 Figure 24: Expression for the current consumption evaluated in the calculator window. Figure 25: Saving a measurement as an output. Run the extracted simulation, report the simulated average current consumption of the cell in table 2. Run the schematic simulation, report the simulated average current consumption of the cell in table 2. Q6. Report the current consumption from extracted and schematic simulation. Average current consumption I_tot Extracted simulation Schematic simulation Table. 2. Average current consumption. Q7. Explain the differences. 6. VERIFY YOUR NAND2 GATE Perform DRC, LVS and extraction on the NAND2 cell you designed on last week s TP. Run the transient simulations again using the testbench by changing the reference NAND2 cell and fill in the timing and average current consumption data in Tables 3 and 4, respectively. 18/19

19 A B Z Gate Delay [ps] Extracted simulation Schematic simulation Table. 3. Possible gate transitions of a NAND2 gate. Average current consumption I_tot Extracted simulation Schematic simulation Table. 4. Average current consumption. Do NOT forget to answer the questions and return this document to the assistants in your room at the end of the session. 19/19