Designing with Nios II Processor for Hardware Engineers
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1 Designing with Nios II Processor for Hardware Engineers Course Description This course provides all theoretical and practical know-how to design ALTERA SoC FPGAs based on the Nios II soft processor under Quartus II software. The course combines 50% theory and 50% practical work on Terrasic DE series evaluation boards. The course starts with Nios II processor system hardware development, Nios II soft core capabilities, and continues with deep methodic training of the Nios II architecture. The course teaches the Nios II architecture and its memory, peripherals, how to manage SoC system, how to configure system based on Nios II, how to transfer data through the Bus system and internal interconnect, how to connect external memories, how to build a system with Qsys, how to handle interrupts, how to develop software and ways for debugging. The second part of the course focuses on appending custom instruction and custom components to enhance performance, use of simulation models (BFMs), and creating SoC test-benches. The course ends with multi-nios II systems (multicore) design, the design considerations, and how to debug multiple processors at the same time. Course Duration 2 days
2 Goals 1. Become familiar with ALTERA Nios II processor, its capabilities and when to use it 2. Understand SoC design hardware and software flow from specification to programming and final verification on the board 3. Develop software for Nios II processor 4. Integrate custom components into the SoC design 5. Integrate custom instructions to a Nios II processor 6. Configure the SoC system (clocks, PLLs, Resets, cache, TCM, on-chip memory, offchip memory, MMU/MPU, Peripherals) 7. Use Bus Functional Models (BFMs) to simulate SoC behavior 8. Use system console to debug hardware 9. Handle Interrupts using the Nios II internal or external interrupt controller 10. Design multi-nios II processor systems Intended Users Hardware and system engineers who would like to design with ALTERA Nios II soft processor Previous Knowledge Quartus II software and Qsys SignalTap Embedded Logic Analyzer ModelSim Course Material 1. Simulator: Modelsim 2. Synthesizer and Place & Route: Quartus II 3. Terrasic Cyclone V GX Evaluation board 4. Course book (including labs)
3 Table of Contents Day #1 Nios II Processor-Based Systems o What is System On a Programmable Chip (SOPC)? o What is Nios II processor? o Typical system architecture o Nios II processor major features o Requirements for Nios II processor designs o Nios II processor block diagram o Licensing o Qsys automatic interconnect generation o Add and configure Nios II CPU in Qsys o Nios II Gen 2 processor changes and improvements o Nios II processor versions and performance comparison o Vector tab settings o Caches and memory interfaces tab o Nios II Gen 2 uncached peripheral region feature o Tightly coupled memory o Arithmetic instructions tab o Nios II multiplier/divider/shifter performance o MMU and MPU settings tab o JTAG debug tab o Advanced features tab o Internal interrupt controller o Vectored interrupt controller (VIC) o Shadow registers o Using bridges with a system o Migrate from Nios II classic to Nios II Gen2 processor Lab #1: Creating a Nios II Processor System Using Qsys Software Development and Debug Tools o Nios II processor system design flow o Nios II software design process o Nios II Embedded Design Suite (EDS)
4 o Nios II software build tools o Creating new software projects o Application and BSP projects o Application and BSP from template o Create BSP project by itself o Create application project by itself o Importing projects into Workspace o Creating a new source file in GUI o Importing source files to a project o Creating linked resources o Setting project properties o Application project properties o Setting compiler flags (App and BSP) o Add libraries to application project o BSP project properties o BSP editor o Build properties for individual files o Project directory structure o.elf and system.h output files o Program target hardware o Running code on a target o Run configurations window o System ID peripheral check o Nios II debugger o Nios II debug perspective o Debug windows o Breakpoints o Watchpoints o Nios II instruction set simulator System Verification with System Console o What is system console? o Usage examples o System console operation requirements o System console interfaces o System console GUI o Command line interface o GUI interactive usage tips o System console services
5 o System console usage flow o Master service type o Dashboards o Widgets o Other system console uses Lab #2: Build a Software Project for the Nios II Processor Day #2 RTL Simulation with the Nios II Processor o RTL simulation for a Qsys system o Enable testbench generation o Qsys testbench output files o Building for an RTL simulation o Running an RTL simulation o msim_setup.tcl simulation script o Component simulation options Custom Components o What are custom components? o Example signal mapping o Component editor GUI o hw.tcl file o Custom component integration into Qsys system o Edit component parameters Nios II Processor Custom Instructions o What are custom instructions? o Block diagram of a system with custom instructions o Custom instructions support in Nios II development tools o Create custom instructions in Qsys o Add custom instruction to system o C language software interface o Assembly language interface o Why custom instructions?
6 o Floating point custom instructions o Floating point CI macros o Nios II custom instruction user guide o Custom instruction vs. custom component o Multi-cycle custom instructions o Accelerating CRC example Working with Development Boards o Ensure unused I/O are tri-state o Flash memory configuration o Hardware configuration from Flash o Boot copier o Nios II Flash Programmer o Extra features o What if you have a custom board? o What if Facory Safe Flash Image overwritten? o Booting from the MAX 10 device on-chip Flash LAB #3: Custom Components and Custom Instructions Application Examples for the Nios II Processor o Component tradeoff o State machine replacement o Custom microcontroller o General purpose system controller o I/O processing controller o Off-loading existing CPU o Build multi-processor systems o Multi-CPU architectures o Shared memory, mutex, and mailboxes o Software for multi-processor systems o Launch group for multi-processor systems o Sending interrupts o Control plane and data plane LAB #4: Build and Explore a Multi-Nios II CPU System
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