Speicherarchitektur. Who Cares About the Memory Hierarchy? Technologie-Trends. Speicher-Hierarchie. Referenz-Lokalität. Caches

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1 11 Speicherarchitektur Speicher-Hierarchie Referenz-Lokalität Caches 1 Technologie-Trends Kapazitäts- Geschwindigkeitssteigerung Logik 2 fach in 3 Jahren 2 fach in 3 Jahren DRAM 4 fach in 3 Jahren 1.4 fach in 10 Jahren Platte 2 fach in 3 Jahren 1.4 fach in 10 Jahren Rechnerkern Geschwindigkeitslücke Hauptspeicher Who Cares About the Memory Hierarchy? Processor-DRAM Memory Gap (latency) µproc 60%/yr. Performance CPU Processor-Memory Performance Gap: (grows 50% / year) 10 DRAM 9%/yr. DRAM : Speed = ƒ(nr. operations) 1998: Speed = ƒ(non-cached memory accesses) 3 1

2 Speicherhierarchie Die Organisation des Gesamtspeichers : Hierarchie von Speicherebenen Diese enthält Speicher unterschiedlicher Größe und unterschiedlicher Zugriffsgeschwindigkeit Register Caches Hauptspeicher Virtueller Speicher Massenspeicher Speicherverwaltung notwendig 4 Memory Hierarchy Technology Random Access: Random : access time is the same for all locations DRAM: Dynamic Random Access Memory High density, low power, cheap, slow Dynamic: needs to be refreshed regularly SRAM: Static Random Access Memory Low density, high power, expensive, fast Static: content last forever (until lose power) 5 Memory Hierarchy Processor Control Data path Regs L1 $ L2 Cache Main Memory Secondary Memory Speed(ns): 0.5ns 2ns 6ns 100n 10,000,000ns Size (MB): ,000 Cost ($/MB): -- $100 $30 $1 $0.05 Technology: Regs SRAM DRAM Disk 6 2

3 Why Hierarchy works: Locality The Principle of Locality: Program access a relatively small portion of the address space at any instant of time. Probability of reference Address Space What programming constructs lead to Principle of Locality? 7 Locality Block is the unit of transfer (like a book) Spatial Locality (Locality in Space): Move blocks consisting of contiguous words to the faster levels - that is, closer to the processor. Library Analogy: Bring back nearby books on shelves when fetch a book; hope that you might need it later for your paper 8 Locality Temporal Locality (Locality in Time): Keep most recently accessed data items closer to the processor Library Analogy: Recently read books are kept on desk 9 3

4 Memory Hierarchy: Terminology Hit: data appears in some block in the upper level Hit Rate: the fraction of memory access found in the upper level Analogy: fraction of time find book on desk. Miss: data needs to be retrieve from a block in the lower level Miss Rate = 1 - (Hit Rate) Analogy: fraction of time must go to shelves for book 10 Memory Hierarchy: Terminology Hit Time: Time to access the upper level which consists of Time to determine hit/miss + Memory access time Analogy: time to find, pick up book from desk Miss Penalty: Time to replace a block in the upper level + Time to deliver the block the processor Analogy: time to go to shelves, find needed book, and return it to your desk, pick up Note: Hit Time << Miss Penalty 11 Idea Create the illusion of a memory that is large, cheap, and fast - on average Performance Model Minimize: Average Access Time = Hit Time + Miss Penalty x Miss Rate influenced by technology and program behavior 12 4

5 13 Memory Hierarchy and Locality Temporal locality: keep recently accessed data items closer to processor Spatial locality: moving contiguous words in memory to upper levels of hierarchy Uses smaller and faster memory close to the processor Fast hit time in highest level of hierarchy Cheap, slow memory furthest from processor If hit rate is high enough, hierarchy has access time close to the highest (and fastest) level and size equal to the lowest (and largest) level 14 Mittlere Effektive Zugriffszeiten 15 5

6 Mittlere Effektive Zugriffszeiten P[Daten in Stufe i-1] + hi 16 Mittlere Effektive Zugriffszeiten 17 Mittlere Effektive Zugriffszeiten 18 6

7 How is the hierarchy managed? Registers Memory - by compiler (or Assembler Programmer) Cache Main Memory - by the hardware Main Memory Disks - by the hardware and operating system - by the programmer (files) 19 MMU Memory Management Unit: Speicher-Verwaltungseinheit CPU Adressen Adressen virtuell MMU physical. Hauptspeicher Ausnahme 20 Virtual to Physical Address Translation Program operates in its virtual address space virtual address (inst. fetch load, store) HW mapping physical address (inst. fetch load, store) Physical memory (incl. caches) Each program operates in its own virtual address space. Each virtual address space is protected from the other, OS can decide where each goes in memory. Hardware (MMU) provides virtual -> physical mapping 21 7

8 Caches 22 Cache Hierarchy Processor Control Data path Regs L1 $ L2 Cache Main Memory Secondary Memory Speed(ns): 0.5ns 2ns 6ns 100n 10,000,000ns Size (MB): ,000 Cost ($/MB): -- $100 $30 $1 $0.05 Technology: Regs SRAM DRAM Disk 23 Pentium Instr Reg/ALU 16K L1 Instr 16K L1 Data 512 K L2 24 8

9 Cache Organization 25 ARM710T Cache Organisation virtual address byte addresses tag RAM tag RAM tag RAM tag RAM [1:0] [8:2] data RAM [10:0] 128 entry 128 entry 128 entry 128 entry =? =? =? =? [10:9] 2048 x 32-bit word encode hit data 26 Virtual Cache Physical Cache 27 9

10 28 Itanium 29 Itanium 30 10

11 Itanium 31 Cache Verwaltung 32 Classifying Misses: 3 Cs Compulsory The first access to a block is not in the cache, so the block must be brought into the cache. Also called cold start misses or first reference misses. (Misses in even an Infinite Cache) Capacity If the cache cannot contain all the blocks needed during execution of a program, capacity misses will occur due to blocks being discarded and later retrieved. Conflict Conflict misses (in addition to compulsory & capacity misses) will occur because a block can be discarded and later retrieved if too many blocks map to its set. Also called collisions or interference misses

12 Improving Cache Performance Memory accesses CPUtime = IC CPI Execution + Instruction Cache Performance Formula Miss rate Miss penalty Clock cycle time 1. Reduce the miss rate, 2. Reduce the miss penalty, 3. Reduce the time to hit in the cache. Reducing cache misses has been the traditional focus of cache research. 34 Example Assume Hit Time = 1 cycle Miss rate = 5% Miss penalty = 20 cycles Avg mem access time = x 20 = 2 cycle 35 How Can Reduce Misses? 3 Cs: Compulsory, Capacity, Conflict In all cases, assume total cache size not changed. What happens if: 1) Change Block Size: Which of 3Cs is obviously affected? 2) Change Associativity: Which of 3Cs is obviously affected? 3) Change Compiler: Which of 3Cs is obviously affected? 36 12

13 Design Trade-off: Block Size Many small blocks Intermediate number of reasonably sized blocks Few large blocks Which cache will have best miss rate? Fix: cache size = Num blocks x block size 37 Block Size Tradeoff Goal: minimize Average Access Time = Hit Time + Miss Penalty x Miss Rate In general, larger block size to take advantage of spatial locality fewer misses, but, larger miss penalty: Takes longer time to fill up the block If block size is too big relative to cache size, miss rate will go up Too few cache blocks, bad for temporal locality 38 Extreme Example: single big block Only ONE entry in the cache! If item accessed, likely accessed again soon But unlikely will be accessed again immediately! The next access will likely to be a miss again Continually loading data into the cache but discard data (force out) before use it again Nightmare for cache designer: Ping Pong Effect 39 13

14 Reduce Misses via Larger Block Size 25% Miss Rate 20% 15% 10% 5% 1K 4K 16K 64K 256K 0% Block Size (bytes) Block Size Tradeoff Miss Penalty Block Size + Miss Rate Exploits Spatial Locality Block Size Fewer blocks: compromises temporal locality Average Access Time Increased Miss Penalty & Miss Rate Block Size 41 Ways to reduce miss rate Larger cache limited by cost and technology hit time of first level cache < cycle time More places in the cache to put each block of memory - associativity fully-associative any block any line k-way set associated k places for each block direct map: k=

15 Reducing Misses by Compiler Optimizations Instructions Reorder procedures in memory so as to reduce conflict misses Profiling to look at conflicts (using tools they developed) Data Merging Arrays: improve spatial locality by single array of compound elements vs. 2 arrays Loop Interchange: change nesting of loops to access data in order stored in memory Loop Fusion: Combine 2 independent loops that have same looping and some variables overlap Blocking: Improve temporal locality by accessing blocks of data repeatedly vs. going down whole columns or rows 43 15

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