14:332:331. Week 13 Basics of Cache

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1 14:332:331 Computer Architecture and Assembly Language Fall 2003 Week 13 Basics of Cache [Adapted from Dave Patterson s UCB CS152 slides and Mary Jane Irwin s PSU CSE331 slides] 331 Lec20.1 Fall 2003

2 Head s Up This week s material Basics of caches - Reading assignment PH 7.2 Reminders 331 Lec20.2 Fall 2003

3 Review: A Typical Memory Hierarchy By taking advantage of the Principle of Locality: Present the user with as much memory as is available in the cheapest technology at the access speed offered by the fastest technology. On-Chip Components Control edram Datapath RegFile ITLB DTLB Instr Data Cache Cache Second Level Cache (SRAM) Main Memory (DRAM) Secondary Memory (Disk) Speed: 1 ns 2 ns 10 ns 50 ns 1,000 ns Size: 128 B 64 KB 256 KB 4 GB TB s Cost: highest lowest 331 Lec20.3 Fall 2003

4 Review: Principle of Locality Temporal Locality Keep most recently accessed data items closer to the processor Spatial Locality Move blocks consisting contiguous words upper levels Hit Time << Miss Penalty Hit: data appears in some block in the upper level (Blk X) - Hit Rate: the fraction of accesses found in the upper level - Hit Time: Time to access the upper level = RAM access time + Time to determine hit/miss Miss: data needs to be retrieve from a lower level block (Blk Y) - Miss Rate = 1 - (Hit Rate) To Processor From Processor - Miss Penalty: Time to replace a block in the upper level with a block from the lower level + Time to deliver this block to the processor In general, Average Access Time: = Hit Time + Miss Penalty x Miss Rate Upper Level Memory Blk X Lower Level Memory 331 Lec20.4 Fall 2003 Blk Y of to the

5 Review: How is the Hierarchy Managed? registers <-> memory by compiler (programmer?) cache <-> main memory by the hardware main memory <-> disks by the hardware and operating system (virtual memory) by the programmer (files) 331 Lec20.5 Fall 2003

6 Cache Two questions to answer (in hardware): Q1: How do we know if a data item is in the cache? Q2: If it is, how do we find it? First method: Direct mapped - For each item of data at the lower level, there is exactly one location in the cache where it might be (i.e., lots of items at the lower level share locations in the upper level) Block size is one word of data Mapping: (word address) modulo (# of words in the cache) 331 Lec20.6 Fall 2003

7 Caching: A Simple First Example Cache Valid Tag Q1: Is it there? Data Compare the cache tag to the high order 2 memory address bits to tell if the memory block is in the cache Main Memory Q2: How do we find it? Use low order 2 memory address bits to determine which cache block (i.e., modulo the number of blocks in the cache) 331 Lec20.7 Fall 2003

8 Direct Mapped Cache Consider the main memory reference string Start with an empty cache - all blocks marked as not valid miss 1 miss 2 miss 3 miss 00 Mem(0) 00 Mem(0) 00 Mem(1) 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 4 miss Mem(0) 00 Mem(1) 00 Mem(2) 00 Mem(3) 3 hit 4 hit Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) 01 Mem(4) 00 Mem(1) 00 Mem(2) 00 Mem(3) miss 01 Mem(4) 00 Mem(1) Mem(2) Mem(3) 331 Lec20.8 Fall 2003

9 Another Reference String Mapping Now consider the main memory reference string Start with an empty cache - all blocks marked as not valid miss 4 miss 0 miss 4 miss Mem(0) 00 Mem(0) 01 Mem(4) Mem(0) 4 0 miss 4 miss 0 miss 4 miss Mem(4) Mem(0) 01 Mem(4) 00 Mem(0) Ping pong effect due to conflict misses - two memory locations that map into the same cache block 331 Lec20.9 Fall 2003

10 Sources of Cache Misses Compulsory (cold start or process migration, first reference): first access to a block Cold fact of life, not a whole lot you can do about it If you are going to run billions of instruction, Compulsory Misses are insignificant Conflict (collision): Multiple memory locations mapped to the same cache location Solution 1: increase cache size Solution 2: increase associativity Capacity: Cache cannot contain all blocks accessed by the program Solution: increase cache size 331 Lec20.10 Fall 2003

11 MIPS Direct Mapped Cache Example One word/block, cache size = 1K words Byte offset Hit Tag Index Data Index Valid Tag Data Lec20.11 Fall 2003

12 Cache Summary The Principle of Locality: Program likely to access a relatively small portion of the address space at any instant of time - Temporal Locality: Locality in Time - Spatial Locality: Locality in Space Three Major Categories of Cache Misses: Compulsory Misses: sad facts of life. Example: cold start misses Conflict Misses: increase cache size and/or associativity Nightmare Scenario: ping pong effect! Capacity Misses: increase cache size Cache Design Space total size, block size, associativity (replacement policy) write-hit policy (write-through, write-back) write-miss policy (write allocate, write buffers) 331 Lec20.12 Fall 2003

13 Memory Systems that Support Caches The off-chip interconnect and memory architecture can affect overall system performance in dramatic ways. on-chip 32-bit data & 32-bit addr per cycle CPU Cache bus Memory One word wide organization (one word wide bus and one word wide memory) Assume 1. 1 clock cycle (2 ns) to send the address clock cycles (50 ns) for DRAM cycle time, 8 clock cycles (16 ns) access time 3. 1 clock cycle (2ns) to return a word of data Memory-Bus to Cache bandwidth number of bytes accessed from memory and transferred to cache/cpu per clock cycle 331 Lec20.13 Fall 2003

14 One Word Wide Memory Organization on-chip CPU Cache bus Memory If the block size is one word, then for a memory access due to a cache miss, the pipeline will have to stall the number of cycles required to return one data word from memory cycle to send address cycles to read DRAM cycle to return data total clock cycles miss penalty Number of bytes transferred per clock cycle (bandwidth) for a single miss is 4/27 = bytes per clock 331 Lec20.14 Fall 2003

15 One Word Wide Memory Organization, con t What if the block size is four words? on-chip 1 cycle to send 1 st address CPU 4 x 25 = cycles to read DRAM cycles to return last data word Cache 102 total clock cycles miss penalty bus Memory 25 cycles 25 cycles 25 cycles 25 cycles Number of bytes transferred per clock cycle (bandwidth) for a single miss is (4 x 4)/102 = bytes per clock 331 Lec20.15 Fall 2003

16 One Word Wide Memory Organization, con t on-chip CPU Cache What if the block size is four words and if a fast page mode DRAM is used? *8 = cycle to send 1 st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty bus Memory 25 cycles 8 cycles 8 cycles 8 cycles Number of bytes transferred per clock cycle (bandwidth) for a single miss is (4 x 4)/51 = bytes per clock 331 Lec20.16 Fall 2003

17 Interleaved Memory Organization on-chip CPU Cache For a block size of four words 1 cycle to send 1 st address = 28 cycles to read DRAM 1 cycles to return last data word 30 total clock cycles miss penalty bus Memory Memory Memory Memory bank 0 bank 1 bank 2 bank 3 25 cycles 25 cycles 25 cycles 25 cycles Number of bytes transferred per clock cycle (bandwidth) for a single miss is (4 x 4)/30 = bytes per clock 331 Lec20.17 Fall 2003

18 DRAM Memory System Summary Its important to match the cache characteristics caches access one block at a time (usually more than one word) with the DRAM characteristics use DRAMs that support fast multiple word accesses, preferably ones that match the block size of the cache with the memory-bus characteristics make sure the memory-bus can support the DRAM access rates and patterns with the goal of increasing the Memory-Bus to Cache bandwidth 331 Lec20.18 Fall 2003

14:332:331. Week 13 Basics of Cache

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