ChipScope Inserter flow. To see the Chipscope added from XPS flow, please skip to page 21. For ChipScope within Planahead, please skip to page 23.

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1 In this demo, we will be using the Chipscope using three different flows to debug the programmable logic on Zynq. The Chipscope inserter will be set up to trigger on a bus transaction. This bus transaction will be caused in SDK. The three flows are: ChipScope Inserter flow. To see the Chipscope added from XPS flow, please skip to page 21. For ChipScope within Planahead, please skip to page 23. Step 1: Create a simple XPS system using the Base System Builder (BSB): stephenm@xilinx.com Page 1

2 Use the import button in XPS to import the ZC702 SoC settings: Page 2

3 Step 2: Create the Netlist. Hardware -> Device Configuration Step 3: Configure the Chipscope: Open the Chipscope inserter tool: Start -> Al l Programs -> Xilinx Design Suite Tools > Xilinx Design Tools > Chipscope Pro -> Chipscope 64-bit Tools -> Core Inserter Add the top-level netlist found in the implementation folder in the XPS project directory Set the device family to Zynq stephenm@xilinx.com Page 3

4 Under the Trigger Parameters tab, select Trigger Width as 3. This is for demo purposes to make things simple. This can be set to suit the designers debug needs. Page 4

5 Under the Capture Parameters tab, select Data Width as 130. This is for demo purposes to make things simple. This can be set to suit the designers debug needs. Page 5

6 Next, add Clock Signals, Data Signals, and the Trigger Signals. Under Clock Signals, add the processor_system7_0_fclk_clk0 and select Make Connections Page 6

7 Under Trigger Signals, add the axi4lite_0_m_awvalid<0-1> and select Make Connections Page 7

8 Under Data Signals, add the axi4lite_0_s_araddr<0-31>, axi4lite_0_s_awaddr<0-31>, axi4lite_0_s_rdata<0-31>, axi4lite_0_s_wdata<0-31> add the axi4lite_0_m_awvalid<01> and select Make Connections Once this is done, select OK, and Next to add Yes to Proceed with Core Insertion Once this is generated you should see the message: Page 8

9 So now we should have the.ngo file in the implementation folder. Rename the top level.ngc file to system.ngc to system_old.ngc, and rename system.ngo to system.ngc and generate the bitstream: Before closing the Chipscope Inserter, save the CDC file into the implementation folder too Page 9

10 Step 4: Create SDK test application to trigger the Chipscope Export to SDK, Project -> Export Hardware Design to SDK Include the bitstream and BMM and select Export and Launch SDK: Page 10

11 Once SDK is launched, create a new Test Peripheral Application (File -> New -> New Application) Select Next, and select Peripheral Tests and Finish to Exit stephenm@xilinx.com Page 11

12 Generate the Linker script. To do this right click on the application and select Generate Linker. Place all the sections in DDR and select Generate to create the linker script. Next Program the Zynq SoC using the program FPGA GUI in SDK, Xilinx Tools -> Program FPGA: Step 5: Debug the system using the Chipscope Analyser Open the Chipscope analyser tool: Start -> Al l Programs -> Xilinx Design Suite Tools > Xilinx Design Tools > Chipscope Pro -> Chipscope 64-bit Tools -> Analyser Initialise the JTAG Chain by selecting the icon highlighted in red below: stephenm@xilinx.com Page 12

13 Click OK: Check to see if the Chipscope unit was detected in the console: Page 13

14 If this is not the case, go back to step 3 and make sure the unit was added. Next, add the CDC file. In the Analyser, File -> Import and navigate to the.cdc file that was saved into the implementation folder in step 3. Select OK to continue: Set the Trigger from XXX to 100. This will cause a trigger on any of the valid signals: stephenm@xilinx.com Page 14

15 Finally, Arm the Chipscope: Page 15

16 Back in SDK, run the application. To do this right click on the Application -> Run As -> Run Configurations: Page 16

17 Double click on Xilinx C/C++ ELF: Then Run to run the application Page 17

18 The Analyser sample buffer will fill and we can see the transactions on the AXI interface: For further debug signals see the Transaction Timing Example signals for the AXI interface you are using: AXI Master Lite AXI Master Burst AXI Slave Burst Page 18

19 To run the bitstream from the SD card, the bootgen tool in SDK can be used. The BootGen will require an FSBL, so create this in SDK. Next Launch the BootGen, Xilinx Tools -> Create Zynq Boot Image: Set up as follows: Rename the resulting bin file in the bootimage folder to BOOT.bin and copy this onto the SD card Page 19

20 Set MODE pins on the ZC702 to boot from the SD CARD: Place the SD card into the SDIO slot on the ZC702 and power on the board. To test, open a hyperterminal, and set the BAUD rate to Press the SRST_B button on the ZC702 (located beside the SDIO). The Test Peripheral should be seen on the serial port: Re-do step 5 to see this in chipscope stephenm@xilinx.com Page 20

21 In this section, the Chipscope will be added using the Debug -> Debug Configuration GUI in XPS: We shall add an ILA: Choose the signals which you wish to monitor, and OK to exit. Page 21

22 Now in XPS, Export to SDK, Project -> Export to SDK. In SDK, create a Test Peripheral application. See page 11 for help here. Once this is created, programme the FPGA. See page 12 for help here. Now Open the Chipscope Analyser. See 13 for help here. If added correctly, you will see the Found 1 Core Unit message in the console: stephenm@xilinx.com Page 22

23 In this flow we will add the Chipscope directly onto the nets in Planahead. To do this create a simple Planahead project, with a XPS (with Zynq ) as a submodule and create a top level wrapper. Next open the synthesized Design: stephenm@xilinx.com Page 23

24 In the Synthesized Design open the system ->nets and choose the same signals as seen in page 5 ->8 Note: to capture the signal, right click and select Mark Debug Select OK: Once this is done the nets will look like: stephenm@xilinx.com Page 24

25 Next, set up the Chipscope: Next.. Page 25

26 Next, select the trigger. Here, I have the AWVALID set to Trig only, and the reset as Data only. To do this highlight the signal you want to change, and set it as appropriate, as shown below: Note: To see the clock, right click on any net and select, Select Clock Domain Select Next, and Finish to continue. stephenm@xilinx.com Page 26

27 Next Generate the Bitstream: Save: Page 27

28 Next, Launch ChipScope Analyser: Page 28

29 Next, Configure the JTAG chain: Next configure the FPGA. To do this right click on the XC7C702: Page 29

30 Select OK to continue: Page 30

31 Next, Import the CDC file. File -> Import, and select Select New : The CDC file should be in.\project_1\project_1.runs\impl_1 stephenm@xilinx.com Page 31

32 Next, set up the trigger condition, and arm the ChipScope: Finally, follow the steps on page to test the application Page 32

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