DSP Design Flow User Guide

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1 DSP Design Flow User Guide 101 Innovation Drive San Jose, CA Software Version: 8.0 Document Date: May 2008

2 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. UG ii Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

3 Contents Chapter 1. Introduction The Advanced Blockset Key Features and Differences When to Use the Advanced Blockset When to Use the Standard Blockset When to Combine the Advanced and Standard Blocksets Chapter 2. Installation System Requirements Obtain & Install DSP Builder Download DSP Builder Install DSP Builder DSP Builder Directory Structure Using Previous Versions of DSP Builder Upgrading From the Previous Release MATLAB Issues Using Multiple Versions of MATLAB MATLAB R2007a on 64-bit Windows Directory Path Names in MATLAB Scripts Graphics Not Displayed on Example Design HTML Pages Setting Up Licensing Appending the License to Your license.dat File Specifying the License File Location Chapter 3. Interoperability DSP Builder Interoperability A Simple Example Using Hardware in the Loop rd Party Interoperability Simulink ModelSim Quartus II SOPC Builder Archiving Designs Appendix A. Example Design Functional Description... A 1 Walkthrough... A 3 Altera Corporation Software Version 8.0 i May 2008 DSP Design Flow User Guide Software User Guide

4 Contents Additional Information Revision History... Info i How to Contact Altera... Info i Typographic Conventions... Info i ii Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

5 1. Introduction This user guide introduces the DSP Builder Advanced Blockset, including the key differences between the DSP Builder standard and advanced blocksets with advice about when to use each blockset. It also provides information about interoperability between the blocksets and with other tools. The Advanced Blockset The DSP Builder Advanced Blockset consists of a number of Simulink libraries that allow you to implement DSP designs quickly and easily. The blockset is based on a high level synthesis technology that optimizes the high level, untimed netlist into low level, pipelined hardware targeted to your chosen FPGA device and chosen clock rate. The hardware is written out as plain text VHDL, along with scripts that integrate with the Quartus II software and the ModelSim simulator. The combinations of these features allows you to create a design without needing intimate device knowledge, and then generate a high quality implementation that runs on a variety of FPGA families with different hardware architectures. By specifying your desired clock frequency you can solve timing closure issues by generating RTL that is pipelined to meet your goal. Filters within the blockset automatically use a high clock rate to increase folding, and reduce hardware size. Example designs are provided as a starting point and to illustrate the design possibilities. Key Features and Differences The DSP Builder standard and advanced blocksets are useful in different circumstances and should normally be used independently. When to Use the Advanced Blockset If you have a streaming algorithm characterized by continuous data streams and occasional control then the Advanced blockset is ideal. Examples of this type of design are found in RF cards, where chains of filters are used. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

6 Key Features and Differences If you want to port your design to different device families, or perform various high level resource trade-offs such as hard versus soft multipliers then the advanced blockset is also a good choice. For information about how you can control these trade-offs, refer to the Control Block section in the DSP Builder Advanced Blockset User Guide. If you want to create designs running at very high clock frequencies, then the advance blockset can help by performing just the right amount of pipelining to meet your timing goal. The advanced blockset is split into two main libraries - ModelIP and ModelPrim. These are useful in the following circumstances: ModelIP: The ModelIP library consists of a set of multichannel, multirate filters, mixers and a numerically controlled oscillator (NCO) that allow you to quickly create designs for digital front end applications. Several implementation examples including up and down converters are provided. ModelPrim: The ModelPrim library allows you to create fast efficient designs captured in the behavioral domain rather than the implementation domain. For example, you can use a delay block and let the tool decide how to implement that delay. When to Use the Standard Blockset If you care about exact cycle-accurate behavior, then you should use the standard blockset. The standard blockset is more suitable for managing multiple clock domains for example, when interfacing to external logic. If you are very familiar with the device architecture and want to access certain detailed device features then this would also be a good choice. If your design is very control rich with many state machines then use the standard blockset. When to Combine the Advanced and Standard Blocksets There may be parts of your design that are typical of both design styles. If this is the case, then you can use both blocksets in subsystems of the same overall design. f For more information about the advanced blockset, refer to the DSP Builder Advanced Blockset Reference Manual and the DSP Builder Advanced Blockset User Guide. For more information about the standard blockset, refer to the DSP Builder Reference Manual and the DSP Builder User Guide. 1 2 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

7 2. Installation System Requirements f DSP Builder is integrated with the MATLAB/Simulink tools from The MathWorks and with the Altera Quartus II software which must be available on your workstation before you install DSP Builder. For full system requirements, refer to the Quartus II Installation & Licensing for Windows manual on the Altera Literature website at: 1 DSP Builder is not currently available for UNIX or Linux workstations. Table 2 1 lists the tool dependencies for the v8.0, v7.2, and v7.1 releases. Table 2 1. DSP Builder Tool Dependencies Software Versions DSP Builder , 7.2 SP1, 7.2 SP2, or 7.2 SP3 Quartus II , 7.2 SP1, 7.2 SP2, or 7.2 SP3 The MathWorks (MATLAB/Simulink) Note (1), Note (2), Note (3) R2006a, R2006b, R2007a, R2007b, or R2008a R14 SP3, R2006a, R2006b, or R2007a 7.1 or 7.1 SP1 7.1or 7.1 SP1 R14 SP3, R2006a, R2006b, or R2007a ModelSim 6.1d to 6.1g 6.1d to 6.1g 6.1d to 6.1g Notes to Table 2 1: (1) Only 32-bit versions of The MathWorks release are currently supported. (2) DSP Builder does not work with MATLAB in read only mode. If error messages are issued while creating board components during the DSP Builder installation, re-install MATLAB with the READ ONLY option unchecked. (3) The DSP Builder Advanced blockset uses Simulink fixed-point types for all operations and requires licensed versions of the Simulink Fixed Point blockset and Fixed-Point Toolbox. The Signal Processing Blockset and Communications Blockset are also recommended and are used in the demonstration designs. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

8 Obtain & Install DSP Builder Obtain & Install DSP Builder Before you can use DSP Builder, you must obtain the files and install them on your computer. DSP Builder can be installed from the Quartus II, 8.0 DVD, or downloaded from the Altera web site. 1 The following instructions describe downloading and installing DSP Builder. If you already have installed DSP Builder from the DVD, skip to DSP Builder Directory Structure on page 2 3. Download DSP Builder If you have Internet access, you can download DSP Builder from Altera s web site at Follow the instructions below to obtain DSP Builder from the Internet. If you do not have Internet access, contact your local Altera representative to obtain the Quartus II version 8.0 DVD. 1. Point your web browser to 2. Click on DSP Builder and then the link to Download DSP Builder. 3. Fill out the registration form and click Submit Request. 4. Read the Altera license agreement. Turn on the I have read the license agreement check box and click Proceed to Final Step. 5. Follow the instructions on the download and installation page to download the executable and save it to your hard disk. Install DSP Builder 1 The MATLAB, Simulink and Quartus II software must be installed before you install DSP Builder. Follow these steps to install DSP Builder on a computer running a supported version of the Windows operating system: 1. Close the following software if it is running on your computer: The Quartus II software The MATLAB and Simulink tools The ModelSim simulator 2. Choose Run (Windows Start menu). 3. Type <path>\dspbuilder-v8.0.exe, where <path> is the location of the downloaded file. 2 2 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

9 Installation 4. Click OK. The DSP Builder v8.0 - InstallShield Wizard dialog box appears. 5. Follow the on-line instructions to install a new copy of the product. Note that you are prompted for the locations of the Quartus II and MATLAB software you want to use with DSP Builder. You can also choose whether to install the standard, advanced or both blocksets. 1 MATLAB is invoked in a minimized window during the install. The transcript may include a number of entity creation error messages but these can be ignored and all components should be correctly initialized. DSP Builder Directory Structure The DSP Builder installation program copies files into the directories shown in Figure 2 1 where <path> is the installation directory which contains the Quartus II software. The default installation directory on Windows is c:\altera\80\quartus. Figure 2 1. DSP Builder Directory Structure <path> Installation directory containg the Quartus II software. dsp_builder Contains the DSP Builder standard toolset. bin Contains binary files, m-scripts and the Simulink Library for the standard blockset. DesignExamples Contains a wide variety of demonstration designs that use the standard blockset. docs Contains documentation, including PDF manuals and the on-line help files for each standard block that are displayed in the MATLAB Help window. func_sim Contains files for fast functional simulation. legacy Contains files required for upgrading legacy designs. lib Contains library files. dspba Contains the DSP Builder advanced toolset. Blocksets Contains binary files, m-scripts and the Simulink Library for the advanced blockset. Docs Contains documentation, including PDF manuals and the on-line help files for each advanced block that are displayed in the MATLAB Help window. Examples Contains a wide variety of demonstration designs that use the advanced blockset. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

10 Upgrading From the Previous Release After installing DSP Builder, the Altera DSP Builder Blockset and/or the Altera DSP Builder Advanced Blockset libraries are available in the Simulink library browser in the MATLAB software. Using Previous Versions of DSP Builder The DSP Builder install program searches for an existing installation of DSP Builder before it installs a new version. If an existing installation is found, the program prompts you to update the existing installation or install a new copy of the product. If you choose to update an existing product, you can modify, repair or remove the old version. 1 Do not attempt to modify or repair a previous version of DSP Builder using the v8.0 install program. These products can only be modified using a corresponding installer. Previous Versions A previous version of DSP Builder cannot co-exist with v8.0 in the same version of MATLAB. However, you can register each version of DSP Builder with different versions of MATLAB as described in Using Multiple Versions of MATLAB on page 2 5 section. 1 DSP Builder must be used with a matching version of the Quartus II software. Ensure that you also change the value of your QUARTUS_ROOTDIR environment variable if you are switching between versions. Upgrading From the Previous Release You can upgrade your designs from the v7.2 release by simply opening them with version 8.0 and saving the model files. This procedure does not automatically update any MegaCore function blocks in your design but the previous versions are compatible provided that the previous MegaCore IP library is still installed on your system. 1 The ports on MegaCore function blocks are now displayed in VHDL port order and may have changed from the order used in the previous version even if the parameterization is the same. f You cannot upgrade from a pre-v7.1 release using the v8.0 release. If you have a pre-v7.1 design, it must be upgraded to v7.2 before you can upgrade the v7.2 design to v8.0. For more information about upgrading to v7.2 refer to Appendix A in the DSP Builder Release Notes and Errata. 2 4 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

11 Installation MATLAB Issues DSP Builder can be used with The MathWorks releases listed in Table 2 1 on page 2 1. Using Multiple Versions of MATLAB You specify the MATLAB installation that you want to use with DSP Builder during DSP Builder installation. If you have more than one MATLAB installation (for example, release R2006a and R2006b) you can register DSP Builder with another version using the following procedure: Standard Blockset 1. Open a command prompt and change directory to the DSP Builder standard blockset installation: cd <DSP Builder Install Path>dsp_builder 2. Run the following commands to register the DSP Builder blocksets with the required MATLAB installation: setupmatlabclasspath install <MATLAB Install Path> <DSP Builder Install Path>\dsp_builder Advanced Blockset 1. Open a command prompt and change directory to the DSP Builder advanced blockset installation: cd <DSP Builder Install Path>dspba 2. Run the following commands to register the DSP Builder advanced blockset with the required MATLAB installation: alt_adv_dspb_install 1 You must use quotes if the DSP Builder install path or MATLAB install path include spaces. MATLAB R2007a on 64-bit Windows The search path is not set correctly if you register either DSP Builder blockset in a MATLAB release R2007a installation that uses the default install location. This is due to a problem with the MATLAB function that sets the search path when the install path includes () characters, such as C:\Program Files (x86)\matlab\r2007a. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

12 Setting Up Licensing This problem is fixed in MATLAB R7007b and does not occur if MATLAB is installed in a path without the (x86). It can also be fixed by manually correcting the MATLAB pathdef.m file to include a leading character before each path name. Directory Path Names in MATLAB Scripts Commands invoked from within a m-script cannot resolve a UNC path to a remote file system. An error is issued when you attempt to run a MATLAB script that uses a UNC path. This affects Signal Compiler, MegaCore function, HDL import, functional simulation, hardware-in-the-loop and the State Machine Table block. This issue can be avoided by mapping the network UNC path to a local drive. Graphics Not Displayed on Example Design HTML Pages The banner, navigation icons and other graphics are not displayed when you open a DSP Builder Blockset demonstration design description from a link in the main MATLAB help window when using MATLAB R2007a or earlier. However, the pages (including all graphics) are displayed correctly when they are opened from the expandable list of demos in the MATLAB help navigator window. This issue is due to a limitation in MATLAB but has been resolved in MATLAB R2007b. Setting Up Licensing Before using DSP Builder, you must request a license file from the Altera web site at and install it on your computer. When you request a license file, Altera s you a license.dat file that enables HDL file and Tcl script generation. If you do not have a DSP Builder license file, you can create models with DSP Builder blocks but you cannot generate HDL files or Tcl scripts. 1 Before you set up licensing for DSP Builder, you must already have the Quartus II software installed on your computer with licensing set up. To install your license, you can either append the license to your existing license.dat file or you can specify an additional license file location. 2 6 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

13 Installation Appending the License to Your license.dat File To install your license, perform the following steps: 1. Close the following software if it is running on your computer: The Quartus II software The LeonardoSpectrum software The Synplify software The MATLAB and Simulink tools The ModelSim simulator The Precision RTL synthesis software 2. Open the DSP Builder license file in a text editor. The file should contain one FEATURE line, spanning two lines. 3. Open your Quartus II license.dat file in a text editor. 4. Copy the FEATURE line from the DSP Builder license file and paste it into the Quartus II license file. 1 Do not delete any FEATURE lines from the Quartus II license file. 5. Save the Quartus II license file. 1 When using editors such as Microsoft Word or Notepad, ensure that the file does not have any extra extensions appended to it after you save (for example, license.dat.txt or license.dat.doc). Verify the filename at the system command prompt. Specifying the License File Location DSP Builder looks for its license file in the same location as the Quartus II software. If the LM_LICENSE_FILE variable is used in the Quartus II software, you can modify this variable to specify an additional location for the DSP Builder license file. Alternatively, you can add the additional location to the license file search path specified in the Quartus II License Setup Options. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

14 Setting Up Licensing 2 8 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

15 3. Interoperability DSP Builder Interoperability It is possible to combine blocks from the DSP Builder standard and advanced blocksets in the same design. However, the blocks cannot be mixed together; the advanced blockset design must be embedded as a subsystem within a top-level design. The mechanism for embedding an advanced blockset subsystem within a top-level DSP Builder design is similar to that for embedding a HDL subsystem as a black box, with the Device block from the advanced blockset taking the place of the HDL Entity block from the standard blockset. The advanced blockset design is generated when you simulate the design in Simulink. This must be done before the top-level design is generated by running Signal Compiler. The design using the standard blockset must have HDL Input and HDL Output blocks delimiting the boundaries of the synthesizable design as shown in Figure 3 1. Figure 3 1. Advanced Blockset Subsystem Delimited by HDL Input and Output Blocks Altera Corporation Software Version May 2008 DSP Design Flow User Guide

16 DSP Builder Interoperability The signal dimensions on the boundary between the advanced blockset subsystem and the HDL Input/Output blocks must match. The signal types are shown on either side of the HDL Input/Output blocks after you have simulated the subsystem and there may be error message of the form: Error (10344): VHDL expression error at <subsystem>_<hdl I/O name>.vhd (line no.): expression has N elements, but must have M elements" 1 If the signal types are not displayed, check that Port Data Types is turned on in the Simulink Format menu. For example in Figure 3 1, the signal type for the HDL OutputQ should be changed to Signed Fractional [2].[15]. After this change, the signal type is shown as SBF_2_15 (representing a signed binary fractional number with 2 integer bit and 15 fractional bits) in the standard blockset part of the design (before the HDL Input block). The same signal is shown as sfix17_en15 (representing a Simulink fixed-point type with word length 17 and 15 fractional bits) in the advanced blockset design (after the HDL Input block). f For more information about the DSP Builder HDL subsystem flow, refer to the Using Black Boxes for HDL Subsystems section in the DSP Builder User Guide. For more information about the fixed-point notation used by the standard blockset, refer to the Fixed-Point Notation section in the DSP Builder User Guide. For more information about Simulink fixed-point types, refer to the MATLAB help. Note the following additional issues: The hardware destination directory specified in the Control block must be specified as an absolute path using forward slash (/) separator characters. The device specified in the Device block must match that specified in the top level Signal Compiler block. When you run the DSP Builder TestBench for a combined blockset design, mismatches when the valid signal is low are expected. 3 2 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

17 Interoperability A Simple Example Figure 3 2 on page 3 3 shows the 2-Channel Digital Up Converter advanced blockset demonstration design (demo_ad9856). The synthesizeable system in this design is the AD9856 subsystem. Its inputs are Ind, Inv and Inc. There are nine outputs with three feeding a Channel Viewer and six feeding a Scope. Figure 3 2. AD9856 Subsystem To make the design interoperable with a Signal Compiler block in the top level, perform the following steps: 1. Select the subsystem, AD9856, the scope, OvScope and the Channel Viewer and choose Create Subsystem from the popup menu to create a subsystem from them. 2. Add three Input blocks from the DSP Builder IO & Bus library at the top level immediately before the new subsystem with the types: Input: Signed Fractional [1][11] Input1: Single Bit Input2: Unsigned Integer 8 Altera Corporation Software Version May 2008 DSP Design Flow User Guide

18 DSP Builder Interoperability 3. Add two Output blocks immediately after the subsystem. Their types should both be Signed Fractional [1][15]. Figure 3 3. New Subsystem on Top-Level Model 4. Open the subsystem and add three HDL Input blocks from the DSP Builder AltLab library between the subsystem input ports and the AD9856 subsystem. These should have the same types as in Step 2: HDL Input: Signed Fractional [1][11] HDL Input1: Single Bit HDL Input2: Unsigned Integer 8 5. On the signed fractional HDL Input, set the External Type parameter to Simulink Fixed Point Type. 6. Add two HDL Output blocks between the subsystem and the subsystem output ports. These should have the same types as in Step 3(Signed Fractional [1][15]). 7. Move the Device block from the AD9856 subsystem up a level into the new subsystem you have created. 1 You have to copy the Device block and delete the old one. The new subsystem should look similar to Figure 3 4 on page Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

19 Interoperability Figure 3 4. New Subsystem 8. Open the Control block in the top level of the design and change the Hardware Destination Directory to an absolute path. For example: C:/rtl 1 You must use forward slashes (/) in this path. 9. Add a Signal Compiler block from the DSP Builder AltLab library to the top-level model. Set the Family to Stratix II to match the family specified in the Device block inside the subsystem. 1 The Device block is used to detect the presence of a DSP Builder advanced subsystem: It should always be in the same system as the HDL Input and Output blocks. 10. Simulate the design to generate HDL for the advanced subsystem. 11. Compile the system using Signal Compiler. It should compile successfully with no errors. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

20 Using Hardware in the Loop The testbench should also work although there are several cycles of delay in the ModelSim output that are not present in Simulink because the advanced blockset simulation is not cycle accurate. You can add standard DSP Builder blocks in the top level design or create additional subsystems using either the standard or advanced blocksets. Using Hardware in the Loop If you want to use Hardware in the Loop (HIL) with a DSP Builder Advanced Blockset design, the advanced blockset subsystem must be compiled with the same version of the Quartus II software that is used for HIL compilation. (There is an error loading the compiled Quartus II project if the versions are not the same.) Figure 3 5 shows the Scale block demonstration design. Figure 3 5. Scale Block Demonstration Design The demonstration design has a Device block in the ScaleSystem subsystem, hence that subsystem can be replaced by a HIL block. 3 6 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

21 Interoperability Figure 3 6 shows a HIL version of the Scale example design where the ScaleSystem subsystem has been replaced by a HIL block from the standard blockset. Figure 3 6. HIL Version of the Scale Block Demonstration Design The HIL block has been loaded with the compiled project from the original demo_scale design. The ports shown on the HIL block are expanded from the multichannel ports in the advanced blockset design. The channeled input a0 is expanded to a0, a1, a2, a4 on the HIL block. Similarly the outputs q0 and qe0 become q0, q1, q2, q3, and qe0, qe1, qe2, qe3. There is one extra reset port appearing on the HIL block. It comes from the Signals block in the original design. This port needs to be tied to 1, or 0 depending on the Reset Active parameter on the Signals block. In this example, it was set to Active Low, so the reset on the HIL block is 1, to indicate that the HIL block should not be reset while it is running. The advanced blockset uses Simulink fixed point types. DSP Builder Input and Output blocks are needed to convert the inputs (and outputs) to (and from) Simulink data types. The sizes and types on the HIL block must match the input (and output) blocks. 1 You may need to insert Output blocks after the HIL block if it is connected to other functional blocks. However, these are not required when the outputs are connected to simulink Scope blocks. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

22 3rd Party Interoperability If the HIL simulation results show all zeros, check the value of the MATLAB workspace variable alt_dspb_hil_reset. Once the value of this variable is changed, a full HIL compile is required and the board must be reprogrammed. 1 If the advanced blockset subsystem is part of a higher level DSP Builder standard blockset design, the normal DSP Builder HIL flow applies. 3rd Party Interoperability The DSP Builder Advanced Blockset is designed to operate with the Simulink, ModelSim, Quartus II and SOPC Builder software. Simulink The advanced blockset is designed to be interoperable with other Simulink blocksets. In particular, the Simulink and the standard DSP Builder blocksets are very useful for creating sophisticated interactive testbenches. There are many examples of using Simulink blocks in the tutorial and demonstration designs. In particular, Simulink scopes are used to identify signals that should be added to the ModelSim Wave view for display as a digital and analog signal. 1 The DSP Builder Advanced blockset uses Simulink fixed-point types for all operations and requires licensed versions of the Simulink Fixed Point blockset and Fixed-Point Toolbox. The Signal Processing Blockset and Communications Blocksets are also recommended and are used in the demonstration designs. f For information about Simulink Fixed Point Types, the Signal Processing Blockset and the Communications Blockset, refer to the MATLAB online help. For information about the tutorials and example designs, refer to the Example Designs section in the DSP Builder Advanced Blockset User Guide. ModelSim Integration with ModelSim is performed using a number of generated scripts: Control.do. This script is named after the control block (normally Control unless renamed by the user). It is used to compile the entire design with RTL equivalents of the testbench structures, add all relevant signals to the Wave window and run for the same period as the Simulink simulation. 3 8 Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

23 Interoperability It relies on some subordinate scripts that recursively compile library files, all the RTL files in the project, and add the signals to the waveform, before the simulation is started. These scripts are easy to follow, and may be useful when building custom flows.the design can be automatically loaded in ModelSim by clicking on the Run Modelsim block in the top-level model. f Only a subset of the Simulink blocks are translated into RTL that can be used for simulation in ModelSim. For a list of compatible blocks, refer to the Run ModelSim block description in the DSP Builder Advanced Blockset Reference Manual. <block name>_atb.do. This script runs the automatic testbench flow for a block. It relies on reading some stimulus files at run time to verify a hardware block. The automatic testbench flow runs a rigorous test and returns a result whether or not the outputs match. f For more information about integration with ModelSim, refer to the Comparison with RTL section in the DSP Builder Advanced Blockset User Guide. Quartus II The advanced blockset is designed for building high speed, high performance DSP data paths. In the majority of production designs there will be an RTL layer surrounding this data path to perform interfacing to processors, high speed I/O, memories, and so on. However, there is little emphasis on the generation of complete designs with PLLs and pinouts. To complete the design, board level components can be assigned using the DSP Builder blockset, SOPC Builder or RTL. The Quartus II software can then be used to complete the synthesis and place and route process. You can automatically load a design into the Quartus II software by clicking on the Run Quartus II block in the top-level model. SOPC Builder A class.ptf file is created for each design. This can be used to expose the processor bus for connection in SOPC builder. A DSP Builder Advanced Blockset subsystem is automatically available from the System Contents tab in SOPC Builder after the path to the class.ptf file has been added to the SOPC Builder IP search path. f For examples of the integration with Simulink, ModelSim, Quartus II and SOPC Builder, refer to the tutorials in the DSP Builder Advanced Blockset User Guide. Altera Corporation Software Version May 2008 DSP Design Flow User Guide

24 Archiving Designs Archiving Designs To create an archive for a combined design using both the standard and advanced blockset, you should first simulate the design to generate HDL for the advanced blocks in the design. Then open the Signal Compiler interface, select the Export tab and click Export. This exports HDL to the specified directory including a copy of all the standard blockset HDL and a.qip file which contains all the assignments and other information required to process the standard blockset model in the Quartus II compiler. This QIP file does not include the HDL files for the advanced blockset. To include these files, it is necessary to add the directories containing the generated HDL for the advanced block as user libraries in the Quartus II software. You can do this by choosing Add/Remove Files in Project from the Project menu, select the Libraries category and add all directories that contain generated HDL from the advanced blocks. (There are separate directories for each level of hierarchy in the Simulink design). This Quartus II project can be archived to produce a portable Quartus II archive file (.qar) file which contains all the source HDL for the combined DSP Builder system. This is achieved by choosing Archive Project from the Project menu in the Quartus II software Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

25 Appendix A. Example Design This appendix describes an example design that illustrates integration of the standard and advanced blocksets. The example design shows how to synchronize DSP Builder standard and advanced blockset systems running in parallel. ModelIP cores such as the FIR and CIC blocks provided in the advanced blockset are cycle accurate and synchronization with the DSP Builder standard blocks is straight-forward. Primitive subsystems are cycle accurate externally, with any extra latency added by the automatic pipelining annotated on the ChannelOut block. This latency value is displayed on the block and is also available as the parameter latency - so again synchronization with the standard blockset is straight-forward. In applications where two parallel paths from standard and advanced blocks merge together, you need to account for the added latency from automatic pipelining to align both paths. Functional Description Figure A 1 shows a block diagram of the example design. Figure A 1. Example Design Block Diagram Advanced Blockset Subsystem Source Sink Standard Blockset Subsystem Adaptive Delay The Advanced Blockset Subsystem consists of a simple eight-tap multi-channel low pass filter. You can assign the number of channels using the parameter ChanCount in the Model Properties PreLoadFnc callbacks. Note that changing this parameter will require manual editing of the design to supply source data for the channels, and to the wire that the Channel Viewer outputs to scopes. The current assignment is set to 4. Altera Corporation Version 8.0 A 1 May 2008 DSP Design Flow User Guide

26 Data on each channel arrives every 20 cycles, so each sample delay is 20 cycles. The filter is a simple moving average; so the filtered result is output (8 20 / 2) cycles after the input plus the latency added by automatic pipelining. For the unedited example design, this is 6 cycles. The advanced blockset part of the design is contained in a subsystem that includes a Device block. This block specifies a device that matches the device specified in the standard blockset Signal Compiler in the toplevel of the model. The internal boundaries of the standard blockset design is delimited by HDL Input and HDL Output blocks that have an external type set to Simulink Fixed Point type. Note that DSP Builder standard blockset data type uses signed binary fractional types in the format SBF_<integer bits>_<fractional bits>, whereas the Simulink fixed-point type used in the advanced blockset uses the format sfix_<word length>_<fractional bits>. The data type on the HDL Input blocks sets the fixed-point type into the advanced blockset subsystem. The data type on the HDL Output blocks must match that coming out of the advanced blockset subsystem. The standard blockset part of the design aligns and subtracts the input signal. The delay for alignment has been split in two for clarity; one delay to balance the fixed delay of the filter as designed, and another to balance the extra auto-pipelining latency. The delay for the latency is defined as a parameter dspba_latency. This parameter has a default value set in the PreLoadFnc callbacks, and is reset in the InitFcn callbacks prior to the alt_dspbuilder_update_model call as: dspba_latency = eval(get_param('demo_primitive_sync/dspba_fir/primitive_fir/channelout', 'latency')) In this design, this parameter is used to balance delays in the surrounding standard blockset design. If you need to use this value elsewhere in your design, you can hard code the value or set a workspace variable using the above command. (To determine the required latency value, run a test simulation.) Note that if using this eval(get_param) method, you need to simulate twice to make sure the correct value is used elsewhere in the design after any design changes. This is because the latency parameter is calculated at the same pre-simulation initialization stage as when it would be needed to set parameters on other blocks, and is not available beforehand. The first of these simulations recalculates the latency value after any updates, but not at a stage early enough for it to be used in the initialization of subsequent blocks. A 2 Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

27 Walkthrough The second simulation, assuming no further design changes, then uses the updated latency value (now unchanged since the last simulation). The paths have also been aligned in order to compare the input and output in the scope Compare Input To Filtered Results. Walkthrough The example design is provided in the DSP Builder standard blockset installation at: <path>\dsp_builder\designexamples\demos\combinedblockset 1. Browse to the CombinedBlockset directory in MATLAB and open the demo_primitive_sync model by double-clicking on the model file or using a command of the form: open_system( demo_primitive_sync ) 2. Double-click on the Control block. In the Hardware Destination Directory box, change../rtl_demo to <working directory>/rtl_demo 1 DSP Builder requires that the Advanced blockset Control block only contains absolute paths. Use forward slash (/) in the path. Backward slash (\) would result in errors later in the Quartus file settings. 3. Start simulation in Simulink to generate RTL for the DSP Builder advanced subsystem. 1 You may see warning messages of the form: Warning: Failed to locate Registered Model for S- Function <standard blockset block> when simulating a combined design. These are from the advanced blockset s scan of the design, and can safely be ignored. 4. Double-click on the Signal Compiler block, select the Simple tab and click Compile. This runs the complete Quartus II compilation flow for the combined system. 1 There may be error messages in Signal Compiler after you have edited the advanced blockset part of the design, or changed the Hardware Destination Directory. If this occurs, you may need to delete the existing generated Quartus II project in <mdl name>_dspbuilder. Delete this project, re-run the simulation and then re-run Signal Compiler. There should be no errors. Altera Corporation Version 8.0 A 3 May 2008 DSP Design Flow User Guide

28 5. You can compare the Simulink simulation to the ModelSim simulation of the generated hardware using the TestBench block: a. Double-click on the TestBench block and select the Simple tab. b. Click Compare against HDL. This demonstrates that the Simulink simulation is cycle and bit accurate by showing that all outputs are identical to a ModelSim simulation of the generated hardware. A 4 Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

29 Additional Information Revision History The following table displays the revision history for this user guide. Date Version Changes Made May New document for v8.0. How to Contact Altera For the most up-to-date information about Altera products, refer to the following table. Contact Note (1) Contact Method Address Technical support Website Technical training Website Product literature Website Non-technical support (General) (Software Licensing) Note to table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions This document uses the typographic conventions shown in the following table. Visual Cue Bold Type with Initial Capital Letters bold type Italic Type with Initial Capital Letters Meaning Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box. External timing parameters, directory names, project names, disk drive names, file names, file name extensions, and software utility names are shown in bold type. Examples: f MAX, \qdesigns directory, d: drive, chiptrip.gdf file. Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed Board Design. Altera Corporation Software Version 8.0 Info i May 2008 DSP Design Flow User Guide

30 Typographic Conventions Visual Cue Italic type Initial Capital Letters Subheading Title Courier type Meaning Internal timing parameters and variables are shown in italic type. Examples: t PIA, n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file. Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu. References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: Typographic Conventions. Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix n, e.g., resetn. 1., 2., 3., and a., b., c., etc. Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier. Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure. Bullets are used in a list of items when the sequence of the items is not important. v The checkmark indicates a procedure that consists of one step only. 1 The hand points to information that requires special attention. c The caution calls attention to a condition that could damage the product or design and should be read prior to starting or continuing with the procedure or process. w The warning calls attention to a condition that could cause injury to the user and should be read prior to starting or continuing the procedure or processes. r The angled arrow indicates you should press the Enter key. f The feet direct you to more information on a particular topic. Info ii Software Version 8.0 Altera Corporation DSP Design Flow User Guide May 2008

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