VCU110 GT IBERT Design Creation
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1 VCU110 GT IBERT Design Creation June 2016 XTP374
2 Revision History Date Version Description 06/08/ Updated for /13/ Updated for Updated for Production Kit. 02/03/ Updated HMC Software. 01/28/ Updated for for ES3 Silicon. AR65643 fixed. 10/06/ Initial version. Added AR61285 and AR Copyright 2016 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. NOTICE OF DISCLAIMER: The information disclosed to you hereunder (the Information ) is provided AS-IS with no warranty of any kind, express or implied. Xilinx does not assume any liability arising from your use of the Information. You are responsible for obtaining any rights you may require for your use of this Information. Xilinx reserves the right to make changes, at any time, to the Information without notice and at its sole discretion. Xilinx assumes no obligation to correct any errors contained in the Information or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE INFORMATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS.
3 Note: This presentation applies to the VCU110 VCU110 IBERT Overview Xilinx VCU110 Board VCU110 Software Install and Board Setup Testing IBERT Designs Testing IBERT GTH FMC and HMC Testing IBERT GTY CFP4 and BullsEye Testing IBERT GTY ExaMax Testing IBERT GTY Interlaken Create IBERT Design for Banks GTY Create IBERT Design for Banks GTH Add HMC Control logic to IBERT GTH design References
4 VCU110 IBERT Overview Description The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a pattern generation and verification design to exercise the UltraScale Virtex GTH and GTY transceivers. A graphical user interface is provided through the Vivado Hardware Manager. Reference Design IP LogiCORE UltraScale IBERT GTY Example Designs LogiCORE UltraScale IBERT GTH Example Designs Testing This tutorial builds a bitstream for all GTHs and another bitstream for all GTYs on the VCU110 GTH Testing: FMC and Hybrid Memory Cube (HMC) GTY Testing: ExaMax/Interlaken, CFP4, and BullsEye cables
5 Xilinx VCU110 Board
6 Note: The IBERT tests require the clock setup from XTP380 VCU110 Software Install and Board Setup Complete setup steps in XTP380 VCU110 Software Install and Board Setup: Software Requirements VCU110 Board Setup UART Driver Install Clock setup
7 VCU110 Setup Open the RDF VCU110 GT IBERT Design Files ( C) ZIP file, and extract the ready_for_download files to your C:\ drive:
8 VCU110 Setup From RDF0336 ZIP file, extract the hmc_files files to your C:\ drive:
9 Testing IBERT GTH
10 Testing IBERT GTH Open a Vivado Tcl Shell: Start All Programs Xilinx Design Tools Vivado Vivado Tcl Shell
11 Testing IBERT GTH In the Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_gth.tcl
12 Testing IBERT GTH The HMC initialization routine can be seen in the UART window
13 Testing IBERT GTH If needed, set Vivado GUI layout to Serial I/O Analyzer
14 Testing IBERT GTH FMC Line Rate is 16.3 Gbps
15 Testing IBERT GTH HMC Line Rate is 15 Gbps; close Vivado GUI after finished viewing
16 Testing IBERT GTY
17 Testing IBERT GTY This test requires customer supplied BullsEye cables In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_gty.tcl
18 Testing IBERT GTY BullsEye line rate is 28 Gbps; CFP4 line rate is 25 Gbps Close Vivado GUI and Tcl Shell after finished viewing
19 Testing IBERT ExaMax
20 Testing IBERT ExaMax In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_examax.tcl
21 Testing IBERT ExaMax ExaMax line rate is 28 Gbps Close Vivado GUI and Tcl Shell after finished viewing
22 Testing IBERT Interlaken
23 Testing IBERT Interlaken In a Vivado Tcl Shell type: cd C:/vcu110_ibert/ready_for_download source ibert_bank_interlaken.tcl
24 Testing IBERT Interlaken Interlaken line rate is 28 Gbps Close Vivado GUI and Tcl Shell after finished viewing
25 Create IBERT Design for GTYs
26 Create IBERT Design for GTYs Open Vivado Start All Programs Xilinx Design Tools Vivado Vivado Select Create New Project
27 Create IBERT Design for GTYs Click Next
28 Note: Vivado generally requires forward slashes in paths Create IBERT Design for GTYs Set the Project name and location to ibert_bank_gty and C:/vcu110_ibert; check Create project subdirectory
29 Create IBERT Design for GTYs Select RTL Project Select Do not specify sources at this time
30 Create IBERT Design for GTYs Under Boards, select the VCU110 Board
31 Create IBERT Design for GTYs Click Finish
32 Create IBERT Design for GTYs Click on the IP Catalog
33 Create IBERT Design for GTYs Select IBERT UltraScale GTY, v1.2 under Debug & Verification
34 Create IBERT Design for GTYs Right click on IBERT UltraScale GTY and select Customize IP
35 Create IBERT Design for GTYs Set the Component name: ibert_bank_gty Under the Protocol Definition tab Select 2 Protocols
36 Create IBERT Design for GTYs Under the Protocol Definition tab Protocol Custom 1: LineRate: 28.0, Refclk: 175 Quad Count: 9 Protocol Custom 2: LineRate: 25.0, Refclk: Quad Count: 4 Select the Protocol Selection tab
37 Create IBERT Design for GTYs Set Quads 122, 125, 127, and 128 to Custom 2 / 25.0 Gbps
38 Create IBERT Design for GTYs Set the remaining Quads to Custom 1 / 28.0 Gbps
39 Create IBERT Design for GTYs Under the Clock Settings tab, set the System Clock: DIFF SSTL12, P Package Pin: J24, Frequency: 300 Deselect Enable DIFF Term
40 Create IBERT Design for GTYs Review the summary and click OK
41 Note: This step will take about 40 minutes Create IBERT Design for GTYs Click Generate
42 Create IBERT Design for GTYs The Generated IBERT IP appears in Design Sources Wait until checkmark appears on ibert_bank_gty_synth_1
43 Compile Example Design Right click on ibert_bank_gty and select Open IP Example Design
44 Compile Example Design Set the location to C:/vcu110_ibert/ibert_bank_gty and click OK
45 Note: This step will take about 140 minutes Compile Example Design A new project is created under <design path>/ Click Generate Bitstream
46 Note: *Will take 15 minutes to open; this step can be skipped Compile Example Design Open and view the Implemented Design* Click Open Hardware Manager
47 Run IBERT Example Design Click Open target and select Auto Connect
48 Run IBERT Example Design Select Program device xcvu190_0
49 Run IBERT Example Design The newly created bitstream and LTX files are set to the default Click Program
50 Run IBERT Example Design Click on Create links
51 Run IBERT Example Design Add links from Quad_122 through Quad_128
52 Run IBERT Example Design Skip Quad_124 and Quad_126, if BullsEye cables are not available
53 Run IBERT Example Design Click OK
54 Run IBERT Example Design The GTY links appear under the Serial I/O Links tab
55 Run IBERT Example Design Select the TX and RX Patterns and set to PRBS 31-bit
56 Run IBERT Example Design Click the BERT Reset button for Link Group 0 to reset all links
57 Run IBERT Example Design All the links are showing no errors
58 Run IBERT Example Design The Tcl commands can be captured into a TCL file for later playback
59 Create IBERT Design for Banks GTH
60 Create IBERT Design for Banks GTH Open Vivado Start All Programs Xilinx Design Tools Vivado Vivado Select Create New Project
61 Create IBERT Design for Banks GTH Click Next
62 Note: Vivado generally requires forward slashes in paths Create IBERT Design for Banks GTH Set the Project name and location to ibert_bank_gth and C:/vcu110_ibert; check Create project subdirectory
63 Create IBERT Design for Banks GTH Select RTL Project Select Do not specify sources at this time
64 Create IBERT Design for Banks GTH Under Boards, select the VCU110 Board
65 Create IBERT Design for Banks GTH Click Finish
66 Create IBERT Design for Banks GTH Click on IP Catalog
67 Create IBERT Design for Banks GTH Select IBERT UltraScale GTH, v1.3 under Debug & Verification
68 Create IBERT Design for Banks GTH Right click on IBERT UltraScale GTH and select Customize IP
69 Create IBERT Design for Banks GTH Set the Component name: ibert_bank_gth Under the Protocol Definition tab Select 3 Protocols
70 Create IBERT Design for Banks GTH Under the Protocol Definition tab Protocol Custom 1: LineRate: 16.3, Refclk: 163, Quad Count: 4 Protocol Custom 1: LineRate: 15, Refclk: 187.5, Quad Count: 8 Protocol Custom 1: LineRate: 5, Refclk: 100, Quad Count: 1
71 Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_220, QUAD_221, QUAD_224, and QUAD_224 to Custom 1 / 16.3 Gbps Set QUAD_220 Refclk to MGTREFCLK0 221
72 Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_225 through QUAD_232 to Custom 2 / 15 Gbps Set QUAD_225-QUAD_228 Refclk to MGTREFCLK0 226 Set QUAD_229-QUAD_232 Refclk to MGTREFCLK0 230
73 Create IBERT Design for Banks GTH Under the Protocol Selection tab Set QUAD_233 to Custom 3 / 5 Gbps Set QUAD_233 Refclk to MGTREFCLK0 233
74 Create IBERT Design for Banks GTH Under the Clock Settings tab, set the System Clock: DIFF SSTL12, P Package Pin: J24, Frequency: 300 Deselect Enable DIFF Term
75 Create IBERT Design for Banks GTH Review the summary and click OK
76 Note: This step will take about an hour Create IBERT Design for Banks GTH Click Generate
77 Create IBERT Design for Banks GTH The Generated IBERT IP appears in Design Sources Wait until checkmark appears on ibert_bank_gth_synth_1
78 Compile Example Design Right click on ibert_bank_gth and select Open IP Example Design
79 Compile Example Design Set the location to C:/vcu110_ibert/ibert_bank_gth and click OK
80 Note: The original project window can be closed Compile Example Design A new project is created under <design path>/
81 Compile Example Design In the Tcl console, type: source C:/vcu110_ibert/hmc_files/system.tcl
82 Compile Example Design HMC control Block design appears Click Add Sources
83 Modifications to Example Design Select Add or create constraints and click Next
84 Modifications to Example Design Select the example_ibert_bank_gth.xdc file and delete it from the Add Sources dialog This file is already in the project
85 Modifications to Example Design Add the system.xdc file from C:\vcu110_ibert\hmc_files Make sure Copy constraint files into project is checked Click Finish
86 Compile Example Design Right click on example_ibert_bank_gth.v and remove it from the project
87 Compile Example Design Select Ignore and click OK
88 Compile Example Design Click Add Sources again
89 Modifications to Example Design Select Add or create design sources and click Next
90 Modifications to Example Design Add example_ibert_bank_gth.v from C:\vcu110_ibert\hmc_files Make sure Copy constraint files into project is checked Click Finish
91 Modifications to Example Design Click Generate Block Design
92 Modifications to Example Design Click Generate
93 Modifications to Example Design Select File Export Export Hardware Deselect Include bitstream then click OK
94 Modifications to Example Design Select File Launch SDK Click OK
95 Modifications to Example Design From the New pulldown, select Board Support Package
96 Modifications to Example Design Click Finish
97 Modifications to Example Design Click OK
98 Modifications to Example Design From the pulldown, select Application Project
99 Modifications to Example Design Name the project hmc_loopback For the Board Support Package, select Use existing Click Next
100 Modifications to Example Design Select Empty Application Click Finish
101 Modifications to Example Design Right click on hmc_loopback, and select Import
102 Modifications to Example Design Expand General, select File System, and click Next
103 Modifications to Example Design Select the C:\vcu110_ibert\hmc_files directory Expand hmc_files and check the src folder Click Finish
104 Modifications to Example Design Expand the hmc_loopback and src folders; the five.c and.h files should be present as shown here
105 Modifications to Example Design Right click on hmc_loopback and select Generate Linker Script
106 Modifications to Example Design Set the stack and heap to (16 KB), then click Generate
107 Modifications to Example Design After software recompiles, close SDK and return to Vivado
108 Modifications to Example Design Select Add Sources
109 Modifications to Example Design Select Add or Create Design Sources
110 Modifications to Example Design Add hmc_loopback.elf from the SDK tree Make sure Copy sources into project is deselected Click Finish
111 Modifications to Example Design Right-click on the ELF file and select Associate ELF Files
112 Modifications to Example Design Click the button to the right; select the hmc_loopback.elf then click OK twice
113 Note: This step will take about 120 minutes Compile Example Design Click Generate Bitstream
114 Note: *Will take 13 minutes to open; this step can be skipped Compile Example Design Open and view the Implemented Design* Click Open Hardware Manager
115 Run IBERT Example Design Click Open target and select Auto Connect
116 Run IBERT Example Design Select Program device xcvu190_0
117 Run IBERT Example Design The newly created bitstream and LTX files are set to the default Click Program
118 Run IBERT Example Design The HMC initialization routine can be seen in the UART window
119 Run IBERT Example Design As per AR61285, if a QPLL is not locking, at the Tcl Console, type: source C:/vcu110_ibert/ready_for_download/reset.tcl
120 Run IBERT Example Design Quads are now locked Click Create links
121 Run IBERT Example Design Add the first forty-eight links
122 Run IBERT Example Design The GTH links appear under the Serial I/O Links tab
123 Run IBERT Example Design Set the TX and RX Patterns to PRBS 31-bit
124 Run IBERT Example Design Now all links are set to PRBS 31-bit Click the BERT Reset button to reset all links
125 Note: If needed, tune FMC TX Pre-Cursor to 3.41 db Run IBERT Example Design All the links are showing no errors
126 Run IBERT Example Design The Tcl commands can be captured into a TCL file for later playback
127 References
128 References IBERT IP LogiCORE IP Integrated Bit Error Ratio Tester for UltraScale GTY PG196 v1_2/pg196-ibert-ultrascale-gty.pdf LogiCORE IP Integrated Bit Error Ratio Tester for UltraScale GTH PG173 v1_3/pg173-ibert-ultrascale-gth.pdf Vivado Programming and Debugging Vivado Design Suite Programming and Debugging User Guide UG908 ug908-vivado-programming-debugging.pdf
129 Documentation
130 Documentation Virtex UltraScale Virtex UltraScale FPGA Family VCU110 Documentation Virtex UltraScale FPGA VCU110 Development Kit VCU110 Board User Guide UG ug1073-vcu110-eval-bd.pdf VCU110 Known Issues Master Answer Record
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