AT91 ARM Thumb Microcontrollers. Application Note. Using the ECC Controller on AT91SAM9260/9263 and AT91SAM7SE Microcontrollers. 1.

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1 Using the ECC Controller on AT91SAM9260/9263 and AT91SAM7SE Microcontrollers 1. Scope The purpose of this document is to explain how to use the Error Corrected Code (ECC) Controller embedded in the AT91SAM9260/9263 and AT91SAM7SE family of ARM Thumb -based microcontrollers. The ECC controller performs 2-bit data error identification and single-bit correction to maintain integrity of data stored in NAND Flash and SmartMedia devices. 2. NAND Flash Device Overview 2.1 Internal Array Architecture The NAND Flash array is organized in a series of blocks which are divided in several pages. Data is stored either in byte (8 bits) or half-word (16 bits) format depending on the device type. Each page consists of a main area for storing data and a spare area (physically similar) typically used for data error identification and correction, wear levelling, etc... One particularity of NAND Flash devices is that they may contain a percentage of invalid blocks in the memory array. Before delivering the chip, these blocks are identified and marked as Invalid Blocks in the first or second page of each block. The existence of bad blocks does not affect the good ones because each block is independent and individually isolated from the bit lines by block select transistors. Because NAND Flash devices have a finite lifetime (approximately write/erase cycles), additional invalid blocks may develop while being used. Storing data requires bad-block management and data error identification and correction. Refer to Section 3. Invalid Block Management. AT91 ARM Thumb Microcontrollers Application Note 2.2 Basic Operation Principle NAND Flash operations are fully controlled through a multiplexed I/O interface and additional control signals. Commands, addresses and data are transferred through the external input/output bus (8-bit or 16-bit) to the dedicated internal registers. In 16- bit devices, commands, addresses and data use the lower 8 bits (7-0), the upper 8 bits are only used during data-transfer cycles. Read and program operations are performed on a per page basis whereas erase operations are performed on a block basis. To read or write from NAND Flash, a command sequence is issued to select a block and a page. After this selection, the entire page can be read or written. The command sequence normally consists of a Command Latch Cycle, an Address Latch Cycle and a Data Cycle either read or write.

2 The waveforms shown in Figure 2-1 depict the successive accesses: Command Latch, Address Latch and Data Output. Notice that no command can be sent to the NAND Flash during t R due to it s busy-state period. Figure 2-1. Page READ Operation CLE t CEA CE t REA RE ALE t R R/B WE I/Ox 00h Address (5 cycles) 30h Command cycle 1 Address cycles Command cycle 2 Don't Care 3. Invalid Block Management Please refer to the NAND Flash manufacturer s datasheet for command sets and full operation description. 3.1 Invalid Block Definition As mentioned in Section 2.1 Internal Array Architecture, NAND flash devices contain a certain percentage of invalid blocks at the end of the production process. Invalid blocks are defined as blocks that contain one or more invalid bits. 3.2 Spare Assignment The invalid block status byte location and the ECC locations within the spare area depend on the device type (small/large-page devices and 8/16- bit devices). The widely used spare area assignment defined by SAMSUNG is illustrated in Figure 3-1, Figure 3-2, Figure 3-3 and Figure Application Note

3 Application Note Figure 3-1. Small Page 8-bit Device Organization 512 Bytes Spare 16 Bytes LSN0 LSN1 LSN2 Reserved Reserved BI ECC0 ECC1 ECC2 S-ECC0 S-ECC1 Reserved Reserved Reserved Reserved Reserved 1 st B 2 nd B 3 rd B 4 th B 5 th B 6 th B 7 th B 8 th B 9 th B 10 th B 11 th B 12 th B 13 th B 14 th B 15 th B 16 th B Figure 3-2. Small Page 16-bit Device Organization 256 Half Words Spare 8 Half Words LSN0 LSN1 LSN2 Reserved Reserved Reserved ECCa ECCb ECCc S-ECCa S-ECCb B1 Reserved Reserved Reserved Reserved LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 1 st Half Word 2 nd Half Word 3 rd Half Word 4 th Half Word 5 th Half Word 6 th Half Word 7 th Half Word 8 th Half Word Figure 3-3. Large Page 8-bit Device Organization 512 Bytes 512 Bytes 512 Bytes 512 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes BI Reserved LSN0 LSN1 LSN2 Reserved Reserved Reserved ECC0 ECC1 ECC2 S-ECC0 S-ECC1 Reserved Reserved Reserved 1 st B 2 nd B 3 rd B 4 th B 5 th B 6 th B 7 th B 8 th B 9 th B 10 th B 11 th B 12 th B 13 th B 14 th B 15 th B 16 th B Figure 3-4. Large Page 16-bit Device Organization 256 Half Words 256 Half Words 256 Half Words 256 Half Words 8 Half Words 8 Half Words 8 Half Words 8 Half Words BI BI LSN0 LSN1 LSN2 ReservedReservedReserved ECC0 ECC1 ECC2 S-ECC0 S-ECC1 Reserved Reserved Reserved LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB 1 st Half Word 2 nd Half Word 3 rd Half Word 4 th Half Word 5 th Half Word 6 th Half Word 7 th Half Word 8 th Half Word Abbreviations as used in Figure 3-1 through Figure 3-4 above BI ECC S-ECC HW LSN Invalid block information ECC code for data ECC code for LSN data Half Word Logical sector number 3

4 3.3 Invalid Block Identification Before shipping, every NAND Flash device is tested with specific test patterns under different voltage and temperature conditions in order to identify memory locations containing errors. When errors are detected, the block to which the invalid memory location belongs is marked as an Invalid Block. All device locations are erased (FFh for 8-bit devices, FFFFh for 16-bit devices) except locations where the invalid block information is written. As illustrated above in Figure 3-1,Figure 3-2, Figure 3-3, and Figure 3-4, the bad block Information is located in the first byte (8-bit devices) or first half word (16-bit devices) in the spare area for Large Page devices and in the sixth byte (8-bit devices) or sixth half word (16-bit devices) in the spare area of Small Page devices. Manufacturers make sure that every invalid block has non-ffh (8-bit devices) or non-ffffh (16-bit devices) data in the bad block information location. Since invalid block information (located in the spare area) written by the manufacturer is not write/erase protected, it can be lost and will be almost impossible to recover. In order to prevent loosing this information, it is highly recommended to proceed to a block status mapping before any write or erase operation. The flow chart below describes how this can be done by software. Figure 3-5. Bad Block Identification Flow Chart Start Create Invalid Block(s) Table Set Block Address = 0 Point to Bad Block Information location No Data = FFh or FFFFh? Update Invalid Block(s) Table Yes No Last Block? Increment Block Address Yes End Important Note: Any intentional erasure of the original invalid block information is prohibited. 4 Application Note

5 Application Note 4. Error Detection and Correction NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. To ensure data read/write integrity, system error checking and correction (ECC) algorithms should be implemented. The AT91SAM9260/9263 and AT91SAM7SE microcontrollers provide ECC hardware support. The embedded ECC controller is capable of single-bit error correction and 2-bit error detection per page (528/1056/2112/4224). When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannot be corrected. 4.1 ECC Calculation Algorithm For Single-bit Error Correction and Double bit Error Detection (SEC-DED) hsiao code is used. 32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/ or 16- bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are generated according to the schemes shown in Figure 4-1 and Figure 4-2. Figure 4-1. Parity Generation for 512/1024/2048/ bit Words1 1st byte 2nd byte 3rd byte 4 th byte P8 P8' P8 P8' P16 P16' P32 PX (page size -3 )th byte (page size -2 )th byte (page size -1 )th byte Page size th byte P8 P8' P8 P8' P16 P16' P32 PX' P1 P1' P1 P1' P1 P1' P1 P1' P2 P2' P2 P2' P4 P4' Page size = 512 Px = 2048 Page size = 1024 Px = 4096 Page size = 2048 Px = 8192 Page size = 4096 Px = P1=bit7(+)bit5(+)bit3(+)bit1(+)P1 P2=bit7(+)bit6(+)bit3(+)bit2(+)P2 P4=bit7(+)bit6(+)bit5(+)bit4(+)P4 P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1' P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2' P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4' 5

6 Figure 4-2. Parity Generation for 512/1024/2048/ bit Words 1st word 2nd word 3rd word 4th word (Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word 6 Application Note

7 Application Note 4.2 ECC Controller Preliminary Requirements In order to calculate ECC properly during write/read and read processes, the following constraints must be respected: at least 1 Hold time must be programmed in the RWHOLD field of the SMC_CSRx register (only AT91SAM7SE family is concerned) read/write sequence must start at a page boundary read/write accesses must be done through the whole main area since ECC is calculated on the main area data data accesses must be performed chronologically through the main area the appropriate page size must be programmed in the PAGESIZE field of the ECC_MR register 4.3 ECC Controller Functional Description Page Write Sequence The ECC controller is automatically reset as soon as the first write command (80h) is performed to the NAND Flash or the SmartMedia device. The ECC calculation starts only once the required address cycles (the number of address cycles depends on the device type) is performed to NAND Flash or the SmartMedia device. The ECC is refreshed at each write access of the page until the last byte or half word of the main area is written. Once the whole main area has been written, the final ECC result is available in the ECC Parity Register (ECC_PR) and ECC NParity Register (ECC_NPR) until a new start condition occurs. It is up to the software application to write the Parity ECC and NParity ECC in the appropriate locations of the device spare area. Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores any other command which is performed to the NAND Flash or the SmartMedia device. Figure 4-3 below illustrates a full page write sequence with ECC calculation. Figure 4-3. ECC Calculation During Page Write Sequence without Random Write Spare ECC Controller Reset Start of ECC Calculation Main Size ECC Result Ready in and Locked I/Ox 80h Address 1st 2nd... n th ECC ECC ECC ECC 10h Write Command 1 Address cycles Write Command 2 Accesses Ignored by the ECC Controller for ECC calculation Main Write Accesses Accesses Allowing ECC calculation Spare ECC locations Write Accesses 7

8 Figure 4-4. ECC Calculation During Page Write Sequence with Random Write Spare ECC Controller Reset Start of ECC Calculation Main Size ECC Result Ready in and Locked I/Ox 80h Address 1st 2nd... n th Write Address cycles Command 1 85h Address ECC ECC ECC ECC 10h Random Column Address Write cycles Command Write Command 2 Accesses Ignored by the ECC Controller for ECC calculation Main Write Accesses Accesses Allowing ECC calculation Spare ECC locations Write Accesses Page Read Sequence The ECC controller is automatically reset as soon as the first read command (00h) is performed to the NAND Flash or the SmartMedia device. The ECC calculation starts only once the required address cycles (the number of address cycles depends on the device type) and the second read command (30h) is performed to the NAND Flash or the SmartMedia device. The ECC is refreshed at each read access of the page until the last byte or half word of the main area is read. Once the whole main area has been read, the next four data read accesses must be performed to the spare area locations where ECC has been previously stored by the software application. If this condition is not respected, the ECC controller will not be able to check data integrity. Since Parity ECC and NParity has been previously stored in locations of the spare area which are not contiguous to the main area, it is useful to perform a random read command sequence before performing the four ECC data accesses. Please note that apart from data accesses (ALE = CLE = 0), the ECC controller ignores any other command which is performed to the NAND Flash or the SmartMedia device. The ECC controller performs error detection automatically by applying an XOR operation between the calculated ECC and the ECC stored in the spare area. In order to determine if an error has been detected by the ECC controller, the software application must check the MULERR, ECCERR and RECERR fields in the ECC Status Register (ECC_SR) No Error MULERR, ECCERR and RECERR fields in the ECC Status Register (ECC_SR) are all cleared. XOR between the calculated ECC computation and the ECC code stored in the spare area is equal to Recoverable Error Only the RECERR field in the ECC Status register (ECC_SR) is set. The corrupted word offset in the read page is defined by the WORDADDR field in the ECC Parity Register (ECC_PR). The corrupted bit position in the concerned word is defined in the BITADDR field in the ECC Parity Register (ECC_PR). 8 Application Note

9 Application Note ECC Error The ECCERR field in the ECC Status Register (ECC_SR) is set. An error has been detected in the ECC code stored in the Spare area of the device. The position of the corrupted bit can be found by applying an XOR operation between the ECC Parity and the ECC NParity codes previously stored in the spare area of the device Non Recoverable Error The MULERR field in the ECC Status Register (ECC_SR) is set. Several errors have been detected in the data stored in the device. The block to which this page belongs should be declared as invalid. Figure 4-5 below illustrates a full page read sequence with ECC error detection. Figure 4-5. ECC Error Detection During Page Read Sequence with Random Read Spare ECC Controller Reset Start of ECC Calculation ECC Result Ready and Locked Start of ECC Error Detection ECC Error Detection Completed Main Size I/Ox 00h Address 30h 1st 2nd... n th 05h Address E0h ECC ECC ECC ECC Read Address Cycles Read Data Accesses Random Column Address Random Command 1 Command 2 Read cycles Read Command 1 Command 2 Accesses ignored by the ECC Controller for ECC calculation Main Read Accesses Accesses allowing ECC calculation Accesses ignored by the ECC Controller for Error Detection Spare ECC locations Read Accesses Figure 4-6. ECC Error Detection During Page Read Sequence without Random Read Spare ECC Controller Reset Start of ECC Calculation ECC Result Ready and Locked Start of ECC Error Detection ECC Error Detection Completed Main Size I/Ox 00h Address 30h 1st 2nd... n th ECC ECC ECC ECC Read Command 1 Address Cycles Read Command 2 Data Accesses Accesses ignored by the ECC Controller for ECC calculation Main Read Accesses Accesses allowing ECC calculation Spare ECC locations Read Accesses 9

10 5. High-Level File System Software Compatibility 6. Software Example High-level software drivers for managing file systems in NAND Flash devices are available from different sources. These drivers provide support for wear leveling, bad block management, ECC etc... File Systems available on the market usually manage ECC as: 3 bytes ECC for 256 bytes of data per page 3 bytes ECC for 512 bytes of data per page The AT91SAM ECC controller manages ECC as: 4 bytes ECC for 512/1024/2048/4096 bytes of data per page Since the ECC offset in the spare area and the number of ECC per page is not yet normalized, it is highly recommended to manage ECC by software when using a high-level file system. A software example managing Bad Block Information and ECC error detection for Large Page Devices can be downloaded from the Atmel web site via the following link: 10 Application Note

11 Application Note 7. Revision History Doc. Rev 6320A 6320B Comments First issue Figure 4-3 and Figure 4-4 updated, Section 3.2 Spare Assignment, updated sentence refering to figures. Change Request Ref

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