7/7/2013 TIFAC CORE IN NETWORK ENGINEERING

Transcription

1 TMS320C50 Architecture 1

2 OVERVIEW OF DSP PROCESSORS BY Dr. M.Pallikonda Rajasekaran, Professor/ECE 2

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5 Short history of DSPs 1960 DSP hardware using discrete components 1970 Monolithic components for DSP subsystems 1979 Intel 2920 DSP (40 pin DIP)(EPROM,A/D,D/A,RAM)(1200bps modem) 1982 Texas Instruments TMS

6 Inside a DSP? Computer Engine Input / Output Program Memory Data Memory Serial ports Timers Host ports External ports Link ports I/O connects to outside world 6

7 INSIDE A DSP ENGINE? 7

8 Why DSP? - Flexible to change Signal Processing Operations through a change in Software, whereas hardwired machines are difficult to Reconfigure. - High Speed Parallel Processing enables it to Real World Processing. - Multi-Function Instruction like MAC etc,. - Multiple data paths - Flexible addressing modes 8

9 MEMORY ARCHITECTURE Stored Program and Data Program Control Input Output ALU Von Neumann Architecture Stored Program Program Control ALU Input Output Stored Data Harvard Architecture 9

10 Conventional microprocessors use: Von Neumann architecture -program and data all in a single memory -Address and data buses are shared between instruction and data fetches. -simple -effective BUT CPU/ALU Addre ss Data Memory performance problems: -fetch for next instruction collides with data fetch/store -Buses may be idle during instruction decode 10

11 Most DSP chips use Harvard architecture -separate memory space(s) for program and data -separate data and program buses D1 Address Data Memory #1 CPU/ALU D1 Data D2 Address P Address Instr. D2 Data Data Memory #2 Program Memory 11

12 Comparison between DSP & GP processor GP µp optimized for: -Multi task operations -handling huge OS -handling various programs -Multiple I/O management -transporting large size of data DSPs optimized for: -special digital processing -real time processing -small code size -single program -limited number of I/O -low power 12

13 DSP LEADING MANUFACTURERS TEXAS INSTRUMENTS (TI) ANALOG DEVICES (ADSP) MOTOROLA 13

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15 TMS320C320 DSP Family 15

16 DSP TEXAS INSTRUMENTS FAMILY TMS320C2000 C24X,C28X DSPs Control Optimized TMS320C5000 C54X,C55X DSPs Power Efficient OMAP C55X+ARM TMS320C6000 C62X,C64X,C67X DSPs High Performance 16

17 TMS320C2000 PLATFORM ROADMAP 17

18 TMS320C2000 DSP Platform TMS320C2000 family offers various DSP processors for motor control. Based on the specific requirements, the user can choose the particular device for the speed control of Induction Motor/Brush less motor/ Switch Reluctance motor. In this platform varieties of DSP Processors are available in 3 categories. TMS320F240 TMS320F2407 TMS320F2812. Targeted for Industrial Automation, Automatic Control Application, UPS, Motor Control, etc. 18

19 TMS320F240 TMS320F2407A TMS320F Bit Fixed point 16 Bit Fixed point 32 Bit Fixed point 20 MIPS 40 MIPS 150 MIPS 544 x 16 Bit RAM 2.5k x 16 Bit RAM 18k x 16 Bit RAM 3 Timers 4 Timers 7 Timers SPI & SCI Serial ports SPI, SCI & CAN Serial ports SPI, SCI & CAN Serial ports 12 PWM Channels 16 PWM Channels 16 PWM Channels 16 Channel 6 microsec conversion time 16 Channel 0.5 micro sec conversion time 16 Channel 200 ns conversion time 19

20 TMS320C5000 PLATFORM ROADMAP 20

21 TMS320C6000 PLATFORM ROADMAP 21

22 TMS320C6000 DSP Platform This has got 3 series of DSP Processor family. TMS320C62XX 32 Bit Fixed Point DSP TMS320C64XX 32 Bit Fixed Point DSP TMS320C67XX 32 Bit Floating Point DSP 22

23 Development Tools CODE COMPOSER STUDIO It includes Assembler Linker Simulator C/C++ compiler Debugger 23

24 ANALOG DEVICES FAMILY Blackfin processors Tiger SHARC processors SHARC DSPs ADSP-21xx Mixed signal DSPs 24

25 NOMENCLATURE OF DSP PROCESSORS TMS 320 C 25 GB L TMX-Expt. Device TMP-Prototype Device TMS-Qualified Device C-CMOS E-CMOS EPROM PACKAGE TYPE TEMPERATURE GB-Ceramic L N-Plastic DIP H FN-Plastic Leaded S FD-Ceramic Leadless M A

26 TMS320C5x Family Features Fabrication using CMOS integrated-circuit technology Architectural design is based on the C25 Advanced Harvard architecture A CPU with application-specific hardware logic On-chip peripherals On-chip memory Highly specialized instruction set 26

27 TMS320C50 PROCESSOR TMS320C50PQ57 27

28 A(15-0) D/P RAM B0 512 X 16 D. RAM B1 512 X 16 D. RAM B2 32 X 16 D/P RAM 9K X 16 P. ROM 2K X 16 TMS320C50 D(15-0) CPU 16-bit T-Reg 1,2 16-bit T-Reg0 16 X 16 Multiplier 16-bit Barrel 32-bit P-register Shifter (L or R) ShiftL(0, 1, 4, -6) 32-bit ALU 32-bit Accumulator and Buffer ShiftL( 0 7 ) 8 Auxiliary Registers 8 Level H/W Stack 3 Status Registers Block repeat/circular Buffer 11 Shadow Registers I/O Ports 64K X 16 Software Waitstates Timer Serial Port Sync PLU BitSet, Clear Test, Toggle 28

29 Central Arithmetic Logic Unit (CALU ) 16-bit 16-bit hardware multiplier with a 32-bit product capability 32-bit arithmetic logic unit (ALU) PLU-Executes IIy only logical operation without affecting Accumulator 32-bit accumulator (ACC) 32-bit accumulator buffer (ACCB) 0- to 16-bit left and right data barrel-shifters 29

30 Program Bus Data Bus MUX 32 Right/Left Shifter (0-16) TMS320C50 Multiplier/Accumulator T Register (16) 16 Multiplier (16 X 16) MUX P Register (32) 32 Left Shifter (0,1,4,-6) Arithmetic Logic Unit (ALU) 32 Accumulator Register (32) 32 MUX 32 Left Shifter (0 7) 32 Accumulator Buffer (32) 30

31 C50 MEMORY MAPPING 0000 Program 0000 Data EEPROM (48KW) INTERNAL RAM (32KW) BFFF C000 FFFF EXTERNAL RAM (16KW) 7FFF 8000 FFFF EXTERNAL RAM (32KW) 31

32 TMS320C50 DATA MEMORY 32

33 TMS320C50 DATA MEMORY Total memory = 0000h FFFFh (64KW) Total no. pages = 200h Every page contains 80h locations Page 0 = 0h * 80h = 0000 to 007F Page 1 = 1h * 80h = 0080 to 00FF Page 100 = 100h * 80h = 8000 to 807F Page 1FF = 1FFh * 80h = FF80 to FFFF 33

34 Addressing Modes Direct addressing-add 9h Indirect addressing Immediate addressing-rpt # 99 Dedicated-register addressing Memory-mapped register addressing Circular addressing 34

35 Dedicated-register addressing BLDD BMAR,DAT 100 BLDD-Block Move from Data memory to Data memory BMAR-Block move Address Register BMAR-200h-Predefined Data in Address 200h is copied to data memory location 100h 35

36 Memory-mapped register addressing LMMR, CBCR #800h Data in CBCR is loaded to the location 800H CBCR-Circular buffer control Register 36

37 Circular addressing CBSR-1 CBSR-2 CBER-1 CBER-2 CBCR Used for convolution, correlation & FIR Filter 37

38 ASSEMBLEY LANGUAGE PROGRAMS Linear convloution.text.mmregs START: LDP #0002H LAR 3,#8200H ;y(n) starting LAR 4,#0007 ;N1+N2-1 LAR 1,#8100H ; x(n) data array with N1-1 trailing zeros LOP: MAR *,1 LACC *+ SACL 050H ;starting of the scope of multiplication LAR 2,#0153H ; end of the array, to be multiplied with h(n) {150+N1-1} MAR *,2 ZAP RPT #0003 ;N1-1 times so that N1 times MACD 0C100H,*- APAC ;to accmulate the final product sample MAR *,3 SACL *+ MAR *,4 BANZ LOP,*- H: B H input : h(n) - program memory c100-1 c101-3 c102-1 c103-3 c104-0 c105-0 c106-0 c107-0 x(n) - data memory output: y(n) data memory

39 Basic software tools for dsp design Basic text editor :This can be a very simple application such as windows notepad.it is used for entering DSP programs Assembler/ Compiler :Used to convert the user editor based files into a machine readable format Conversion Utilities :Converts assembled and linked DSP code into a DSP chip executable format (.hex,.bin,.asc etc) Down loader :It is used to transfer the DSP executable format into the DSP development board Debugger :Enables software to be tested for the particular DSP device; the debug environment may be in the form of a simulator or emulator 39

40 Source C C++ Software Compiler Optimizer Efficiency Effort % Low ASM Hand 100% High Optimize 40

41 Software Tools Assembler optimizer Link.cmd Text editor.asm Assembler.obj Linker.out Debugger.c Compiler optimizer.c - c source file.asm - assembly source file.obj - object file.out - executable file.cmd - linker command file 41

42 DSP choosing considerations Arithmetic formats Data width Speed Memory organization Ease of development Multiprocessor support Power consumption management Cost 42

43 Fixed point Floating point -difficult programming -low cost -limited dynamic -range & precision -more flexible -easier to program -more expensive -higher power consumption 43

44 Data widths are -32 bit -16 bit -24 bit -20 bit Cost considerations -chip size -pin number -external memory Memory organization -On and Off-chip memory size 44

45 Development tools: -software tools assemblers linkers simulators debuggers compilers -hardware tools development boards emulators 45

46 Cost: Least expensive DSPs have -fewer features -less on chip Memory -lower performance Chipset price depends on: -Packaging -Quantity 46

47 MAC using GPP R0 R X R2 44 Clr A ;Clear Accumulator A Clr B ; Clear Accumulator B Loop Mov *R0, Y0 ; Move data from memory location 1 to register Y0 Mov *R1,X0 ; Move data from memory location 2 to register X0 Mpy X0,Y0,A ;X0*Y0 ->A Add A,B ;A + B -> B Inc R0 ;R > R0 Inc R1 ;R > R1 Dec N ;Dec N (initially equals to 3) Tst N ;Test for the value Jnz Loop ;Different than zero loop again Mov B,*R2 ;Move result to memory 47

48 MAC using DSP Harvard Architecture allows multiple memory reads R X 24 9 Clr A ;Clear Accumulator A Rep N ; Rep N times the next instruction 44 MAC *(R0)+, *(R1)+, A ; Fetch the two memory locations pointed by R0 and R1, multiply them together and add the result to A, the final result is stored back in A Mov A, *R2 ; Move result to memory 48

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50 .mmregs.text Start: LACC #2345H LAR AR1,#8000H LAR AR2,#0fffH Loop: MAR *,AR1 SACL *+,AR2 BANZ Loop,*- HERE:B HERE.end 50

51 7/7/2013 TIFAC CORE IN NETWORK 51

52 TI 5000 SERIES TMS320C50 1. MICRO 50 ST 2. MICRO 50 LC 3. MICRO 50 EB TMS320VC MICRO MICRO 5416 AT 52

53 TMS 320C50 STARTER KIT 53

54 TMS 320C50 TRAINER KIT 54

55 C50 TRAINER KIT MONITOR EEPROM TIMER & SERIAL LOGIC SERIAL PORT TIMER PORT CONNECTOR BUS EXPANDER EXTERNAL DATA MEMORY EXTERNAL PROGRAM MEMORY BATTERY BACKUP C50 PROCESSOR HIGH SPEED ADC HIGH SPEED DAC Analog Output Analog Input RESET LOGIC (MICRO 50LC) 55

56 TMS320C50 KIT WITH FUNCTION GENERATOR 56

57 TMS 320C50 PROFESSIONAL TRAINER KIT 57

58 TMS 320VC5416 TRAINER KIT 58

59 TMS320VC5416 ADVANCED TRAINER KIT 59

60 TI 6000 SERIES TMS320C33 1. MICRO 33 TMS320C MICRO 6713 AT 60

61 TMS 320C33 TRAINER KIT 61

62 TMS320C6713 TRAINER KIT MICRO

63 TI 2000 SERIES TMS320F MICRO 240 TMS320F MICRO MICRO 2407 EB 63

64 TMS 320F240 TRAINER KIT 64

65 TMS 320F2407 TRAINER KIT 65

66 IPM UNIT 66

67 TMS 320F240 BASED MOTOR CONTROL 67

68 ANALOG DEVICES SERIES ADSP EZ KIT MICRO 81 AD ADSP 2189 ADSP MICRO 81 AT 1. MICRO 89 ST 2. MICRO 89 AT 1. MICRO 91 68

69 ADSP 2181 ADVANCED TRAINER KIT 69

70 ADSP 2181 TRAINER KIT 70

71 ADSP 2181 TRAINER KIT 71

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90 THANK YOU 90