Future Technology Devices International Ltd. FT201X

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1 Future Technology Devices International Ltd. FT201X (USB I2C SLAVE IC) The FT201X is a USB to I 2 C interface with the following advanced features: Single chip USB to I 2 C slave interface. Up to 3.4MHz, high speed mode, I 2 C supported Entire USB protocol handled on the chip. No USB specific firmware programming required. Fully integrated 2048 byte multi-timeprogrammable (MTP) memory, storing device descriptors and CBUS I/O configuration. Fully integrated clock generation with no external crystal required plus optional clock output selection enabling a glue-less interface to external MCU or FPGA. 512 byte receive buffer and 512 byte transmit buffer utilising buffer smoothing technology to allow for high data throughput. FTDI s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases. Configurable CBUS I/O pins. Transmit and receive LED drive signals. USB Battery Charger Detection. Allows for USB peripheral devices to detect the presence of a higher power source to enable improved charging. Device supplied pre-programmed with unique USB serial number. USB Power Configurations; supports buspowered, self-powered and bus-powered with power switching. Integrated +3.3V level converter for USB I/O. True 3.3V CMOS drive output and TTL input; Operates down to 1V8 with external pull-ups. Tolerant of 5V input. Configurable I/O pin output drive strength; 4 ma (min) and 16 ma (max). Integrated power-on-reset circuit. Fully integrated AVCC supply filtering - no external filtering required. + 5V Single Supply Operation. Internal 3V3/1V8 LDO regulators Low operating and USB suspend current; 8mA (active-typ) and 125uA (suspend-typ). UHCI/OHCI/EHCI host controller compatible. USB 2.0 Full Speed compatible. Extended operating temperature range; -40 to 85⁰C. Available in compact Pb-free 16 Pin SSOP and QFN packages (both RoHS compliant). Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Company Number: SC Copyright Future Technology Devices International Limited 1

2 1 Typical Applications Upgrading Legacy Peripherals to USB Utilising USB to add system modularity Incorporate USB interface to enable PC transfers for development system communication USB dongle implementations for Software/ Hardware Encryption and Wireless Modules Interfacing MCU/PLD/FPGA based designs to add USB connectivity USB Instrumentation Motherboard and system monitoring through USB USB Industrial Control USB Digital Camera Interface Ability to detect dedicated charging ports for high current charging of batteries in portable devices 1.1 Driver Support Royalty free VIRTUAL COM PORT (VCP) DRIVERS for... Windows 8 32,64-bit Windows 7 32,64-bit Windows Vista and Vista 64-bit Windows XP and XP 64-bit Windows Embedded Operating Systems Server 2003, XP and Server 2008 Windows CE 4.2, 5.0 and 6.0 Mac OS-X Linux 3.2 and greater Android Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 8 32,64-bit Windows 7 32,64-bit Windows Vista and Vista 64-bit Windows XP and XP 64-bit Windows Embedded Operating Systems Server 2003, XP and Server 2008 Windows CE 4.2, 5.0 and 6.0 Mac OS-X Linux 2.6 and greater Android The drivers listed above are all available to download for free from FTDI website ( Various 3rd party drivers are also available for other operating systems - see FTDI website ( for details. For driver installation, please refer to Part Numbers Part Number FT201XQ-x FT201XS-x Package 16 Pin QFN 16 Pin SSOP Note: Packing codes for x is: - R: Taped and Reel, (SSOP is 3,000pcs per reel, QFN is 5,000pcs per reel). - U: Tube packing, 100pcs per tube (SSOP only) - T: Tray packing, 490pcs per tray (QFN only) For example: FT201XQ-R is 5,000pcs taped and reel packing Copyright Future Technology Devices International Limited 2

3 1.3 USB Compliant The FT201X is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) (Rev D). Copyright Future Technology Devices International Limited 3

4 2 FT201X Block Diagram VCC 1V8 Internal Core Supply 3V3OUT 3.3 Volt LDO Regulator 1.8 Volt LDO Regulator FIFO RX Buffer (512 bytes) VCCIO SDA SCL USBDP USBDM USB Transceiver with Integrated 1.5k pullups and battery charge detection Serial Interface Engine (SIE) USB Protocol Engine I2C Controller CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 CBUS5 Internal MTP Memory USB DPLL FIFO TX Buffer (512 bytes) 3V3OUT Internal 12MHz Oscillator X4 Clock Multiplier 48MHz RESET# To USB Transceiver Cell Reset Generator Figure 2.1 FT201X Block Diagram For a description of each function please refer to Section 4. Copyright Future Technology Devices International Limited 4

5 Table of Contents 1 Typical Applications Driver Support Part Numbers USB Compliant FT201X Block Diagram Device Pin Out and Signal Description LD QFN Package QFN Package PinOut Description LD SSOP Package SSOP Package PinOut Description CBUS Signal Options Function Description Key Features Functional Block Descriptions I 2 C Interface Description Devices Characteristics and Ratings Absolute Maximum Ratings ESD and Latch-up Specifications DC Characteristics MTP Memory Reliability Characteristics Internal Clock Characteristics USB Power Configurations USB Bus Powered Configuration Self Powered Configuration USB Bus Powered with Power Switching Configuration Application Examples USB to I 2 C Converter USB Battery Charging Detection USB and I 2 C Interfacing Host Interface (USB) VCP and D2xx Interfaces Reading and Writing Data Copyright Future Technology Devices International Limited 5

6 9.2 I 2 C Interface Addressing Data Transfers Other I 2 C Commands Internal MTP Memory Configuration Default Values Methods of Programming the MTP Memory Programming the MTP memory over USB Programming the MTP memory over I 2 C Memory Map Hardware Requirements Protocol Address MTP memory (0x10) Write MTP memory (0x12) Read MTP memory (0x14) Examples of Writing and Reading Package Parameters SSOP-16 Package Mechanical Dimensions SSOP-16 Package Markings QFN-16 Package Mechanical Dimensions QFN-16 Package Markings Solder Reflow Profile Contact Information Appendix A References Document References Acronyms and Abbreviations Appendix B - List of Figures and Tables List of Figures List of Tables Appendix C - Revision History Copyright Future Technology Devices International Limited 6

7 VCC VCCIO 10 1 FT201X USB I2C SLAVE IC Datasheet 3 Device Pin Out and Signal Description LD QFN Package V3OUT USBDM USBDP RESET# SCL SDA CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 CBUS Figure 3.1 QFN Schematic Symbol QFN Package PinOut Description Note: # denotes an active low signal. Pin No. Name Type Description 10 ** VCC POWER Input 5 V (or 3V3) supply to IC 1 VCCIO POWER Input 1V8-3V3 supply for the IO cells 8 ** 3V3OUT POWER Output 3V3 output at 50mA. May be used to power VCCIO. When VCC is 3V3; pin 8 is an input pin. Connect to pin 10. 3, 13 POWER Input 0V Ground input. Table 3.1 Power and Ground *Pin 17 is centre pad beneath the IC. Connect to. ** If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input Pin No. Name Type Description 7 USBDM INPUT USB Data Signal Minus. 6 USBDP INPUT USB Data Signal Plus. 9 RESET# INPUT Reset input (active low). Table 3.2 Common Function pins Copyright Future Technology Devices International Limited 7

8 Pin No. Name Type Description 2 SDA I/O I 2 C bi-directional data line 16 SCL Input I 2 C clock input 12 CBUS0 I/O 11 CBUS1 I/O 5 CBUS2 I/O 14 CBUS3 I/O 4 CBUS4 I/O 15 CBUS5 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Table 3.3 I 2 C Interface and CBUS Group (see note 1) Notes: 1. When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = 1 ) by setting an option in the MTP memory. 2. Clock stretching is not supported Copyright Future Technology Devices International Limited 8

9 5 13 VCC VCCIO 12 3 FT201X USB I2C SLAVE IC Datasheet LD SSOP Package 10 3V3OUT SCL SDA USBDM USBDP RESET# CBUS0 CBUS1 CBUS2 CBUS3 CBUS4 CBUS Figure 3.2 SSOP Schematic Symbol SSOP Package PinOut Description Note: # denotes an active low signal. Pin No. Name Type Description 12 ** VCC POWER Input 5 V (or 3V3) supply to IC 3 VCCIO POWER Input 1V8-3V3 supply for the IO cells 10 ** 3V3OUT POWER Output 3V3 output at 50mA. May be used to power VCCIO. When VCC is 3V3, pin 10 is an input pin and should be connected to pin 12. 5, 13 POWER Input 0V Ground input. Table 3.4 Power and Ground ** If VCC is 3V3 then 3V3OUT must also be driven with 3V3 input Pin No. Name Type Description 9 USBDM INPUT USB Data Signal Minus. 8 USBDP INPUT USB Data Signal Plus. 11 RESET# INPUT Reset input (active low). Table 3.5 Common Function pins Copyright Future Technology Devices International Limited 9

10 Pin No. Name Type Description 4 SDA I/O I 2 C bi-directional data line 2 SCL Input I 2 C clock input 15 CBUS0 I/O 14 CBUS1 I/O 7 CBUS2 I/O 16 CBUS3 I/O 6 CBUS4 I/O 1 CBUS5 I/O Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Configurable CBUS I/O Pin. Function of this pin is configured in the device MTP memory. See CBUS Signal Options, Table 3.7. Table 3.6 Interface and CBUS Group (see note 1) Notes: 1. When used in Input Mode, the input pins are pulled to VCCIO via internal 75kΩ (approx.) resistors. These pins can be programmed to gently pull low during USB suspend (PWREN# = 1 ) by setting an option in the MTP memory. 2. Clock stretching is not supported Copyright Future Technology Devices International Limited 10

11 3.3 CBUS Signal Options The following options can be configured on the CBUS I/O pins. CBUS signal options are common to both package versions of the FT201X. These options can be configured in the internal MTP memory using the software utility FT_PROG, which can be downloaded from the FTDI Utilities ( The default configuration is described in Section 9. CBUS Signal Option Available On CBUS Pin Description TRI-STATE CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 IO Pad is tri-stated DRIVE 1 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Output a constant 1 DRIVE 0 CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Output a constant 0 PWREN# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Output is low after the device has been configured by USB, then high during USB suspend mode. This output can be used to control power to an external logic P- Channel logic level MOSFET switch. Enable the interface pull-down option when using the PWREN# in this way. SLEEP# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Goes low during USB suspend mode. Typically used to power down an external logic. CLK24MHz CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 24 MHz Clock output.* CLK12MHz CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 12 MHz Clock output.* CLK6MHz CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 6 MHz Clock output.* GPIO CBUS0, CBUS1, CBUS2, CBUS3, CBUS bit bang mode option. Allows up to 4 of the CBUS pins to be used as general purpose I/O. Configured individually for CBUS0, CBUS1, CBUS2 and CBUS3 in the internal MTP memory. A separate application note, AN232R-01, available from FTDI website ( describes in more detail how to use CBUS bit bang mode. BCD Charger CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Battery charge Detect, indicates when the device is connected to a dedicated battery charger host. Active high output. BCD Charger# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Inverse of BCD Charger (open drain) BitBang_WR# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Synchronous and asynchronous bit bang mode WR# strobe output. BitBang_RD# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Synchronous and asynchronous bit bang mode RD# strobe output. I2C_TXE# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Transmit buffer empty, used to indicate to I 2 C master device status of the FT201EX transmit buffer Copyright Future Technology Devices International Limited 11

12 CBUS Signal Option Available On CBUS Pin Description I2C_RXF# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Receive buffer full, used to indicate to I 2 C master device status of FT201EX receive buffer VBUS Sense CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Input to detect when VBUS is present. Time Stamp CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Toggle signal which changes state each time a USB SOF is received Keep_Awake# CBUS0, CBUS1, CBUS2, CBUS3, CBUS4, CBUS5 Prevents the device from entering suspend state when unplugged. May be used if programming the MTP memory over I2C Table 3.7 CBUS Configuration Control *When in USB suspend mode the outputs clocks are also suspended. Copyright Future Technology Devices International Limited 12

13 4 Function Description The FT201X is a USB to I 2 C interface device which simplifies USB implementations and reduces external component count by fully integrating into the device an EEPROM, and a clock circuit which requires no external crystal. It has been designed to operate efficiently with USB host controllers by using as little bandwidth as possible when compared to the total USB bandwidth available. 4.1 Key Features Functional Integration. Fully integrated MTP memory, clock generation, AVCC filtering, Power-On- Reset (POR) and LDO regulators. Configurable CBUS I/O Pin Options. The fully integrated MTP memory allows configuration of the Control Bus (CBUS) functionality and drive strength selection. There are 6 configurable CBUS I/O pins. These configurable options are defined in section 3.3. The device is shipped with the most commonly used pin definitions pre-programmed - see Section 9 for details. Asynchronous Bit Bang Mode with RD# and WR# Strobes. The FT201X supports FTDI s previous chip generation bit-bang mode. In bit-bang mode, the 2 I 2 C lines can be switched from the regular interface mode to a 2-bit general purpose I/O port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate pre-scalar). In the FT201X device this mode has been enhanced by outputting the internal RD# and WR# strobes signals which can be used to allow external logic to be clocked by accesses to the bit-bang I/O bus. This option will be described more fully in a separate application note available from FTDI website ( Synchronous Bit Bang Mode. The FT201X supports synchronous bit bang mode. This mode differs from asynchronous bit bang mode in that the interface pins are only read when the device is written to. This makes it easier for the controlling program to measure the response to an output stimulus as the data returned is synchronous to the output data. An application note, AN232R-01, available from FTDI website ( describes this feature. Source Power and Power Consumption. The FT201X is capable of operating at a voltage supply between +3.3V and +5.25V with a nominal operational mode current of 8mA and a nominal USB suspend mode current of 125µA. This allows greater margin for peripheral designs to meet the USB suspend mode current limit of 2.5mA. An integrated level converter within the I 2 C interface allows the FT201X to interface to UART logic running at +1.8V to +3.3V (5V tolerant). 4.2 Functional Block Descriptions The following paragraphs detail each function within the FT201X. Please refer to the block diagram shown in Figure 2.1 Internal MTP Memory. The internal MTP memory in the FT201X is used to store USB Vendor ID (VID), Product ID (PID), device serial number, product description string and various other USB configuration descriptors. The internal MTP memory is also used to configure the CBUS pin functions. The FT201X is supplied with the internal MTP memory pre-programmed as described in Section 9. A user area of the internal MTP memory is available to system designers to allow storing of additional data from the user application over USB. The internal MTP memory descriptors can be programmed in circuit, over USB without any additional voltage requirement. The descriptors can be programmed using the FTDI utility software called FT_PROG, which can be downloaded from FTDI Utilities on the FTDI website ( Additionally the MTP memory can be configured over the I 2 C interface. +1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8V reference voltage for driving the internal core of the IC. +3.3V LDO Regulator. The +3.3V LDO regulator generates the +3.3V reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides +3.3V power to the 1.5kΩ internal pull up resistor on USBDP. The main function of the LDO is to power the USB Transceiver and the Reset Generator Cells Copyright Future Technology Devices International Limited 13

14 rather than to power external logic. However, it can be used to supply external circuitry requiring a +3.3V nominal supply with a maximum current of 50mA. USB Transceiver. The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide +3.3V level slew rate control signalling, whilst a differential input receiver and two single ended input receivers provide USB data in, Single-Ended-0 (SE0) and USB reset detection conditions respectfully. This function also incorporates a 1.5kΩ pull up resistor on USBDP. The block also detects when connected to a USB power supply which will not enumerate the device but still supply power and may be used for battery charging. USB DPLL. The USB DPLL cell locks on to the incoming NRZI USB data and generates recovered clock and data signals for the Serial Interface Engine (SIE) block. Internal 12MHz Oscillator - The Internal 12MHz Oscillator cell generates a 12MHz reference clock. This provides an input to the x4 Clock Multiplier function. The 12MHz Oscillator is also used as the reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. Clock Multiplier / Divider. The Clock Multiplier / Divider takes the 12MHz input from the Internal Oscillator function and generates the 48MHz, 24MHz, 12MHz and 6MHz reference clock signals. The 48Mz clock reference is used by the USB DPLL and the Baud Rate Generator blocks. Serial Interface Engine (SIE). The Serial Interface Engine (SIE) block performs the parallel to serial and serial to parallel conversion of the USB data. In accordance with the USB 2.0 specification, it performs bit stuffing/un-stuffing and CRC5/CRC16 generation. It also checks the CRC on the USB data stream. USB Protocol Engine. The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol requests generated by the USB host controller and the commands for controlling the functional parameters of the I 2 C in accordance with the USB 2.0 specification chapter 9. FIFO RX Buffer (512 bytes). Data sent from the USB host controller to the I 2 C interface via the USB data OUT endpoint is stored in the FIFO RX (receive) buffer. Data is removed from the buffer to the I 2 C transmit register under control of the I 2 C Controller. (Rx relative to the USB interface). FIFO TX Buffer (512 bytes). Data from the I 2 C receive register is stored in the TX buffer. The USB host controller removes data from the FIFO TX Buffer by sending a USB request for data from the device data IN endpoint. (Tx relative to the USB interface). I 2 C Controller. Module to handle the latching in and out of serial data on the I 2 C interface. Supports up to 3.4MHz, High Speed Serial Mode. RESET Generator - The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT201X. RESET# can be tied to 3V3OUT. Copyright Future Technology Devices International Limited 14

15 5 I 2 C Interface Description I 2 C (Inter Integrated Circuit) is a multi-master serial bus invented by Philips. I 2 C uses two bi-directional open-drain wires called serial data (SDA) and serial clock (SCL). Common I²C bus speeds are the 100 kbit/s standard mode (SM), 400 kbit/s fast mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s High Speed mode (HS) An I 2 C bus node can operate either as a master or a slave: Master node issues the clock and addresses slaves Slave node receives the clock line and address. The FT201X device shall only be able to operate as a slave, but is capable of speeds up to 3.4MBit/s. There are four potential modes of operation for a given bus device, although most devices only use a single role and its two modes: Master transmit sending data to a slave Master receive receiving data from a slave Slave transmit sending data to a master Slave receive receiving data from the master The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. If the slave exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-tolow transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.) If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.) The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message"). I²C defines three basic types of message, each of which begins with a START and ends with a STOP: Single message where a master writes data to a slave; Single message where a master reads data from a slave; Combined messages, where a master issues at least two reads and/or writes to one or more slaves In a combined message, each read or write begins with a START and the slave address. After the first START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message. Please refer to the I 2 C specification for more information on the protocol. Copyright Future Technology Devices International Limited 15

16 6 Devices Characteristics and Ratings 6.1 Absolute Maximum Ratings FT201X USB I2C SLAVE IC Datasheet The absolute maximum ratings for the FT201X devices are as follows. These are in accordance with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause permanent damage to the device. Parameter Value Unit Conditions Storage Temperature -65 C to 150 C Degrees C Floor Life (Out of Bag) At Factory Ambient (30 C / 60% Relative Humidity) 168 Hours (IPC/JEDEC J- STD-033A MSL Level 3 Compliant)* Hours Ambient Operating Temperature (Power Applied) -40 C to 85 C Degrees C MTTF FT201XS TBD Hours MTTF FT201XQ TBD Hours VCC Supply Voltage -0.3 to +5.5 V VCCIO IO Voltage -0.3 to +4.0 V DC Input Voltage USBDP and USBDM -0.5 to V DC Input Voltage High Impedance Bi-directional (powered from VCCIO) -0.3 to +5.8 V DC Output Current Outputs 22 ma Table 6.1 Absolute Maximum Ratings * If devices are stored out of the packaging beyond this time limit the devices should be baked before use. The devices should be ramped up to a temperature of +125 C and baked for up to 17 hours. 6.2 ESD and Latch-up Specifications Description Specification Human Body Mode (HBM) > ± 2kV Machine mode (MM) > ± 200V Charged Device Mode (CDM) > ± 500V Latch-up > ± 200mA Table 6.2 ESD and Latch-Up Specifications Copyright Future Technology Devices International Limited 16

17 6.3 DC Characteristics DC Characteristics (Ambient Temperature = -40 C to +85 C) Parameter Description Minimum Typical Maximum Units Conditions VCC VCC2 Icc1 Icc2 VCC Operating Supply Voltage VCCIO Operating Supply Voltage Operating Supply Current Operating Supply Current V Normal Operation V ma Normal Operation 125 μa USB Suspend 3V3OUT 3.3v regulator output V VCC must be greater than 3V3 otherwise 3V3OUT is an input which must be driven with 3.3V Table 6.3 Operating Voltage and Current Copyright Future Technology Devices International Limited 17

18 Parameter Description Minimum Typical Maximum Units Conditions Ioh = -2mA 2.97 VCCIO VCCIO V I/O Drive strength* = 4mA Voh Output Voltage High 2.97 VCCIO VCCIO V I/O Drive strength* = 8mA 2.97 VCCIO VCCIO V I/O Drive strength* = 12mA 2.97 VCCIO VCCIO V I/O Drive strength* = 16mA Iol = +2mA V I/O Drive strength* = 4mA Vol Output Voltage Low V I/O Drive strength* = 8mA V I/O Drive strength* = 12mA V I/O Drive strength* = 16mA Vil Input low Switching Threshold 0.8 V LVTTL Vih Input High Switching Threshold 2.0 V LVTTL Vt Switching Threshold 1.49 V LVTTL Vt- Vt+ Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage 1.15 V 1.64 V Rpu Input pull-up resistance KΩ Vin = 0 Rpd Input pull-down resistance KΩ Vin =VCCIO Iin Input Leakage Current -10 +/-1 10 μa Vin = 0 Ioz Tri-state output leakage -10 +/-1 10 μa Vin = 5.5V or 0 current Table 6.4 I/O Pin Characteristics VCCIO = +3.3V (except USB PHY pins) * The I/O drive strength and slow slew-rate are configurable in the MTP memory. Copyright Future Technology Devices International Limited 18

19 Parameter Description Minimum Typical Maximum Units Conditions Ioh = +/-2mA 2.25 VCCIO VCCIO V I/O Drive strength* = 4mA Voh Output Voltage High 2.25 VCCIO VCCIO V I/O Drive strength* = 8mA 2.25 VCCIO VCCIO V I/O Drive strength* = 12mA 2.25 VCCIO VCCIO V I/O Drive strength* = 16mA Iol = +/-2mA V I/O Drive strength* = 4mA Vol Output Voltage Low V I/O Drive strength* = 8mA V I/O Drive strength* = 12mA V I/O Drive strength* = 16mA Vil Input low Switching Threshold 0.8 V LVTTL Vih Input High Switching Threshold 0.8 V LVTTL Vt Switching Threshold 1.1 V LVTTL Vt- Vt+ Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage 0.8 V 1.2 V Rpu Input pull-up resistance KΩ Vin = 0 Rpd Input pull-down resistance KΩ Vin =VCCIO Iin Input Leakage Current -10 +/-1 10 μa Vin = 0 Tri-state output leakage Ioz -10 +/-1 10 μa Vin = 5.5V or 0 current Table 6.5 I/O Pin Characteristics VCCIO = +2.5V (except USB PHY pins) * The I/O drive strength and slow slew-rate are configurable in the MTP memory. Copyright Future Technology Devices International Limited 19

20 Parameter Description Minimum Typical Maximum Units Conditions Ioh = +/-2mA 1.62 VCCIO VCCIO V I/O Drive strength* = 4mA Voh Output Voltage High 1.62 VCCIO VCCIO V I/O Drive strength* = 8mA 1.62 VCCIO VCCIO V I/O Drive strength* = 12mA 1.62 VCCIO VCCIO V I/O Drive strength* = 16mA Iol = +/-2mA V I/O Drive strength* = 4mA Vol Output Voltage Low V I/O Drive strength* = 8mA V I/O Drive strength* = 12mA V I/O Drive strength* = 16mA Vil Input low Switching Threshold 0.77 V LVTTL Vih Input High Switching Threshold 1.6 V LVTTL Vt Switching Threshold 0.77 V LVTTL Vt- Vt+ Schmitt trigger negative going threshold voltage Schmitt trigger positive going threshold voltage V V Rpu Input pull-up resistance KΩ Vin = 0 Rpd Input pull-down resistance KΩ Vin =VCCIO Iin Input Leakage Current -10 +/-1 10 μa Vin = 0 Ioz Tri-state output leakage -10 +/-1 10 μa Vin = 5.5V or 0 current Table 6.6 I/O Pin Characteristics VCCIO = +1.8V (except USB PHY pins) * The I/O drive strength and slow slew-rate are configurable in the MTP memory. Copyright Future Technology Devices International Limited 20

21 Parameter Description Minimum Typical Maximum Units Conditions Voh Output Voltage High 3V3OUT- 0.2 V Vol Output Voltage Low 0.2 V Vil Input low Switching Threshold V Vih Input High Switching Threshold V Table 6.7 USB I/O Pin (USBDP, USBDM) Characteristics 6.4 MTP Memory Reliability Characteristics The internal 2048 Byte MTP memory has the following reliability characteristics: Parameter Value Unit Data Retention 10 Years Write Cycle 2,000 Cycles Read Cycle Unlimited Cycles Table 6.8 MTP memory Characteristics 6.5 Internal Clock Characteristics The internal Clock Oscillator has the following characteristics: Parameter Value Minimum Typical Maximum Unit Frequency of Operation (see Note 1) MHz Clock Period ns Duty Cycle % Table 6.9 Internal Clock Characteristics Note 1: Equivalent to +/-1667ppm Copyright Future Technology Devices International Limited 21

22 7 USB Power Configurations The following sections illustrate possible USB power configurations for the FT201X. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT201XS and FT201XQ package options. All USB power configurations illustrated apply to both package options for the FT201X device. Please refer to Section 11 for the package option pin-out and signal descriptions. 7.1 USB Bus Powered Configuration 1 Ferrite Bead VCC VCC R 27R USBDM USBDP SHIELD 5 47pF 10nF 47pF RESET# FT201X VCCIO 3V3OUT A VCC 100nF + 4.7uF 100nF Figure 7.1 Bus Powered Configuration Figure 7.1 Illustrates the FT201X in a typical USB bus powered design configuration. A USB bus powered device gets its power from the USB bus. Basic rules for USB bus power devices are as follows i) On plug-in to USB, the device should draw no more current than 100mA. ii) In USB Suspend mode the device should draw no more than 2.5mA. iii) A bus powered high power USB device (one that draws more than 100mA) should use one of the CBUS pins configured as PWREN# and use it to keep the current below 100mA on plug-in and 2.5mA on USB suspend. iv) A device that consumes more than 100mA cannot be plugged into a USB bus powered hub. v) No device can draw more than 500mA from the USB bus. The power descriptors in the internal MTP memory of the FT201X should be programmed to match the current drawn by the device. A ferrite bead is connected in series with the USB power supply to reduce EMI noise from the FT201X and associated circuitry being radiated down the USB cable to the USB host. The value of the Ferrite Bead depends on the total current drawn by the application. A suitable range of Ferrite Beads is available from Laird Technologies ( for example Laird Technologies Part # MI0805K601R-10. Note: If using PWREN# (available using the CBUS) the pin should be pulled to VCCIO using a 10kΩ resistor. Copyright Future Technology Devices International Limited 22

23 7.2 Self Powered Configuration VCC( V) SHIELD k7 47pF 47pF 27R 27R VCC USBDM USBDP FT201X VBUS_SENSE 10k VCCIO RESET# 3V3OUT VCC A 100nF 100nF + 100nF 4.7uF Figure 7.2 Self Powered Configuration Figure 7.2 illustrates the FT201X in a typical USB self-powered configuration. A USB self-powered device gets its power from its own power supply, VCC, and does not draw current from the USB bus. The basic rules for USB self-powered devices are as follows i) A self-powered device should not force current down the USB bus when the USB host or hub controller is powered down. ii) A self-powered device can use as much current as it needs during normal operation and USB suspend as it has its own power supply. iii) A self-powered device can be used with any USB host, a bus powered USB hub or a selfpowered USB hub. The power descriptor in the internal MTP memory of the FT201X should be programmed to a value of zero (self-powered). In order to comply with the first requirement above, the USB bus power (pin 1) is used to control the VBUS_Sense pin of the FT201X device. When the USB host or hub is powered up an internal 1.5kΩ resistor on USBDP is pulled up to +3.3V, thus identifying the device as a full speed device to the USB host or hub. When the USB host or hub is powered off, VBUS_Sense pin will be low and the FT201X is held in a suspend state. In this state the internal 1.5kΩ resistor is not pulled up to any power supply (hub or host is powered down), so no current flows down USBDP via the 1.5kΩ pull-up resistor. Failure to do this may cause some USB host or hub controllers to power up erratically. Figure 7.2 illustrates a self-powered design which has a +3.3V to +5.25V supply. Note: 1. When the FT201X is in reset, the interface I/O pins are tri-stated. Input pins have internal 75kΩ pull-up resistors to VCCIO, so they will gently pull high unless driven by some external logic. Copyright Future Technology Devices International Limited 23

24 7.3 USB Bus Powered with Power Switching Configuration P Channel Power MOSFET Switched 5V Power to External Logic 100k 0.1uF 0.1uF 1k PWREN# 1 Ferrite Bead VCC SHIELD pF 47pF 27R 27R USBDM USBDP FT201X RESET# 10nF VCCIO 3V3OUT CBUS3 A VCC 100nF + 4.7uF 100nF Figure 7.3 Bus Powered with Power Switching Configuration A requirement of USB bus powered applications, is when in USB suspend mode, the application draws a total current of less than 2.5mA. This requirement includes external logic. Some external logic has the ability to power itself down into a low current state by monitoring the PWREN# signal. For external logic that cannot power itself down in this way, the FT201X provides a simple but effective method of turning off power during the USB suspend mode. Figure 7.3 shows an example of using a discrete P-Channel MOSFET to control the power to external logic. A suitable device to do this is an International Rectifier ( IRLML6402, or equivalent. It is recommended that a soft start circuit consisting of a 1kΩ series resistor and a 0.1μF capacitor is used to limit the current surge when the MOSFET turns on. Without the soft start circuit it is possible that the transient power surge, caused when the MOSFET switches on, will reset the FT201X or the USB host/hub controller. The soft start circuit example shown in Figure 7.3 powers up with a slew rate of approximaely12.5v/ms. Thus supply voltage to external logic transitions from to +5V in approximately 400 microseconds. As an alternative to the MOSFET, a dedicated power switch IC with inbuilt soft-start can be used. A suitable power switch IC for such an application is the Micrel ( MIC2025-2BM or equivalent. With power switching controlled designs the following should be noted: i) The external logic to which the power is being switched should have its own reset circuitry to automatically reset the logic when power is re-applied when moving out of suspend mode. ii) Set the Pull-down on Suspend option in the internal FT201X MTP memory. iii) One of the CBUS Pins should be configured as PWREN# in the internal FT201X MTP memory, and used to switch the power supply to the external circuitry. iv) For USB high-power bus powered applications (one that consumes greater than 100mA, and up to 500mA of current from the USB bus), the power consumption of the application must be set in the Max Power field in the internal FT201X MTP memory. A high-power bus powered application uses the descriptor in the internal FT201X MTP memory to inform the system of its power requirements. v) PWREN# gets its VCC from VCCIO. For designs using 3V3 logic, ensure VCCIO is not powered down using the external logic. In this case use the +3V3OUT. Copyright Future Technology Devices International Limited 24

25 8 Application Examples The following sections illustrate possible applications of the FT201X. The illustrations have omitted pin numbers for ease of understanding since the pins differ between the FT201XS and FT201XQ package options. 8.1 USB to I 2 C Converter 1 Ferrite Bead VCC VCC SCL SCL SHIELD pF 10nF 47pF 27R 27R USBDM USBDP FT201X RESET# VCCIO 3V3OUT SDA SDA 1k VCCIO 1k I2C MASTER DEVICE A VCC 100nF + 4.7uF 100nF Figure 8.1 Application Example showing USB to I 2 C Converter An example of using the FT201X as an I 2 C peripheral is shown in Figure 8.1. The FT201X is the slave on the I 2 C bus. Therefore the clock supplied to the SCL pin must come from the I 2 C Master. The device will support standard I 2 C data rates such as 100 kbit/s standard mode (SM), 400 kbit/s fast mode (FM), 1 Mbit/s Fast mode plus (FM+), and 3.4 Mbit/s High Speed mode (HS). The data line SDA is bi- directional. The master is initially in master transmit mode by sending a start bit followed by the 7-bit address of the slave it wishes to communicate with, which is finally followed by a single bit representing whether it wishes to write(0) to or read(1) from the slave. If the slave (FT201X) exists on the bus then it will respond with an ACK bit (active low for acknowledged) for that address. The master then continues in either transmit or receive mode (according to the read/write bit it sent), and the slave continues in its complementary mode (receive or transmit, respectively). The address and the data bytes are sent most significant bit first. The start bit is indicated by a high-tolow transition of SDA with SCL high; the stop bit is indicated by a low-to-high transition of SDA with SCL high. If the master wishes to write to the slave then it repeatedly sends a byte with the slave sending an ACK bit. (In this situation, the master is in master transmit mode and the slave is in slave receive mode.) If the master wishes to read from the slave then it repeatedly receives a byte from the slave, the master sending an ACK bit after every byte but the last one. (In this situation, the master is in master receive mode and the slave is in slave transmit mode.) The master then ends transmission with a stop bit, or it may send another START bit if it wishes to retain control of the bus for another transfer (a "combined message"). I²C defines three basic types of message, each of which begins with a START and ends with a STOP: Copyright Future Technology Devices International Limited 25

26 Single message where a master writes data to a slave; Single message where a master reads data from a slave; FT201X USB I2C SLAVE IC Datasheet Combined messages, where a master issues at least two reads and/or writes to one or more slaves In a combined message, each read or write begins with a START and the slave address. After the first START, these are also called repeated START bits; repeated START bits are not preceded by STOP bits, which is how slaves know the next transfer is part of the same message. The I 2 C address of the FT201X is stored in the device internal MTP memory. Please refer to the I 2 C specification for more information on the protocol. 8.2 USB Battery Charging Detection A recent addition to the USB specification ( is to allow for additional charging profiles to be used for charging batteries in portable devices. These charging profiles do not enumerate the USB port of the peripheral. The FT201X device will detect that a USB compliant dedicated charging port (DCP) is connected. Once detected while in suspend mode a battery charge detection signal is provided to allow external logic to switch to charging mode as opposed to operation mode. To use the FT201X with battery charging detection the CBUS pins must be reprogrammed to allow for the BCD Charger output to switch the external charger circuitry on. The CBUS pins are configured in the internal MTP memory with the free utility FT_PROG. If the charging circuitry requires an active low signal to enable it, the CBUS pin can be programmed to BCD Charger# as an alternative. When connected to a USB compliant dedicated charging port (DCP, as opposed to a standard USB host) the device USB signals will be shorted together and the device suspended. The BCD charger signal will bring the LTC4053 out of suspend and allow battery charging to start. The charge current in the example below is 1A as defined by the resistance on the PROG pin. VBUS 3V3OUT VBUS 3V3OUT VBUS 3V3OUT CN USB 1 VBUS 2 D- 3 D+ 4 ID 5 600R/2A 27R 27R 3V3OUT DM DP RESET# VCC VCCIO 0.1uF 0.1uF 10nF N.F. 0R 0.1uF CBUS0 BCD SLD FT201X VBUS VBUS VBUS VBATT 0.1uF 4.7uF CHRG VCC FAULT TIMER 10 ACPR 9 BAT SHDN 8 PROG 7 6 NTC BCD NTC 1 + NCT - TB3.5mm 0.1uF 11 LTC4053EDD 2K2 1K5 1uF 1R EEPROM Setting X-Chip Pin CBUS0 Function BCD Battery Options Battery Charger Enable Force Power Enable De-acticate Sleep X VBUS JUMPER-2mm 4K32 1% NTC 1A when connected to a dedicated charger port 0A when enumerated 0A when not enumerated and not in sleep 0A when in sleep JP1 SIP-3 JP1 NCT Available NCT Enabled NCT Disabled (Default) Copyright Future Technology Devices International Limited 26

27 Figure 8.2 USB Battery Charging Detection (1- pin) Alternatively the PWREN# And SLEEP pins may be used to control the LTC4053 such that a battery may be charged from a standard host (low current) or from a dedicated charging port (high current). In such a design as shown below the charge current would need to be limited to 0.4A to ensure that the USB host power limit is not exceeded. VBUS 3V3OUT VBUS 3V3OUT VBUS 3V3OUT CN USB 1 VBUS 2 D- 3 D+ 4 ID 5 600R/2A 27R 27R U1 3V3OUT DM DP RESET# VCORE VCC VCCIO 0.1uF 0.1uF 10nF SLD 0R N.F. 0.1uF CBUS5 CBUS6 FT201X SLEEP# PWREN# VBUS VBUS VBUS VBATT 0.1uF 4.7uF 0.1uF CHRG VCC FAULT TIMER ACPR 9 BAT SHDN 8 PROG 7 6 NTC LTC4053EDD 2K2 SLEEP# NTC 16K5 1% 4K32 1% 1uF 1 + NCT - TB3.5mm PWREN# 1R EEPROM Setting X-Chip Pin CBUS5 CBUS6 Function SLEEP# PWREN# Battery Options Battery Charger Enable Force Power Enable De-acticate Sleep X X X VBUS JUMPER-2mm 4K32 1% 0.4A when connected to a dedicated charger port 0.4A when enumerated 0.1A when not enumerated and not in sleep mode 0A when in sleep mode NTC JP1 SIP-3 JP1 NCT Available NCT Enabled NCT Disabled (Default) Figure 8.3 USB Battery Charging Detection (2- pin) In the example above the FT201X SLEEP pin is used to enable/disable the LTC4053, while the PWREN# signal alters the charging current by altering the resistance on the LTC4053 PROG pin. A third option shown in the example below uses the SLEEP signal from the FT201X to enable / disable the battery charger. The BCD# and PWREN# signals are then used to alter the resistance on the PROG pin of the LTC4053 which controls the charge current drawn from the USB connector. Copyright Future Technology Devices International Limited 27

28 VBUS 3V3OUT VBUS 3V3OUT VBUS 3V3OUT CN USB 1 VBUS 2 D- 3 D+ 4 ID 5 600R/2A 27R 27R 3V3OUT DM DP RESET# VCC VCCIO 0.1uF 0.1uF N.F. 0R 10nF 0.1uF CBUS0 CBUS1 CBUS FT201X BCD# PWREN# SLEEP# SLD VBUS VBUS VBUS VBATT 0.1uF 4.7uF CHRG VCC FAULT TIMER 10 ACPR 9 BAT SHDN 8 PROG 7 6 NTC SLEEP# NTC 1 + NCT - TB3.5mm 0.1uF 11 LTC4053EDD 2K2 16K5 1% 4K32 1% 1K5-1% 1uF PWREN# BCD# 1R EEPROM Setting X-Chip Pin CBUS0 CBUS1 CBUS2 Function BCD# PWREN# SLEEP# Battery Options Battery Charger Enable X Force Power Enable De-acticate Sleep X VBUS 4K32 1% JUMPER-2mm NTC JP1 SIP-3 1A when connected to a dedicated charger port 0.4A when enumerated 0.1A when not enumerated and not in sleep 0A when in sleep JP1 NCT Available NCT Enabled NCT Disabled (Default) Figure 8.4 USB Battery Charging Detection (3 - pin) To calculate the equivalent resistance on the LTC4053 PROG pin select a charge current, then Res = 1500V/I chg For more configuration options of the LTC4053 refer to: AN_175_Battery Charging Over USB Note: If the FT201X is connected to a standard host port such that the device is enumerated the battery charge detection signal is inactive as the device will not be in suspend. Copyright Future Technology Devices International Limited 28

29 9 USB and I 2 C Interfacing This section covers the transfer of data from USB to I 2 C and vice versa. Please note that the FT200XD and FT201X are I 2 C slave devices only and should be interfaced to an I 2 C host (often in a microcontroller or FPGA). If an I 2 C master is required, please see the FT232H, FT2232H, FT4232H and FT2232D devices. This section covers transfer of data only. The USB and I 2 C interfaces on the FT200XD and FT201X can also be used for programming of the MTP memory, which is covered in a separate section. Throughout this section, the reference FT-X applies to the FT200XD and FT201X devices, as the other members of the FT-X family do not have I 2 C interfaces. 9.1 Host Interface (USB) From the host computer s point of view, the I 2 C data can be sent and received in the same way as when interfacing to one of the standard UART devices such as the FT232R. The FT-X handles the entire I 2 C protocol inside the chip and so reading and writing data does not require any special programming from the PC side. It can be treated as a simple data bridge VCP and D2xx Interfaces Like the other FTDI devices, the host can use D2xx commands or can use a Virtual COM Port (VCP) to communicate with the device. D2xx Interface The D2xx method allows the application software to use the functions in the FTDI D2xx library to communicate directly with the device. This is a library provided free-of-charge by FTDI and is available within the driver download files at the link below. It includes functions to find the FTDI devices on the system, open a particular device, send data to the device and read data from the device. Any data written using FT_Write, for example, will be sent to the FT-X chip and will be available for the external I 2 C Master to read. As mentioned above, only the data itself needs to be sent as the FT-X handles all of the I 2 C specific protocol. There are many other functions available, and full details can be found in the D2xx Programmers Guide. Virtual COM Port Interface If using the Virtual Com Port (VCP), the device will appear as if it were a real COM port on the computer. This is useful where an application has already been written to use an RS232 port on the computer as it allows that application to treat the FT-X as if it were a real COM port. This port can be opened in a terminal program or a custom application in the same way as a serial port would be opened. Data can then be sent or received using standard serial / COM port functions. No I 2 C decoding is required as the chip itself handles the I 2 C protocol. Because of this, even I 2 C versions of the FT-X family can be used with the VCP interface. Any data which the host PC sends to the Virtual COM Port (for example, typed into the terminal window in HyperTerminal) will be sent over USB to the FT-X and can then be read by the external I 2 C Master. Likewise, any data written to the FT-X over I 2 C will be sent to the PC where the terminal program will display it. Since the FT-X is the I 2 C slave and does not generate a clock signal, the settings such as baud rate and handshaking do not have any effect. Copyright Future Technology Devices International Limited 29

30 D2xx and VCP Interface under Windows In Windows systems, the VCP driver is actually an additional layer on top of the D2xx driver. The D2xx driver is always loaded and the VCP later may or may not be loaded on top of it, depending on the requirements of the application. When VCP is disabled, the device will appear only under Universal Serial Bus Controllers in the Device Manager and no COM port is exposed. When the VCP is enabled, the device will appear under both the Universal Serial Bus Controllers and the Ports (COM & LPT) sections in Device Manager. The VCP interface will be disabled by default in the FT200XD and FT201X but can be enabled in one of the following ways: - An option bit in the MTP memory on the chip is checked each time that the device is enumerated, and can cause the host computer to load the VCP layer. This allows each individual hardware unit to enable or disable VCP as per its requirements. The MTP information in section 10 has further details. FT_Prog can also be used to modify the MTP settings. - The user may open the Properties for the device under Universal Serial Bus Controllers in Device Manager in Windows and tick a box to load the VCP. Re-enumeration of the FT-X is necessary to enable the new setting. - By editing the driver FtdiBus.inf file (please refer to AN_107). Note that the FT_INF utility available from the FTDI website can be used to help create the modified inf files. In other Operating systems (e.g. Linux, Mac and Windows CE), there are separate drivers for D2xx and VCP, and only one of these drivers may be installed at any time. Therefore, the mode is selected by installing the associated driver instead and the selection defined in the bullet points above has no effect Reading and Writing Data Data from FT-X to the Host When data is to be sent from the host computer to the external I 2 C master, the software application writes this data to the FTDI driver using VCP or D2xx and this data is sent by the driver over USB to the buffer in the device. The external I 2 C master device may then perform an I 2 C read (Master receiver, Slave transmitter) operation to retrieve the data. The external I 2 C master should check if data is available to ensure that the data which has been read is valid. The methods for this are described in section below. Data from Host to the FT-X When data is to be sent from the external I 2 C master to the host computer, the external master performs an I 2 C write (Master transmitter, Slave receiver) operation to the FT-X. The FT-X stores this in its buffer and the data is sent back to the driver on the host computer over USB. As with other FTDI devices, this happens when either the buffer in the device fills or when the latency timer rolls over (so that partially filled buffers do not wait indefinitely), whichever happens first. Note that when writing data to the FT-X over I 2 C, the external master should check whether there is space available in the buffer inside the FT-X. It can do this using the methods shown in section below. The host computer application can then read the data from the driver buffer using the VCP interface or the D2xx commands. In the case of D2xx, the number of bytes available may be determined using the FT_GetQueueStatus command before doing the FT_Read. Copyright Future Technology Devices International Limited 30

31 9.2 I 2 C Interface From an I 2 C point of view, the FT-X behaves as a standard I 2 C slave. Data transfers take the same form as a standard I 2 C communication. In addition to reading and writing, there are some other commands which can be used to determine the status of the device and these are covered in this section and in further detail in section 9.3. Note: This section uses 7-bit addressing in the examples. It uses eight characters to describe the seven address bits and the single read/write bit. For example, means address 0x73 with the Read/Write bit set to 1, and therefore corresponds to a read of address 0x73. Data values are represented in bytes, for example, for data value 0xA Addressing The FT-X can be given a custom slave address on the I 2 C bus. This is stored in MTP memory and can be re-programmed over USB or I 2 C. Please see the separate MTP Programming information in section 10. The slave address is used when reading and writing to the device. The FT-X supports both 7-bit and 10- bit addressing. The general call address ( ) is for addressing every device on the bus. Some slaves do not support the General Call Address though the FT-X devices do support it. They will acknowledge this address, receive the second byte and interpret it. There are several commands available for this second byte. The FT-X will support the Software Reset command which is part of the I2C specification as well as other custom FTDI commands. These are covered in more detail later in the Other I2C Commands section Data Transfers Reading and Writing For all I 2 C data transfers to and from the FT-X, the slave address of the FT-X is used. The figure below shows a typical 7-bit address transfer for each direction. Figure 9.1: Data transfers using 7-bit addressing Copyright Future Technology Devices International Limited 31

32 The figure below summarises all of the transfers available (7-bit and 10-bit addressing). Figure 9.2: Data transfers with 7-bit and 10-bit addressing modes Flow Control when Reading When reading data, it is important to know if there is data available to read over I 2 C and if the data read is valid. There are three methods by which to check whether the data being read is valid. - Checking the I2C_TXE# line, which indicates whether the transmit buffer is empty. This signal can be mapped to the CBUS pins. This line does not indicate the number of bytes available. If the line is asserted, there are one or more bytes in the transmit buffer. Note that the Transmit buffer is the buffer which holds data which has come from the host computer and is going to be read by the external I 2 C master. - Do a read over I 2 C (Master receiver, Slave transmitter) and check whether the FT-X acknowledges the address phase. The FT-X will NAK the address phase if there is no data to read. - If bursting data, then there is not an address phase for each byte. In this case, it is not possible to tell when the buffer has emptied and therefore when you are no longer reading valid bytes. In this case, a Data Available check can be carried out first. If the byte after the general call address is 0x0C ( ), the FT-X returns the Data Available Count to indicate the number of bytes available for burst read. Please also refer to section 9.3. Note that because this returns a single byte, the maximum value is 0xFF, and so a value of 0xFF indicates that there are 255 or more bytes available. Figure 9.3: Checking the Data Available Count Flow Control when Writing Copyright Future Technology Devices International Limited 32

33 When writing data (data going from I 2 C toward the host computer), it is important to check if there is space available and if the FT-X accepted the byte written. There are two methods by which to check whether space is available. - Check the I2C_RXF# line, which indicates whether the Receive buffer is full. This line indicates that there is at least one empty byte available in the buffer. However, there is no indication of how many bytes are available. This signal can be mapped to the CBUS pins. Note that the Receive buffer is the buffer which holds data which has come from the external I 2 C master and is going to the host computer over USB. - Do a write over I 2 C (Master transmitter, Slave receiver) and check if the FT-X ACKs. The FT-X will NAK if there is no space in the buffer for the data to be written into. The FT-X will NACK in the address phase if this is the first byte being written and there is no space available. If the buffer becomes full during a burst write, the FT-X will NACK any bytes during the data phase which cannot be accommodated in the buffer. Note that because the acknowledgement can be checked for each byte written (since the FT-X slave is generating the acknowledge when writing to it), there is no command to ask the FT-X how much buffer space is available. 9.3 Other I 2 C Commands Soft reset This uses the General Call Address. If the second byte is 0x06 ( ) it will be interpreted by the FT-X as the Soft Reset command, which clears all buffers. Flush command This uses the General Call Address. If the second byte is 0x0E ( ) it will be interpreted by the FT-X as the Flush command and the Transmit and Receive buffers will be flushed of all data. Figure 9.4: Flush data command Read Data Available command This uses the General Call Address. If the second byte is 0x0C ( ) it will be interpreted by the block as the Read Data Available command and on the next I 2 C read cycle following this command, the data will hold the number of bytes available for burst read. Figure 9.5: Reading the amount of data available USB State command This uses the General Call Address. If the second byte is 0x16 ( ) it will be interpreted by the block as the USB State command and on the next read cycle following this command, the data will hold the coded USB State value. The USB state allows you to check the current USB enumeration state: 0x00 = Suspended. 0x01 = Default. Copyright Future Technology Devices International Limited 33