Design and Implementation of MP3 Player Based on FPGA Dezheng Sun

Transcription

1 Applied Mechanics and Materials Online: ISSN: , Vol. 443, pp doi: / Trans Tech Publications, Switzerland Design and Implementation of MP3 Player Based on FPGA Dezheng Sun College of Information Science and Engineering, Northeastern University, Shenyang , China Keywords: Mp3 Player,, FPGA Abstract. The paper adopts a method of a low speed processer and FPGA based hardware accelerator SOC units to develop the MP3 player, added with some peripheral devices. The experimental results show that the system has implemented the basic functions of the MP3 player, having its own advantage on increasing the decoding speed and reducing the system consumption. The system is convenient to redesign for more function in the future because it s designed based on FPGA. In conclusion, it has a wide application prospect. Introduction The MP3 player is not only small size, light weight, large storage capacity and small power consumption. With increasing memory capacity and price continue to lower, MP3 players, car and portable audio field, more and more people are welcome, especially in the field of portable audio, MP3 players have occupied the absolute mainstream position, so the MP3 player is great application significance [1]. MP3 player performance mainly depends on the performance system with MP3 decoder, MP3 decoder system [2]; there are two main MP3 software decoding algorithms to optimize the design and MP3 hardware decoding study, Low-speed core processors and other hardware acceleration module SOC (System on a Chip, SoC) design and the external device to achieve [3]. MP3 Decoding Process Analysis MP3 decoding process shown in Fig. 1, the decoding process includes the extract stream synchronization (in units of frames) Huffman decoding, the scale factor decoding, inverse quantization, re-arrangement of the stereo processing, aliasing reconstruction IMDCT transform, sub-with integrated filter synthesis, the final output of the original PCM data. In the decoding process, the more time-consuming IMDCT and sub band filtering the two elements. Compiled, they occupy a considerable number of hardware resources; power consumption is particularly high for both the design computationally intensive algorithm IMDCT, sub-band synthesis filter to do hardware acceleration to improve overall system performance. IMDCT algorithm has long block and short block, long block input calculation is 18:00 short block input is 6:00, the length of the block input values are not 2 ^ n, so you can use the fast algorithm of Szu Wei, Lee, this the algorithm for the larger operations of input points, the faster the more obvious. Traditional IMDCT algorithm needed in the calculation of the long block is 36 * 18 multiplications and 36 * 17 addition, Szu Wei, Lee algorithm, the calculation of the long block only 43 multiplications and 115 additions, the operation speed of the program significantly improved. Calculated directly in the design sub-band filter, you need to perform 32 * 64 multiplication and 31 * 64 addition, the two-channel sampling rate of 44.1KHz, the multiplication capacity of (44100/32) * (64 * ) * 2 = million times / sec, while the system clock is generally used is 50MHz single cycle occupied 58.2% of the entire decoding time, seriously affecting the rate of decoding of the entire system. Therefore, according to the symmetry of the cosine function, combined with of Beyond of Gi Lee, the fast DCT algorithm to improve, improved sub-band integrated filter only needs 384 multiplications and 376 additions greatly enhance the speed of operation. All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications, (ID: , Pennsylvania State University, University Park, USA-09/05/16,22:17:51)

2 Applied Mechanics and Materials Vol The Hardware Design of the System Nios II-based embedded system mainly consists of three parts: IP library (the Nios II soft core processor, the Avalon bus peripheral interface), GNUPro software compiler, SOPC Builder development tool. Altera Corporation, CycloneII FPGA chip used in hardware design, model EP2C70F896C6 main peripheral equipment, including off-chip SDRAM memory, SD card, audio chips, WM8731, the LCD, the FPGA chip to complete the various hardware modules and data flow control chip memory to store program data and code execution, SD cards to store MP3 files, audio chip, the PCM data stream output, LCD display system status, IP core reuse is the key to the SOPC design. The hardware system architecture shown in Fig 2 Internal FPGA logic design is based on Quartus II development environment to the Verilog language programming, audio control, SD card reader, LCD drivers and other function modules. SOPC Builder configuration and Nios II soft core processor and the necessary peripherals, and then re-compile, download the configuration of the FPGA chip to form a connection of the hardware logic circuit, and finally verify that the system in order to achieve the output of MP3 audio files. In addition to the audio module, SD card control module, LCD display to the other modules in the drive module through SOPC Builder to add the IP core build. As for the child in the MP3 decoding algorithm with integrated filter, IMDCT transform two parts dealing with them the special time-consuming, against such time-consuming problem, you can use the software and hardware co-processing more time-consuming part of the hardware acceleration (software, often several times faster than the speed of processing of the original software.) to improve the entire system run time. This design method can be determined, in the consolidated mutual constraint relationship between the system software and hardware in order to ensure certainty, efficiency of the system. MP3 stream Frame synchronization and Error header information decoder Huffman Scale factor Inverse Quantization Re-arranged Left Audio PCM Stream Comes with Comprehensive filtering Right Audio PCM Stream Comes with Comprehensive filtering IMDCT IMDCT Aliasing Reconstruction Aliasing Reconstruction Stereo Processing Fig. 1 MP3 MP3 Audo Decode System Key Module MP3 Audio MP3 Audio Play Module Core Processing Module SD Card Module Display Module Fig. 2 MP3 Player Overall Function Structure Diagram

3 748 Computer-Aided Design, Manufacturing, Modeling and Simulation III System Software Design Configure Niosn Soft-Core System Modules Altera Corporation provide the SOPCBullder of development tools, you can very easily customize the system retaining nuclear. MP3 player system needs to configure the hardware logic of NIOSH, configured processor shown in Figure 4.2, on in eyelone11ep2c70f896c6 chips to achieve a soft core epu Nios11, OnChipRAM, and digital interface Nios11 soft-core CPU and Ip the module of ltrj by Avalon on-chip bus is connected. The purpose is to configure the soft-core processor of Niosn to use Ni0SH processor system to coordinate the work of the whole system. Shown in Fig. 3 Fig. 3 Configured Nios 2 soft-core system block diagram Huflhlan Decoding Module Since the Huffillan coding is carried out to quantify the value of the frequency domain, usually a large value is mainly concentrated in the low frequency part, and zero values are concentrated in the high frequency part, so each band the flexibility to choose a higher coding efficiency Huffillan table. Huffizzan decoding module function is to decode the compressed data input derived scaling factor (scalefactor); Then, in the process of decoding Huffinan, the use of side information obtained from the synchronization information processing module, draw Hu while an decoding required information, and then look for the advance in the ROM, built the corresponding Huffinan table, the final output of the original 576 frequency lines in the frequency domain to quantify value. These outputs are used for the next processing module - inverse quantization module. The overall decoding process is the Start of '1 'to done is set to '1' end, which quantify the value of the frequency domain to store the primary storage area to Huffinan module to facilitate debugging and inverse quantization module call. Fig. 4 is Huffnian decoding module data flow diagram. Fig. 4 Data flow diagram of Huffman decoding module The code is: Huffmancodebits () { For (l=o; l < big_ values*2; l+=2) Hcod [ x ] [ y ]

4 Applied Mechanics and Materials Vol If ( x ==15&&linbits>O) linbitsx If (x! = 0) signx If ( y ==15&&limits>O) linbitsy If (y! = 0) sign Is l =x If [l + l] =y For (: l<big_ values*2+countl*4; 1+=4) { Hcod [ v ] [ w ] [ y ] If (v! =0) sign If (w! =0) signw If (x! =0) signx If (y! =0) signy Is [1] =v Is [l+ l] =w Is [l+2] =x Is [l+3] =y For (; 1<576; l++) Is [1] =O Conclusions This is the MP3 decoder design based on SOPC technology, its advantages is that the system functions to improve flexibility, that does not change the circumstances of the hardware platform, casual, additions or deletions to the system and optimize to reduce the cost of the system, which is the other programs difficult to compare. Hardware decoding system using Verilog HDL language to describe, after the RTL-level simulation and verification, the Cyclone II device within EP2C8Q208 resources occupancy rate of 8% total register for the 3335 system frequencies up to 72MHz, the actual test, the design to achieve the desired effect. But there are still some places for improvement and could be improved, and this is also after the MP3 player design need to improve and focus of the study: (1) This design features simple, compiled FPGA chip resources occupied by relatively small, further increase in other functions, such as image display. (2) How to improve a more efficient algorithm to improve system uptime, reduce power consumption in order to achieve portable high performance, low power requirements, this is the future of MP3 design focus of the study. References [1] Eilert, J.Ehliaf, A., Dake Liu, Using low Precision floating Point numbers to reduce memory eost for MP3 decoding, Multimedia Signal Professing, IEEE 6th Workshop on 22 (44), (2004) [2] TaghiPour, H., Frounehi, J., Zarifi, M.H, Design and implementation of MP3 decoder using Partial dynamic reconfiguration on Virtex-4 FPGAs, Computer and Communication Engineering 34(15), (2008) [3] Nam, S.J., Kim, B.H., Im, C.D., Kim, J.B., Lee, S.J., Jeong, S.S., Kim, J.K., Park, S.J, a low Power MPEG1/11 layer 3 audiodeeoder, Circuits and Systems 2(55), (2001)

5 Computer-Aided Design, Manufacturing, Modeling and Simulation III / Design and Implementation of MP3 Player Based on FPGA /