XC95288 In-System Programmable CPLD

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1 0 XC95288 In-System Programmable CPLD November 12, 1997 (Version 2.0) 0 3* Preliminary Product Specification Features 15 ns pin-to-pin logic delays on all pins f CNT to 95 MHz 288 macrocells with 6,400 usable gates Up to 192 user pins 5 V in-system programmable - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18-90 product terms drive any or all of 18 macrocells within - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 ma outputs 3.3 V or 5 V capability PCI compliant ( -10 speed grade) Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 352-pin BGA and 208-pin HQFP packages Description The XC95288 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of sixteen 36V18 s, providing 6,400 usable gates with propagation delays of 10 ns. See Figure 2 for the architecture overview. Power Management Power dissipation can be reduced in the XC95288 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: I CC (ma) = MC HP (1.7) + MC LP (0.9) + MC (0.006 ma/mhz) f Where: MC HP = s in high-performance mode MC LP = s in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) 900 Typical I CC (ma) 600 High Performance (500) (500) Low Power Clock Frequency (MHz) 100 Figure 1: Typical I CC vs. Frequency For XC95288 (700) X7131 November 12, 1997 (Version 2.0) 3-59

2 XC95288 In-System Programmable CPLD JTAG Port 1 3 JTAG Controller In-System Programming Controller s 1 to 18 /GCK /GSR /GTS s FastCONNECT Switch Matrix s 1 to 18 3 s 1 to 18 4 s 1 to s 1 to 18 Figure 2: XC95288 Architecture X5924 Note: outputs (indicated by the bold line) drive the s directly 3-60 November 12, 1997 (Version 2.0)

3 Absolute Maximum Ratings Symbol Parameter Value Units V CC Supply voltage relative to GND -0.5 to 7.0 V V IN DC input voltage relative to GND -0.5 to V CC V V TS Voltage applied to 3-state output with respect to GND -0.5 to V CC V T STG Storage temperature -65 to +150 C T SOL Max soldering temperature (10 1/16 in = 1.5 mm) +260 C Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions 1 Symbol Parameter Min Max Units V CCINT Supply voltage for internal logic and input buffer V (4.5) (5.5) V CCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V Supply voltage for output drivers for 3.3 V operation V V IL Low-level input voltage V V IH High-level input voltage 2.0 V CCINT +0.5 V V O Output voltage 0 V CCIO V Note: 1. Numbers in parenthesis are for industrial-temperature range versions. Endurance Characteristics Symbol Parameter Min Max Units t DR Data Retention 20 - Years N PE Program/Erase Cycles 10,000 - Cycles November 12, 1997 (Version 2.0) 3-61

4 XC95288 In-System Programmable CPLD DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 5 V operation I OH = -4.0 ma 2.4 V V CC = Min Output high voltage for 3.3 V operation I OH = -3.2 ma V V CC = Min 2.4 V OL Output low voltage for 5 V operation I OL = 24 ma 0.5 V V CC = Min Output low voltage for 3.3 V operation I OL = 10 ma 0.4 V V CC = Min I IL Input leakage current V CC = Max ±10.0 µa V IN = GND or V CC I IH high-z leakage current V CC = Max ±10.0 µa V IN = GND or V CC C IN capacitance V IN = GND f = 1.0 MHz 10.0 pf I CC Operating Supply Current (low power mode, active) V I = GND, No load f = 1.0 MHz 300 (Typ) ma AC Characteristics XC XC Symbol Parameter Min Max Min Max Units t PD to output valid ns t SU setup time before GCK ns t H hold time after GCK ns t CO GCK to output valid ns f 1 CNT 16-bit counter frequency MHz 2 f SYSTEM Multiple FB internal operating frequency MHz t PSU setup time before p-term clock input ns t PH hold time after p-term clock input ns t PCO P-term clock to output valid ns t OE GTS to output valid ns t OD GTS to output disable ns t POE Product term OE to output enabled ns t POD Product term OE to output disabled ns t WLH GCK pulse width (High or Low) ns Note: 1. f CNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. f CNT is also the Export Control Maximum flip-flop toggle rate, f TOG. 2. f SYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs November 12, 1997 (Version 2.0)

5 V TEST Device Output R 1 R 2 C L Output Type V CCIO 5.0 V 3.3 V V TEST 5.0 V 3.3 V R Ω 260 Ω R Ω 360 Ω C L 35 pf 35 pf X5906 Figure 3: AC Load Circuit Internal Timing Parameters XC XC Symbol Parameter Min Max Min Max Units Buffer Delays t IN Input buffer delay ns t GCK GCK buffer delay ns t GSR GSR buffer delay ns t GTS GTS buffer delay ns t OUT Output buffer delay ns t EN Output buffer enable/disable delay ns Product Term Control Delays t PTCK Product term clock delay ns t PTSR Product term set/reset delay ns t PTTS Product term 3-state delay ns Internal Register and Combinatorial delays t PDI Combinatorial logic propagation delay ns t SUI Register setup time ns t HI Register hold time ns t COI Register clock to output valid time ns t AOI Register async. S/R to output delay ns t RAI Register async. S/R recovery before clock ns t LOGI Internal logic delay ns t LOGILP Internal low power logic delay ns Feedback Delays t F FastCONNECT matrix feedback delay ns t LF local feeback delay ns Time Adders t 3 PTA Incremental Product Term Allocator delay ns t SLEW Slew-rate limited delay ns Note: 3. t PTA is multiplied by the span of the function as defined in the family data sheet. November 12, 1997 (Version 2.0) 3-63

6 XC95288 In-System Programmable CPLD XC95288 Pins N U P U P Y P W R AA R Y R Y [1] 1 11 R AA T AB T AA [1] T Y V AC K E [1] K C J E [1] L F K E [1] 2 9 L D L G M F M F [1] M H M G N H : [1] Global control pin outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global Signals are fixed November 12, 1997 (Version 2.0)

7 XC95288 Pins (continued) AA AC AB AD AD AE AE AC AD [1] AD AC AE AF AD AD AE AE AF AE AE AE AE AF AF C A D B A C B D C A B B B C C B D C B B C [1] A D B Note: [1] Global control pin November 12, 1997 (Version 2.0) 3-65

8 XC95288 In-System Programmable CPLD XC95288 Pins (continued) AE AD AF AC AE AF AC AE AD AD AF AE AE AD AD AE AC AC AF AE AE AD AE AC C B B A A D D C B B A A C B B A A D A B B A C D November 12, 1997 (Version 2.0)

9 XC95288 Pins (continued) AD V AD W AC U AD U AA V AA V AB U AC T AA R AA R Y R V R K P G N H N H N J M F M G M G M F L E L D L F J November 12, 1997 (Version 2.0) 3-67

10 XC95288 In-System Programmable CPLD XC95288 Global, JTAG and Power Pins Pin Type HQ208 BG352 /GCK1 44 Y24 /GCK2 46 AA24 /GCK3 55 AD23 /GTS1 7 E25 /GTS2 9 F26 /GTS3 3 E23 /GTS4 5 E24 /GSR 206 C23 TCK 98 AD6 TDI 94 AF6 TDO 176 D12 TMS 96 AE6 V CCINT 5 V 11, 59, 124, 153, 204 J23, V24, AF23, AC15, AF15, AD11, AD5, Y3, T1, J3, G4, D5, D10, B13, D17, C22, H24 V CCIO 3.3 V/5 V 1, 26, 53, 65, 79, 92, 105, 132, 157, 172, 181, 184 A10, A17, B2, B25, D7, D13, D19, G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC8, AC14, AC20, AE25, AF10, AF17 GND 2, 13, 24, 27, 42, 52, 68, 81, 93, 104,108, 129, 130, 141, 156, 163, 177, 190, 207 A1, A2, A5, A8, A14, A19, A22, A25, A26, B1, B26, C7, C9, C13, C18, D24, E1, E26, H1, H26, K4, N1, N24, P3, P26, V23, W1, W4, W26, AB1, AB4, AB26, AC9, AD10, AD14, AD15, AD20, AE1, AE26, AF1, AF2, AF5, AF8, AF13, AF19, AF22, AF25, AF26 No Connects A18, A23, A24, B4, B8, B10, B23, C1, C2, C3, C4, C5, C8, C11, C24, C25, D1, D3, D4, D14, D16, D21, D23, D25, E3, E4, F3, F23, G25, J2, J24, J26, K2, L4, L23, P2, T3, T4, T24, U25, V25, W3, W24, Y2, AB3, AB23, AC2, AC4, AC6, AC11, AC16, AC17, AC21, AC23, AC24, AC25, AD16, AD21, AD24, AD26, AE2, AE4, AE10, AE15, AF3, AF4, AF9, AF November 12, 1997 (Version 2.0)

11 ing Information XC HQ 208 C Device Type Speed Temperature Range Number of Pins Package Type Speed Options ns pin-to-pin delay ns pin-to-pin delay Packaging Options HQ Pin Heat Sink Quad Flat Pack (HQFP) BG Pin Plastic Ball Grid Array (BGA) Temperature Options C Commercial 0 C to 70 C I Industrial 40 C to 85 C Component Availability Pins Type Plastic HQFP Plastic BGA Code HQ BG XC C,I C,I 15 C C C = Commercial = 0 to +70 C I = Industrial = 40 to 85 C November 12, 1997 (Version 2.0) 3-69

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