XC95144XL High Performance CPLD

Size: px

Start display at page:

Download "XC95144XL High Performance CPLD"

Joanna Fletcher
6 years ago
Views:

1 XC95144XL High Performance CPLD November 13, 1998 (Version 1.2) Features 5 ns pin-to-pin logic delays System frequency up to 178 MHz 144 macrocells with 3,200 usable gates Available in small footprint packages pin TQFP (81 user pins) pin TQFP (117 user pins) pin CSP (117 user pins) Optimized for high-performance 3.3 V systems - Low power operation - 5 V tolerant pins accept 5 V, 3.3 V, and 2.5 V signals V or 2.5 V output capability - Advanced 0.35 micron feature size CMOS FastFLASH technology Advanced system features - In-system programmable - Superior pin-locking and routability with FastCONNECT II switch matrix - Extra wide -input Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with 3 global and one productterm clocks - Individual output enable per output pin with local inversion - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000 V Pin-compatible with 5 V-core XC95144 device in the 100-pin TQFP package Description The XC95144XL is a 3.3 V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of eight V Blocks, providing 3,200 usable gates with propagation delays of 5 ns. See Figure 2 for architecture overview. Preliminary Product Specification Power Estimation Power dissipation in CPLDs can very substantially depending on the system frequency, design application, and output loading. To help reduce power dissipation, each macrocell in a XC9500XL device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of I CC, the following equation may be used: I CC (ma) = MC HP (0.5) + MC LP (0.3) + MC( ma/mhz) f Where: MC HP = in high-performance (default) mode MC LP = in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Block with no output loading. The actual I CC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in graphical form. Typical I CC (ma) Low Power High Performance 104 MHz 178 MHz Clock Frequency (MHz) X5898C Figure 1: Typical I cc vs. Frequency for XC95144XL November 13, 1998 (Version 1.2) 1

2 XC95144XL High Performance CPLD JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 1 to /GCK /GSR /GTS Blocks FastCONNECT II Switch Matrix Block 2 1 to Block 3 1 to Block 4 1 to Block 8 1 to X5922B Figure 2: XC95144XL Architecture Block outputs (indicated by the bold line) drive the Blocks directly. 2 November 13, 1998 (Version 1.2)

3 Absolute Maximum Ratings Symbol Description Value Units V CC Supply voltage relative to GND -0.5 to 4.0 V V IN Input voltage relative to GND (Note 1) -0.5 to 5.5 V V TS Voltage applied to 3-state output (Note 1) -0.5 to 5.5 V T STG Storage temperature (ambient) -65 to +150 o C T SOL Maximum soldering temperature 1/16 in. = 1.5 mm) +260 T J Junction temperature +150 o C o C Note 1: Maximum DC undershoot below GND must be limited to either 0.5 V or 10 ma, whichever is easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to +7.0 V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol Parameter Min Max Units V CCINT Supply voltage for internal logic Commercial T A = 0 o C to 70 o C V and input buffers Industrial T A = -40 o C to +85 o C V V CCIO Supply voltage for output drivers for 3.3 V operation V Supply voltage for output drivers for 2.5 V operation V V IL Low-level input voltage V V IH High-level input voltage V V O Output voltage 0 V CCIO V Quality and Reliability Characteristics Symbol Parameter Min Max Units t DR Data Retention 20 - Years N PE Program/Erase Cycles (Endurance) 10,000 - Cycles V ESD Electrostatic Discharge (ESD) 2,000 - Volts DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 3.3 V outputs I OH = -4.0 ma 2.4 V Output high voltage for 2.5 V outputs I OH = -500 µa 90% V CCIO V V OL Output low voltage for 3.3 V outputs I OL = 8.0 ma 0.4 V Output low voltage for 2.5 V outputs I OL = 500 µa 0.4 V I IL Input leakage current V CC = Max V IN = GND or V CC ± 10.0 µa I IH high-z leakage current V CC = Max V IN = GND or V CC ± 10.0 µa C IN capacitance V IN = GND f = 1.0 MHz I CC Operating Supply Current (low power mode, active) V I = GND, No load f = 1.0 MHz 10.0 pf 45 ma November 13, 1998 (Version 1.2) 3

4 XC95144XL High Performance CPLD AC Characteristics XC95144XL-5 XC95144XL-7 XC95144XL-10 Symbol Parameter Units Min 1 Max 1 Min Max Min Max t PD to output valid ns t SU setup time before GCK ns t H hold time after GCK ns t CO GCK to output valid ns f SYSTEM Multiple FB internal operating frequency MHz t PSU setup time before p-term clock input ns t PH hold time after p-term clock input ns t PCO P-term clock output valid ns t OE GTS to output valid ns t OD GTS to output disable ns t POE Product term OE to output enabled ns t POD Product term OE to output disabled ns t AO GSR to output valid ns t PAO P-term S/R to output valid ns t WLH GCK pulse width (High or Low) ns t PLH P-term clock pulse width (High or Low) ns Advance Note 1:Please contact Xilinx for up-to-date information on advance specifications. Preliminary V TEST Device Output R 1 R 2 C L Output Type V CCIO 3.3 V 2.5 V V TEST 3.3 V 2.5 V R Ω 250 Ω R Ω 660 Ω C L 35 pf 35 pf X5906A Figure 3: AC Load Circuit 4 November 13, 1998 (Version 1.2)

5 Internal Timing Parameters Symbol Parameter XC95144XL-5 XC95144XL-7 XC95144XL-10 Min 1 Max 1 Min Max Min Max Units Buffer Delays t IN Input buffer delay ns t GCK GCK buffer delay ns t GSR GSR buffer delay ns t GTS GTS buffer delay ns t OUT Output buffer delay ns t EN Output buffer enable/disable delay ns Product Term Control Delays t PTCK Product term clock delay ns t PTSR Product term set/reset delay ns t PTTS Product term 3-state delay ns Internal Register and Combinatorial Delays t PDI Combinatorial logic propagation delay ns t SUI Register setup time ns t HI Register hold time ns t ECSU Register clock enable setup time ns t ECHO Register clock enable hold time ns t COI Register clock to output valid time ns t AOI Register async. S/R to output delay ns t RAI Register async. S/R recover before clock ns t LOGI Internal logic delay ns t LOGILP Internal low power logic delay ns Feedback Delays t F FastCONNECT II feedback delay ns Time Adders t PTA Incremental product term allocator delay ns t SLEW Slew-rate limited delay ns Advance Preliminary Note 1: Please contact Xilinx for up-to-date information on advance specifications. November 13, 1998 (Version 1.2) 5

6 XC95144XL High Performance CPLD XC95144XL Pins Block Macrocell TQ100 TQ144 CS144 BScan Order Notes Block Macrocell TQ100 TQ144 CS144 BScan Order H M F L1 3 [1] G K J N G L G L L H N2 300 [1] H N K N H M J K J K J L M K2 381 [1] M C C A2 372 [1] A A C B1 363 [1] D C2 360 [1] A D4 3 [1] B D3 351 [1] C D C E D E B E A E D F B F C F A Note 1: Global control pin. Notes 6 November 13, 1998 (Version 1.2)

7 XC95144XL (Continued) Block Macrocell TQ100 TQ144 CS144 BScan Order Notes Block Macrocell TQ100 TQ144 CS144 BScan Order N N L L M M N L M K K K N K N K M J K H L J N H K H J M H C G F B E A G A F D F A F B D B E A E D D D A C D B B C Notes November 13, 1998 (Version 1.2) 7

8 XC95144XL High Performance CPLD XC95144XL Global, JTAG and Power Pins Pin Type TQ100 TQ144 CS144 /GCK K2 /GCK L1 /GCK N2 /GTS1 3 5 D4 /GTS2 4 6 D3 /GTS3 1 2 B1 /GTS4 2 3 C2 /GSR A2 TCK L10 TDI L9 TDO C8 TMS N10 V CCINT 3.3 V 5, 57, 98 8, 42, 84, 141 B3, D1, J13, L4 V CCIO 2.5 V/3.3 V 26, 38, 51, 88 1, 37, 55, 73, 109, 127 A1, A13, C7, L7, N1, N13 GND Ordering Information 21, 31, 44, 62, 69, 75, 84, 100, 29, 36, 47, 62, 72, 89, 90, 99, 108, 114, 123, 144 B2, B8, B12, C10, E11, G1, G12, G13, K1, M2, M5, M9, M12 No Connects - Example: XC95144XL -7 TQ 100 C Device Type Speed Grade Temperature Range Number of Pins Package Type Speed Options ns pin-to-pin delay ns pin-to-pin delay -5 5 ns pin-to-pin delay Packaging Options TQ Pin Thin Quad Flat Pack (TQFP) TQ Pin Thin Quad Flat Pack (TQFP) CS Pin Chip Scale Package (CSP) Temperature Options C= Commercial T A = 0 o C to +70 o C I = Industrial T A = -40 o C to +85 o C 8 November 13, 1998 (Version 1.2)

9 Component Availability Pins Type Plastic TQFP Plastic TQFP Chip Scale Package CSP Code TQ100 TQ144 CS144 XC95144XL Revision History -10 C, I C, I - -7 C C (C) -5 (C) (C) - C = Commercial (T A = 0 o C to +70 o C) I = Industrial (T A = -40 o C to +85 o C) ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date availability information. Date 10/30/98 Minor corrections in CS144 pinout table. 11/13/98 V1.2 Minor correction in CS144 pinout table. Revision November 13, 1998 (Version 1.2) 9

XC95288 In-System Programmable CPLD

0 XC95288 In-System Programmable CPLD November 12, 1997 (Version 2.0) 0 3* Preliminary Product Specification Features 15 ns pin-to-pin logic delays on all pins f CNT to 95 MHz 288 macrocells with 6,400