HotChips An innovative HD video and digital image processor for low-cost digital entertainment products. Deepu Talla.

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1 HotChips 2007 An innovative HD video and digital image processor for low-cost digital entertainment products Deepu Talla Texas Instruments 1 Salient features of the SoC HD video encode and decode using 16-bit DRAM interface Up to 75 MP/s of image processing for fast picture capture, processing, and display Low-power consumption for portable end equipments Flexibility and programmability for implementing new use-cases High level of integration coupled with high performance to bring high-end features into low-cost products Belongs to the DaVinci TM family of digital video processors; products with this SoC shipping in the market today 2

2 Outline Target applications Block diagram of the SoC Architectural details of key components Performance and power specifications Software platform Example reference design (used for 2 target applications) Floorplan and key statistics of the SoC 3 Target applications Digital still camera Solid state camcorder HD docking station Digital photo frame IP security network camera Photo printer Other Low-cost EEs HDTV card reader Low-cost portable media player 4

3 Block diagram Video Processing Subsystem ARM Subsystem ARM926EJ-S 216 MHz CPU 16KB I$, 8KB D$ 32KB RAM 8 KB ROM Imaging acceleration - programmable SIMD engine MJCP MPEG4 HD engine JPEG compression Front End ISP Image signal processor Back End Enhanced On-Screen Display (OSD) Video Enc (VENC) Image/video Statistics CCD/CMOS controller Resizer 10b DAC CCD/ CMOS Imager Analog/ digital video output Peripherals DMA Data & Configuration Bus Connectivity System McBSP x2 EDMA Serial Interfaces I 2 C SPI x3 UART x3 Motor control DDR EMIF (171 MHz) USB2.0 HS GIO NAND/ECC EMIF Timer x6 Program/Data Storage CE-ATA Over MMC WDT MMC/SD SDIO x2 PWM x4 MS/Pro 5 Video processing subsystem State-of-the-art ISP for camera capture Advanced image processing algorithms in hardware with additional software programmable accelerators for flexibility Handles any sensor read-out pattern Latest generation of lens distortion/shading compensation, noise filters, CFA interpolation, color processing, edge enhancement, and resizing IP Real-time statistics for auto focus, exposure, white balance, video stabilization, image classification, etc Optimized display subsystem Multiple video and graphic window support for enhanced GUI Integrated analog components for direct connect to a TV System tailored master interface Multi-level arbitration to re-order and buffer various module commands/data to simplify SoC level interconnect 6

4 Video and imaging coprocessors (1 of 2) Flexible SIMD engine Allows for implementing differentiated algorithms at 5-10x speed of an ARM processor high ISO (low light) noise filtering, redeye reduction, face tracking/detection and recognition, image stitching, adaptive contrast enhancement, motion estimation Up to 8 ALUs used per cycle MAC, absolute difference, table lookup, max/min, median, etc Local SRAMs with multiple banks to achieve maximum memory performance Programmed using vector style instructions with each instruction operating on a 2D block of data APIs available for common functions 7 Video and imaging coprocessors (2 of 2) MPEG4 compression engine Processing at HD rates with margin to achieve 30 fps in a system Programmable ME engine for resolution versus bit-rate/psnr tradeoff ME engine performs tasks of 422-to-420 conversion, full and half pel ME, inter/intra coding decision, Y and C prediction, and various block copies 16-way SAD engine Budget less than 1000 cycles per macro-block JPEG compression engine Fixed function block > 40 MP/s sustained performance in a system Can be used for video as a mjpeg sequence 8

5 Infrastructure components Shared across portfolio of DaVinci processors Reuse at IP, SoC, drivers, and software On-chip bus Split command and data to maximize performance for multiple masters at different priorities, latency & bandwidth requirements, and transfer sizes DRAM memory controller (DDR EMIF) Multi-level arbitration schemes to achieve HD performance in a 16-bit DDR2 environment EDMA Flexible DMA engine with 64 channels to simplify programming of slave data transfers 9 Key application performance specs Raw image processing (ISP and JPEG compression) 75 MP/s Sustained image processing (limited by overall system not the SoC) > 5 fps at 8 MP resolution HD video encode and decode (720P) > 30 f/s MPEG4 in full system including digital video stabilization Advanced image processing (using programmability in the SoC) High ISO image capture (10000) Red-eye removal (< 400 ms for 10MP image) Fast face-tracking (> 30 f/s) Adaptive image contrast enhancement (< 500 ms for 10 MP image) Panoramic image stitching (3 images < 1 second) 10

6 Power consumption Standby power (deep sleep mode) 1 mw Image and video preview < 200 mw without DRAM power; < 250 mw including DRAM power SD video encode and playback < 250 mw without DRAM power; < 330 mw including DRAM power HD video encode (720P) < 400 mw without DRAM power; < 550 mw including DRAM power High speed image processing (> 50 MP/s) < 300 mw without DRAM power, < 400 mw including DRAM power 11 Software platform overview Customer application/s Reference Framework Basic user interface Application APIs Algorithm abstraction Code Composer Studio Dev Tools Trace Application kernel/software Compliant Plug-in OS abstraction Program Build Program Debug Real-Time Analysis Platform support package Chip support library OS port Board support package Other drivers XDS Emulator Host Computer Embedded emulation components SoC physical hardware 12

7 Example: HW + SW turnkey reference design for digital imaging products (DSC, DVC) Imager Board CCD or CMOS Sensor AFE, Lens, Motor, Strobe, Focus Assist Display Board (LCD) Digital Media Processor Board SD/MMC Digital Media Processor USB 2.0 USB 1.1 NAND DDR1/2/m Audio Codec WLAN Power / UI Board Battery and DC power Battery Charger, Key scan RTC, User buttons, Mode settings Hardware Processor Board LCD Board Imager Board Power / UI Board Software Drivers Chip Support Libraries Operating System Image Pipeline Image Quality & Tuning Tools QA Testing Support Defined API Video and Audio Codecs Customers can customize or use their own codecs and algorithms 13 Floorplan 90nm with 5 metal layers 1.3V core voltage ~2.6 million gates ~1.7 Mbits of memory 12x12 package Major blocks Dark blue ARM subsystem Yellow Imaging and video compression Light green Video processing subsystem 14

8 References SoC press release: DaVinci technology overview and specifications: DaVinci technology digital video innovation product bulletin: 15

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