Encoder Core. API Specification. Revision: SOC Technologies Inc.
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1 Encoder Core API Specification Revision: SOC Technologies Inc.
2 SOC is disclosing this user manual (the Documentation ) to you solely for use in the development of designs to operate with SOC hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of SOC. SOC expressly disclaims any liability arising out of your use of the Documentation. SOC reserves the right, at its sole discretion, to change the Documentation without notice at any time. SOC assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. SOC expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information. THE DOCUMENTATION IS DISCLOSED TO YOU AS-IS WITH NO WARRANTY OF ANY KIND. SOC MAKES NO OTHER WARRANTIES, WHETHER EXPRESSED, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL SOC BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION SOC, Inc. All rights reserved. SOC, the SOC logo, the Brand Window, and other designated brands included herein are trademarks of SOC, Inc. Page 2 of 7
3 Revision History The following table shows the revision history for this document. Date Comment Revision Author Old versions /20/2016 Added Revision History Added firmware revision info registers: 0xE6,0xE7, 0xE9,0xEA Added comments according to Hollyland questions Added API address map table (Table 1) Added support for H265 Added register bits for configuration 1.4 Blake 1.5 Blake 1.6 Blake Add API documents name in Table Add audio sample rate register 0xD5 Add DDR info, 0xA Added register 0xDB and 0xDC for version control 1.8 Blake 1.9 Blake API update for compatibility 2.0 Mulong API update for register 0xEE and 0xEF to support 8K frame Added comment for Register A6 for module only. 2.1 Blake 2.2 Blake Page 3 of 7
4 Table-1: Encoder Core API Space Map Address Range (HEX) Information 0 to 3F The Video Encoder core APIs, depends on your production: 50 to 7F a. MPEG2 Encoder API address range <MPEG2 Encoder API.pdf> b. H264 Encoder API address range <H264 Encoder API.pdf> c. H265 Encoder API address range <H265 Encoder API.pdf> Please reference according API manual as your production. 80 to 8F Video Input Core API described in <Video Input Core API.pdf> 40 to 4F Encoder Core System top level API 90 to FF (this manual) Table-2: Encoder System Configuration Addr Information (HEX) 92 Bit[2:0]: Multi-Channel/Time Sharing API Core Selection - 0 Selects all cores for writing = Core # - Note only 1 core can be read at a time. A value of 0 should not be used for reading registers. - This register is also used for indexing sub-api blocks such as Video Input, H264 Encoder A6 Read only (DO NOT write to this register): Bit [2]: DDR_CALIB_OK. 1 = DDR calibration ok. 0 = DDR calibration failed, please check your DDR type and connections. Comments: This register is designed for system level (including MIG) only for SOC MPEG Video CODEC FPGA Module users. The core user would simply ignore this register. Access R The following registers are unique to each time-shared core (when used) 94 Bit[15:8]: Real-Time Encoding Frame Rate Bit[7:0]: Target Frame Rate *It is a read only register. To change frame rate, use 0x88 in the R video input module. 95 Bit[15:0]: Decimal Bit Rate(Mbps), for reference only R Page 4 of 7
5 Bit[3:0]: Fractional Bit Rate (0.x Mbps), for reference only 96 Bit[7:0]: Presentation Latency / 2.84ms - Example: 0x1E = 85.2ms *It is the the difference of PTS - PCR in TS stream. PCR is current encoding time in encoder and current time in decoder. PTS is the Present Time Stamp of a decoded frame for decoder. 97 Bit[12:0]: Target Bit Rate Value / 10 (Mbps) - Example: 150(decimal) = 15Mbps 9E Bit[12:0]: Constant Bit Rate Value / 10 (Mbps) - Example: 150(decimal) = 15Mbps Bit[15]: Enabled NULL packet insertion. - When the target bitrate drops below the threshold, NULL transport packets will be inserted if enabled. *Note: This is to control the minimum bit-rate of the TS stream. EE Bit[15:0] Encoded Width The user can change to force a different resolution. Write 0 to the register will recover the input video width. EF Bit[15:0] Encoded Height The user can change to force a different resolution. Write 0 to the register will recover the input video height. The following registers are shared between all cores even when muli/time-sharing cores are used 9D Bit[20]: Time limted Core Expired Bit[14]: DNA Passed Bit[13]: User TX Ready Bit[8]: EEPROM Authentication Present Bit[7]: DNA Authentication Present * Bit[2]: Force Video Encoder Read* Bit[1]: Bypass DDR Fifo* Bit[0]: Bypass Transport Stream Encoder* 9F Bit[15:0]: Signed Audio Offset from Video Frames D5 This register is only for special customer. Bit [3:0]: Audio_bit_rate (Decimal)*: For MPEG1/2 layer 2 (MP2): 0x 8: 64 kbps 0x 9: 96 kbps 0x A: 128 kbps 0x B: 192kbps * Page 5 of 7
6 Others: Reserved. Bit[15:8]: Audio sample rate *: 0x32: The sample rate is 32K 0x44: The sample rate is 44.1K 0x48: The sample rate is 48K The sample rate is supported only on special build. Bit[23:16]: Audio encoder type "0F" for AAC, x"04" for MPEG AUDIO layer 1, 2 or 3 DB Bit[31:0]: GIT_DATE R DC Bit[31:0]: GIT_VERSION R E0 Bit[10]: Evaluation Time Out Bit[9]: Evaluation Version Bit[6]: DNA Passed Bit[5]: Final Encoder Reset * Bit[2]: WatchDog Reset Bit[1]: Enable WatchDog Bit[0]: API Controlled Reset* E1 Bits are toggle by writing 1 to the corresponding bit Bit[3]: Disable Video Bit[2]: Disable Audio E2 Bit[28]: DNA Authentication Present Bit[27]: EEPROM Authentication Present Bit[26]: Compression Audio is supported or not in this core Bit[25]: PCM Audio is supported or not in this core Bit[23]: DDR Fifo Buffer Present R Bit[22]: H264(AVC) Video Encoder Present Bit[21]: H265(HEVC) Video Encoder Present Bit[20]: MPEG2 Video Encoder Present E6 Bit[31:0]: Encoder Core Build Date R E7 Bit[31:0]: Encoder Core Build Time Stamp R Table-3: DDR Fifo Registers The DDR fifo uses a portion of DDR to buffer data/compressed stream. This allows for buffering of > 8Mbytes. The DDR fifo IP core is optional and not present in all designs. Please contact SOC if you feel this function is required for your application. Note this core is not available for time-shared encoders at this time Addr Information Access (HEX) 40 Bit[31:0]: Build Date R Page 6 of 7
7 41 Bit[14]: Reset Bit[13]: Buffer Overflow Bit[10]: Byte Read Bit[9]: Output Buffer Empty Bit[8]: Output Buffer Ready Bit[3]: Timer Enabled* Bit[2]: Low Delay* Bit[1]: Clear Buffer Overflow Register* Bit[0]: API Reset* 42 Bit[5:0]: Burst Size Bit[8]: Bypass DDR Fifo (DDR will not be used) 43 Bit[25:0]: DDR Start Address R 44 Bit[25:0]: DDR End Address R 45 Bit[7:0]: DDR Buffer Percent R 46 Bit[7:0]: DDR Buffer Count (Number of Blocks in DDR) R 47 Bit[15:0]: Input Count R 48 Bit[15:0]: Read Count R Page 7 of 7
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