DAC 2018 FPGA design contest
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1 DAC 2018 FPGA design contest Naveen Purushotham, Xilinx Jingtong Hu, University of Pittsburgh Bei Yu, Chinese University of Hong Kong Xinyi Zhang, University of Pittsburgh
2 Agenda Welcome DAC Contest Committee Contest Introduction Webinars Piazza PYNQ TM & Reference design discussion Things to know Design rules Reference design Questions & Answers Page 2
3 DAC Contest Committee Page 3
4 PYNQ Page 4
5 Python productivity for Zynq An open-source framework for combining SW and HW libraries on Zynq Use SW libraries of Python language Exploit programmable logic and microprocessors using HW libraries Out of Box Prebuilt SD card Python, Jupyter, Ubuntu & Bitstreams Python & Debian & Bitstream extensible PYNQ marries data science software and capabilities of zynq and programmable hardware PYNQ-Z1 First PYNQ supported board Page 5
6 Jupyter Notebooks: browser-based development with rich, multi-media support Designed for Interactive, exploratory computing Reproducible results Ideal for Teaching and learning Projects and research Provides Interactive design with Zynq application-oriented perspective githubcom/ipython/ipython/wiki/a-gallery-of-interesting-ipython-notebooks Where to find more notebooks Page 6
7 Overlays aka hardware libraries special bitstreams Step 1: Create an FPGA design for a class of related applications Step 2: Export the bitstream and a C API for programming the design Step 3: Wrap the C API to create a Python library Step 4: Import the bitstream and the library in your Python scripts and program Page 7
8 Neural Network Application example Runs in Browser HW libraries for PL Program Bitstream Page 8
9 Neural Network Application example Import python Runs in SW Browser libraries HW libraries for PL Program Bitstream Show results and analysis Page 9
10 Productivity level tools for Zynq Python scripts & programs Interactive console Python Libraries CPython Virtual Machine Ubuntu core Python-C bindings for IP drivers IP drivers in C Post-bitstream-programmable overlay Page 10
11 Example PYNQ Project FINN: Binary Neural Network Overlay on PYNQ SVHN, Road signs, CIFAR-10 Int Symposium on FPGAs, Feb 2017 Image pre-processing in Python Unprecedented image classification rates 1,000x speed-up over Raspberry Pi3 Binary Neural Network in FPGA & ARM CPU cat Page 11
12 A high productivity tool for experienced FPGA designers Pynq as a High Productivity Platform for FPGA Design & Exploration Fellow FPGA designers, try Pynq You ll like it Pynq makes exploring new FPGA ideas lightweight, fresh, fast, easy, fun again I hadn t expected that Pynq would also be a high productivity tool for experienced FPGA designers to more rapidly explore, evaluate, discover, and play Using Pynq to explore, develop, prototype saved me weeks of effort It was particularly good for interactively writing tests and exploring new hardware corner cases in Python with <1 second turnaround Jan Gray feedback on implementing 80 x 32-bit RISC cores on PYNQ-Z1 Page 12
13 PYNQ is completely open-source Where to find more information Page 13
14 PYNQ Team standing by Build something cool Contribute to Open Source Contribute Reproducible Results If not already a member, join the PYNQ support forum Page 14
15 DAC Contest reference design DDR PS side ZYNQ PL side Batch size = 500 open and resize images inference Timer should start before opening the images and end after PS side receives all detected coordinates Write to XML can be excluded from timer Page 15
16 Q & A Page 16
Inference
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