HW/SW Co-design. Design of Embedded Systems Jaap Hofstede Version 3, September 1999
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1 HW/SW Co-design Design of Embedded Systems Jaap Hofstede Version 3, September 1999
2 Embedded system Embedded Systems is a computer system (combination of hardware and software) is part of a larger system (that may or may not be a computer) performs a fixed function for that system 99/09/07 HW/SW Co-design 2
3 SW or HW? Software Hardware Flexibility Late design changes Features Reuse Reduced time to market Performance Low power (Security) 99/09/07 HW/SW Co-design 3
4 Applications Relatively small systems Consumer electronics Consumer products Automobiles Telecommunication Computer peripherals Copiers, FAX machines Multimedia systems Relatively large systems Airplanes Industry 99/09/07 HW/SW Co-design 4
5 Classes of embedded systems Reactive (Control Dominated) Transforming (Data Dominated) State Real-time Digital Signal Processing (DSP) Limited functionality, but very fast 99/09/07 HW/SW Co-design 5
6 Cost Main parts of cost Design is a trade-off Initial cost Product cost Time to market Cost Design time Performance 99/09/07 HW/SW Co-design 6
7 Technological developments Number of transistors: 35% Clock speed: 25% Processor performance: 50% Gap is growing Design Capacity: only about 20% What to do with all those transistors? Integrate several functions Programmable processors ROM for Programs for these processors 99/09/07 HW/SW Co-design 7
8 Classes of embedded systems Standard microprocessor or DSP with separate RAM, ROM and interfaces Standard microprocessor or DSP with ASIC or FPGA Processor core integrated on ASIC or FPGA ASIP 99/09/07 HW/SW Co-design 8
9 To manage complexity Traditional design SW and HW partitioning at an early stage HW and SW designed separately 99/09/07 HW/SW Co-design 9
10 HW/SW Co-design Specify, explore, refine Flexible design strategy Hierarchy of models at different abstraction levels HW and SW designed with interaction and feedback Final partitioning after evaluation of trade-offs Requires Co-specification Co-development (Cosynthesis) Co-verification 99/09/07 HW/SW Co-design 10
11 Goals Reduced time to market Better products Lower development costs Lower number of design cycles Higher level of abstraction Volume specific targets 99/09/07 HW/SW Co-design 11
12 Tools Design framework Common specifications Silicon compilers Software compilers Real-time kernels Simulators Analysis tools 99/09/07 HW/SW Co-design 12
13 Disciplines Application domain Specification and programming languages Compilers (!) VLSI design Parallel/distributed systems Real-time systems Formal methods (Performance) analysis 99/09/07 HW/SW Co-design 13
14 Specification Provide clear and unambiguous description Allow CAD tools Should not constrain implementation in either SW or HW To be compiled to other languages for HW (VHDL) or SW (C) Executable to verify if requirements are met 99/09/07 HW/SW Co-design 14
15 Computation models Control dominated Finite State Machines (FSM) Communicating Sequential Processes (CSP) Discrete event models (VHDL) Petri nets Data dominated Control flow graphs Data flow graphs Control/Data flow graphs 99/09/07 HW/SW Co-design 15
16 Co-simulation Simulation of systems with a mix of different kinds of SW and HW components Levels High abstraction Instructions ASIC models Gate Switch Analogue 99/09/07 HW/SW Co-design 16
17 Compilers Front-end (target independent) Back-end (source independent) Scanning Parsing Static semantic analysis Optimization Optimization Code generation 99/09/07 HW/SW Co-design 17
18 Code generation 1. Instruction selection 2. Register allocation 3. Instruction scheduling Currently often separate Characteristics of DSP s and ASIPs make these three subtasks mutually dependent Coupling necessary for generation of optimal code 99/09/07 HW/SW Co-design 18
19 Characteristics of DSP s Harvard Multiple busses with restricted connectivity High I/O-rate Irregular register sets of different sizes Special purpose registers Special registers for zero-overhead loops Multiply-add-accumulate in one instruction Fixed-point operations Hardware supported addressing modes 99/09/07 HW/SW Co-design 19
20 Example: Data path ADSP210x i: 0 i n: y i [j] = y i-1 [j] + x[j-i]*a[i] D x P a * +,- Addressregisters A0, A1, A2.. i+1, j-i+1 Address generation unit (AGU) AX +,-,.. AR AY AF x[j-i] MX MR a[i] MY MF x[j-i]*a[i] y i-1 [j] 99/09/07 HW/SW Co-design 20
21 Compiler back-ends for DSP s Very hard to generate sufficiently efficient code Intensive optimization required Coupling of three subtasks Long compilation time acceptable 99/09/07 HW/SW Co-design 21
22 Compiler back-ends for ASIP s ASIP s often have characteristics of DSP s Specific code generator required Retargetable code generators Code generator must be generated automatically from description of processor From register description and instruction set (behavior) From structure of ASIP data path as generated by high level synthesis (structure) 99/09/07 HW/SW Co-design 22
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