Input. Output. Datapath: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions.

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1 path & Control Readings: Computer Processor Devices Control Input path Output path: System for performing operations on data, plus memory access. Control: Control the datapath in response to instructions. 70 Simple CPU Develop complete CPU for subset of instruction set : LDUR, STUR Opcode 00 Rd Branch: B Opcode Conditional Branch: CBZ Opcode CondAddr19 Rd Arithmetic: ADD, SUB Opcode Rm SHAMT Rd Most other instructions similar 71

2 Execution Cycle Fetch Decode Operand Fetch Execute Result Store Next Obtain instruction from program storage Determine required actions and instruction size Locate and obtain operand data Compute result value or status Deposit results in storage for later use Determine successor instruction 72 Processor Overview Overall flow fetches instructions s select operand registers, ALU immediate values ALU computes values Load/Store addresses computed in ALU Result goes to register file or memory Register File 73

3 RTL & Processor Design Convert instructions to Register Transfer Level (RTL) specification RegA = RegB + RegC; RTL specifies required interconnection of units, control Math unit example: (add): A = A + B; I++; (mult): A = A * B: I++; (hold): A = A; I++; (init): A = Din; I++; A I 74 Fetch 75

4 Add/Subtract RTL Add instruction: ADD Rd,, Rm Subtract instruction: SUB Rd,, Rm Opcode Rm SHAMT Rd 76 Add/Subtract path 4 77

5 Load RTL Load : LDUR Rd, [, ] Opcode 00 Rd 78 path + Load 4 Addr Dout 79

6 Store RTL Store : STUR Rd, [, ] Opcode 00 Rd 80 path + Store 4 Addr Dout 81

7 Branch RTL Branch : B path + Branch 4 Reg2Loc Addr 83

8 Conditional Branch RTL Conditional Branch : CBZ Rd, CondAddr Opcode CondAddr19 Rd 84 path + Conditional Branch Reg2Loc 4 Addr 85

9 Control Identify control points for pieces of datapath Fetch Unit ALU Memories path muxes Etc. Use RTL for determine per-instruction control assignments 86 Complete path UncondBr Reg2Loc CondAddr19 4 Zero Addr 87

10 Control Signals Opcode[31:26] Opcode[25:21] xxxxx xxx ADD SUB LDUR STUR B CBZ 88 ADD Control = Mem[]; Reg[Rd] = Reg[] + Reg[Rm]; = + 4; Reg2Loc CondAddr19 UncondBr 4 Zero Addr 89

11 SUB Control = Mem[]; Reg[Rd] = Reg[] - Reg[Rm]; = + 4; Reg2Loc CondAddr19 UncondBr 4 Zero Addr 90 LDUR Control = Mem[]; Addr = Reg[] + SignExtend(); Reg[Rd] = Mem[Addr]; CondAddr19 = + 4; Reg2Loc UncondBr 4 Zero Addr 91

12 STUR Control = Mem[]; Addr = Reg[] + SignExtend(); Mem[Addr] = Reg[Rd]; = + 4; Reg2Loc CondAddr19 UncondBr 4 Zero Addr 92 B Control = Mem[]; = + SignExtend(); UncondBr Reg2Loc CondAddr19 4 Zero Addr 93

13 CBZ Control = Mem[]; Cond = (Reg[Rd] == 0); if (Cond) = + (CondAddr19); else = + 4; Reg2Loc CondAddr19 UncondBr 4 Zero Addr 94 Advanced: Exceptions Exception = unusual event in processor Arithmetic overflow, divide by zero, Call an undefined instruction Hardware failure I/O device request (called an interrupt ) user program Exception: System Exception Handler return from exception Approaches Make software test for exceptional events when they may occur ( polling ) Have hardware detect these events & react: Save state (Exception Program Counter, protect the GPRs, note cause) Call Operating System If (undef_instr) = C If (overflow) = C If (I/O) = C

14 Performance of Single-Cycle Machine CPI? ADD, SUB Instr. mux Reg Read mux ALU mux Reg Setup LDUR Instr. Reg Read ALU mux Reg Setup STUR Instr. Reg Read ALU CBZ Instr. mux Reg Read mux ALU mux setup B Instr. mux setup 96 Reducing Cycle Time Cut combinational dependency graph and insert register / latch Do same work in two fast cycles, rather than one slow one storage element Acyclic Combinational Logic storage element Acyclic Combinational Logic (A) storage element storage element Acyclic Combinational Logic (B) storage element 97

15 Pipelined Processor Overview Divide datapath into multiple stages IF Fetch RF Register Fetch EX Execute MEM WB Writeback Instr. Register File Register File 98

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