AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing

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1 AEGIS: Architecture for Tamper-Evident and Tamper-Resistant Processing G. Edward Suh, Dwaine Clarke, Blaise Gassend, Marten van Dijk, Srinivas Devadas Massachusetts Institute of Technology L C S

2 Cases for Physical Security Applications on untrusted hosts with untrusted owners Digital Rights Management (DRM), Software licensing Distributed computation on Internet Mobile agents New challenges Untrusted OS Physical attacks Music/Movie Make Illegal Copies Incorrect Results; Break the System Program Software Distributed Computing, Peer-to-Peer Network

3 Conventional Tamper-Proof Packages Processing system in a tamper-proof package (IBM 4758) Expensive: many detecting sensors Needs to be continuously powered: battery-backed RAM $2,690 in 2001 Memory 99MHz 486 Source: IBM website

4 Single-Chip Secure Processors Only trust a single chip: tamper-resistant Off-chip memory: verify the integrity and encrypt Untrusted OS: identify a core part or protect against OS attacks Cheap, Flexible, High Performance Untrusted OS Identify or Protect against Trusted Environment Check Integrity, Encrypt I/O Memory

5 Related Research XOM (execution Only Memory): David Lie et al Stated goal: Protect integrity and privacy of code and data Operating system is completed untrusted Memory integrity checking does not prevent replay attacks Privacy is expensive but not necessary for all applications Palladium/NGSCB: Microsoft Stated goal: Protect from software attacks Combination of hardware and software mechanisms Adds "curtained" memory to avoid DMA attacks Uses a security kernel (Nexus) Memory integrity and privacy are assumed (only software attacks).

6 AEGIS: High-Level Architecture L C S

7 Secure Execution Environments Tamper-Evident (TE) environment Guarantees a valid execution and the identity of a program; no privacy Any software or physical tampering to alter the program behavior should be detected Private Tamper-Resistant (PTR) environment TE environment + privacy Encrypt instructions and data Assume programs do not leak information via memory access patterns Implementation Either have a trusted part of the OS or completely untrust the OS Secure context manager, encryption and integrity verification

8 Secure Context Manager (SCM) A specialized module in the processor Standard Processor SCM Assign a secure process ID (SPID) for each secure process Regs Processor Core SPID Implements new instructions enter_aegis set_aegis_mode L1 Instruction cache L1 Data cache random sign_msg On-Chip L2 Cache Maintains a secure table Even operating system cannot modify Off-Chip Memory

9 SCM: Program Start-Up enter_aegis : TE mode Start protecting the integrity of a program Compute and store the hash of the stub code: H(Prog) Tampering of a program results in a different hash Stub code verifies the rest of the code and data set_aegis_mode Start PTR mode on top of the TE mode enter_aegis code_end SHA-1 H(Prog) Protected Table Program.text enter_aegis EKey1 = 0xA4523BC2E435D; EKey2 = 0xB034D2C654F32; E1Msg = Secret=GetSecret(Challenge); Key1=Decrypt(EKey1, Stub Segment Secret); Key2=Decrypt(EKey2, Secret); CheckMAC(Key1, Key2, MAC); Msg = Decrypt(E1Msg, Key1); E2Msg = Encrypt(Msg, Key2); Output(E2Msg); Secret=GetSecret(Challenge); Key1=Decrypt(EKey1, Secret); Key2=Decrypt(EKey2, Secret); CheckMAC(Key1, Key2, MAC); Msg = Decrypt(E1Msg, Key1); E2Msg = Encrypt(Msg, Key2); Output(E2Msg);

10 SCM: On-Chip Protection Registers on interrupts SCM saves Regs on interrupts, and restore on resume Standard Processor Regs Processor Core Interrupt SPID H(Prog) SCM On-chip caches Need to protect against software attacks Use SPID tags and virtual memory address Allow accesses from the cache only if both SPID and the virtual address match SPID Tags L1 Instruction cache Resume L1 Data cache On-Chip L2 Cache SPID Tags SPID Tags Regs Off-Chip Memory

11 Memory Encryption Program Processor ENCRYPT write Untrusted RAM Trusted State DECRYPT read Encrypt on an L2 cache block granularity Use symmetric key algorithms with CBC mode Randomize initial vectors

12 Integrity Verification Program Processor Untrusted RAM V E R I F Y Trusted State ENCRYPT DECRYPT write read Address 0x45 E(124), MAC(0x45, 124) E(120), MAC(0x45, IGNORE 120) Cannot simply MAC on writes and check the MAC on reads Replay attacks Hash trees for integrity verification

13 Hash Trees Processor VERIFY root = h(h 1.h 2 ) VERIFY L2 block h 1 =h(v 1.V 2 ) h 2 =h(v 3.V 4 ) Logarithmic overhead for every cache miss Low performance Cached hash trees Data Values READ MISSV 1 V 2 V 3 V 4 Untrusted Memory

14 Cached Hash Trees (HPCA 03) VERIFY Processor root = h(h 1.h 2 ) h 1 =h(v 1.V 2 ) h 2 =h(v 3.V 4 ) VERIFY In L2 VERIFY DONE!!! In L2 Cache hashes in L2 L2 is trusted Stop checking earlier Less overhead MISS V 1 V 2 V 3 MISS V 4 Untrusted Memory

15 Message Authentication Processor Other systems The processor signs a message for a program sign_msg M: {H(Prog), M} SKproc Unique for each program because H(Prog) is always included Other systems Processor Embed the user s public key in a program Incoming messages are signed with the user s private key Program with P user {Message} Suser {H(Prog), Message} Sproc

16 L C S Applications

17 Certified Execution Execution certified by the secure processor Dispatcher provides a program and data Processor returns the results with the signature Requires the TE environment Verify results -H(Prog) -signature enter_aegis Execute Get results Program, Data RESULT Processor s Public Key RESULT Processor s Private Key Job Dispatcher Secure Processor

18 Digital Rights Management Protects digital contents from illegal copying Trusted software (player) on untrusted host Content provider only gives contents to the trusted player Requires the PTR environment Verify -H(Player) -nonce -signature Run Player - enter_aegis -enter PTR Content Player Random nonce Signed nonce Processor s Public Key Content Provider Authenticated & Encrypted Channel (SSL) Secure Processor Processor s Private Key

19 L C S Performance

20 Performance Implication: TE processing Major performance degradation is from off-chip integrity checking Start-up and context switches are infrequent no performance overhead for on-chip tagging Normalized IPC KB 1MB 4MB Worst case 50% degradation Most cases < 25% degradation gcc gzip mcf twolf vortex vpr applu art swim (a) 64B L2 Caches with 64B blocks

21 Performance Implication: PTR processing Major performance degradation is from off-chip integrity checking and encryption KB 1MB 4MB Normalized IPC Worst case 60% degradation Most cases < 40% degradation gcc gzip mcf twolf vortex vpr applu art swim L2 Caches with 64B blocks

22 Summary Physical attacks are becoming more prevalent DRM, software licensing, distributed computing, etc. Single-chip secure processors provide trusted execution environments with acceptable overhead Tamper-Evident environment, Private Tamper-Resistant environment Simulation results show 25-50% overhead for TE, 40-60% overhead for PTR processing New mechanisms can reduce the overhead to 5-15% for TE, and 10-25% for PTR processing (CSG Memo 465) Significant development effort underway FPGA/ASIC implementation of AEGIS processor

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