A Lightweight AES Implementation Against Bivariate First-Order DPA Attacks Weize Yu and Selçuk Köse
|
|
- Abner Moore
- 5 years ago
- Views:
Transcription
1 A Lightweight AES Implementation Against Bivariate First-Order DPA Attacks Weize Yu and Selçuk Köse Department of Electrical Engineering University of South Florida 1
2 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 2
3 Why Hardware Security is Important? 3
4 Side-Channel Attacks Possible side-channel attacks 4
5 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 5
6 Power Analysis Attacks Power supply Input data Core Chip without protection Power supply Input data Cryptographic circuit Core Key inside Cipher data Cryptographic chip 6
7 Simple Power Analysis (SPA) Attacks D. Oswald and R.-U. Bochum, ID and IP theft with Side-Channel Attacks, EMSEC,
8 Conventional First-Order (CFO) Differential Power Analysis (DPA) Attacks C. Tokunaga and D. Blaauw, Securing Encryption Systems With a Switched Capacitor Current Equalizer, IEEE J. Solid-State Cir., Jan P.-C. Liu, H.-C. Chang, and C.-Y. Lee, A Low Overhead DPA Countermeasure Circuit Based on Ring Oscillators, IEEE Trans. Cir. and Sys. 2: Express Briefs, Jul
9 Results of CFO DPA Attacks Successful CFO DPA attacks Unsuccessful CFO DPA attacks Correlation coefficient between the correct key and monitored power consumption is important C. Tokunaga and D. Blaauw, Securing Encryption Systems With a Switched Capacitor Current Equalizer, IEEE J. Solid-State Cir., Jan
10 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 10
11 Encryption Logic Circuit Modification Power information leakage 0-1 Drawback: High power/area/ performance overhead differential logic 0-1 and 1-0 are the same 0-0 and 1-1 are the same differential logic Combine them together 0-1 and 1-1 are the same 0-0 and 1-0 are the same K. Tiri, M. Akmal, and I. Verbauwhede, A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards, in Proc. 28th European Solid-State Circuits, Sep
12 Power Supply Scrambling stage 1 stage 2 stage 3 06/16/08 Drawback: High power/area/performance overhead Temperature Aware Behavioral Synthesis C. Tokunaga and D. Blaauw, Securing Encryption Systems With a Switched Capacitor Current Equalizer, IEEE J. Solid-State Circuits, Jan
13 Power Delivery Network (PDN) Modification 06/16/08 Drawback: High PDN impedence hurts the circuit's energy efficiency and robustness Temperature Aware Behavioral Synthesis X. Wang, W. Yueh, D. B. Roy, S. Narasimhan, Y. Zheng, S. Mukhopadhyay, D. Mukhopadhyay and S. Bhunia, Role of Power Grid in Side Channel Attack and Power-Grid-Aware Secure Design, in Proc. Design Automation Conference (DAC),
14 Random Dynamic Voltage Scaling (RDVS) Input data dependent P dyn = αcv 2 dd f c Randomly alter V dd Drawback: High power overhead 06/16/08 Temperature Aware Behavioral Synthesis K. Baddam and M. Zwolinski, Evaluation of Dynamic Voltage and Frequency Scaling as a Differential Power Analysis Countermeasure, in Proc. VLSI design, Jan
15 Plaintexts Masking Input data dependent P dyn = αcv 2 dd f c Drawback: High area/performance overhead due to a large amount of mask data N. Pramstaller, E. Oswald, S. Mangard, F. K. Gurkaynak, and S. Hane, A Masked AES ASIC Implementation, in Proc. Austrochip,
16 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 16
17 Aggressive Voltage Scaling (AVS) Technique AVS technique Low overhead N. D. P. Avirneni and A. K. Somani, Countering power analysis attacks using reliable and aggressive designs, IEEE Transactions on Computers, Jun
18 AVS Technique Against CFO DPA Attacks Correct key 150 Successful CFO DPA attacks on an S-box without countermeasure after inputting 10 thousand plaintexts Unsuccessful CFO DPA attacks on an S-box with AVS technique after inputting 1 million plaintexts Correct key 150 N. D. P. Avirneni and A. K. Somani, Countering power analysis attacks using reliable and aggressive designs, IEEE Transactions on Computers, Jun
19 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 19
20 BFO DPA Attacks on a Cryptographic Circuit with AVS Technique Two adjacent power consumptions of a Two adjacent input data CFO DPA attacks CFO DPA attacks V dd changes slowly BFO DPA attacks The power noise induced by randomly reshuffling Supply voltage V dd is eliminated by executing BFO DPA attacks! 20
21 Results of DPA Attacks on S-Boxes with AVS Technique Successful CFO DPA attacks on an S-box without countermeasure after inputting 1 thousand plaintexts Unsuccessful CFO DPA attacks on an S-box with AVS technique after inputting 100 thousand plaintexts Successful BFO DPA attacks on an S-box with AVS technique after inputting 6 thousand plaintexts 21
22 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 22
23 Advanced Encryption Standard (AES) Cryptographic Algorithm Plaintext Add round key Substitute bytes Round 1 Shift rows Mix columns DPA attacks Substitute bytes Shift rows Round m-1 Add round key Mix columns Substitute bytes Add round key Round 2 Shift rows Mix columns Substitute bytes Shift rows Round m Add round key Add round key Ciphertext 23
24 DPA Attacks on AES Engine Select input plaintexts to simplify DPA attacks. 1st encryption round of a typical 128-bit AES engine 24
25 Proposed Lightweight Masked AES Engine Conventional AES engine (1st encryption round) Proposed lightweight masked AES engine (1st encryption round) Mask: m=( ), ( ), ( ), ( ),... or m=( ), ( ), ( ), ( ),... Constant sequence Random sequence 25
26 Results of BFO DPA Attacks on AES Engines with AVS Technique Successful BFO DPA attacks on a conventional AES engine with AVS technique after inputting 6 thousand plaintexts Successful BFO DPA attacks on a lightweight masked AES engine (constant masking sequence) with AVS technique after inputting 500 thousand plaintexts Unsuccessful BFO DPA attacks on a lightweight masked AES engine (random masking sequence) with AVS technique after inputting 1 million plaintexts 26
27 Presentation Flow p Side-channel attacks p Power analysis attacks (PAA) p Previous countermeasures against PAA p Aggressive voltage scaling (AVS) against conventional first-order (CFO) DPA attacks p Bivariate first-order (BFO) DPA attacks on p Proposed countermeasure for securing against BFO DPA attacks p Conclusion 27
28 Conclusion Cryptographic circuit is vulnerable against power analysis attacks Aggressive voltage scaling (AVS) technique is an efficient countermeasure against conventional first-order (CFO) DPA attacks with low overhead Conventional AES engine employs AVS technique is vulnerable against bivariate first-order (BFO) DPA attacks Lightweight random masked AES engine with AVS technique thwarts DPA attacks efficiently with negligible power/area/ performance overhead 28
29 Thanks! 29
A Countermeasure Circuit for Secure AES Engine against Differential Power Analysis
A Countermeasure Circuit for Secure AES Engine against Differential Power Analysis V.S.Subarsana 1, C.K.Gobu 2 PG Scholar, Member IEEE, SNS College of Engineering, Coimbatore, India 1 Assistant Professor
More informationA Simple Power Analysis Attack Against the Key Schedule of the Camellia Block Cipher
A Simple Power Analysis Attack Against the Key Schedule of the Camellia Block Cipher Lu Xiao and Howard M. Heys 2 QUALCOMM Incorporated, lxiao@qualcomm.com 2 Electrical and Computer Engineering, Faculty
More informationHOST Differential Power Attacks ECE 525
Side-Channel Attacks Cryptographic algorithms assume that secret keys are utilized by implementations of the algorithm in a secure fashion, with access only allowed through the I/Os Unfortunately, cryptographic
More informationSide channel attack: Power Analysis. Chujiao Ma, Z. Jerry Shi CSE, University of Connecticut
Side channel attack: Power Analysis Chujiao Ma, Z. Jerry Shi CSE, University of Connecticut Conventional Cryptanalysis Conventional cryptanalysis considers crypto systems as mathematical objects Assumptions:
More informationCountering power analysis attacks by exploiting characteristics of multicore processors
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. IEICE Electronics Express, Vol.*, o.*, 1 11 Countering power analysis attacks by exploiting
More informationA Defense Mechanism for Differential Power Analysis Attack in AES
Journal of Computer Science Original Research Paper A Defense Mechanism for Differential Power Analysis Attack in AES 1 M. Rajaramand 2 J. Vijaya 1 Anna University, Chennai, India 2 Vice Chancellor, Anna
More informationExperiments in Attacking FPGA-Based Embedded Systems using Differential Power Analysis
Experiments in Attacking FPGA-Based Embedded Systems using Differential Power Analysis Song Sun Zijun Yan Joseph Zambreno Dept. of Electrical and Computer Engineering Iowa State University Ames, IA 50011
More informationCorrelated Power Noise Generator as a Low Cost DPA Countermeasures to Secure Hardware AES Cipher
Correlated Power Noise Generator as a Low Cost DPA Countermeasures to Secure Hardware AES Cipher Najeh Kamoun 1, Lilian Bossuet 2, and Adel Ghazel 1 1 CIRTA COM, SUP COM 2 IMS, University of Bordeaux Tunis,
More informationEMERGENCE of internet of things (IoT) devices is challenging
2934 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I: REGULAR PAPERS, VOL. 64, NO. 11, NOVEMBER 2017 A Lightweight Masked AES Implementation for Securing IoT Against CPA Attacks Weize Yu and Selçuk Köse, Member,
More informationA physical level perspective
UMass CS 660 Advanced Information Assurance Spring 2011Guest Lecture Side Channel Analysis A physical level perspective Lang Lin Who am I 5 th year PhD candidate in ECE Advisor: Professor Wayne Burleson
More informationCorrelated Power Noise Generator as a Low Cost DPA Countermeasure to Secure Hardware AES Cipher
Author manuscript, published in "Proceeding of the 3rd IEEE International Conference on Signals, Circuits and Systems, SCS 2009, pp. 1-6, Djerba, Tunisa, November 2009., Tunisia (2009)" Correlated Power
More informationSIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017
SIDE CHANNEL ATTACKS AGAINST IOS CRYPTO LIBRARIES AND MORE DR. NAJWA AARAJ HACK IN THE BOX 13 APRIL 2017 WHAT WE DO What we do Robust and Efficient Cryptographic Protocols Research in Cryptography and
More informationPower Analysis Attacks
Power Analysis Attacks Elisabeth Oswald Computer Science Department Crypto Group eoswald@cs.bris.ac.uk Elisabeth.Oswald@iaik.tugraz.at Outline Working principle of power analysis attacks DPA Attacks on
More informationPrototype IC with WDDL and Differential Routing DPA Resistance Assessment
Prototype IC with WDDL and Differential Routing DPA Resistance Assessment Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, and Ingrid Verbauwhede,2 Electrical Engineering
More informationPOWER ANALYSIS RESISTANT SRAM
POWER ANALYSIS RESISTANT ENGİN KONUR, TÜBİTAK-UEKAE, TURKEY, engin@uekae.tubitak.gov.tr YAMAN ÖZELÇİ, TÜBİTAK-UEKAE, TURKEY, yaman@uekae.tubitak.gov.tr EBRU ARIKAN, TÜBİTAK-UEKAE, TURKEY, ebru@uekae.tubitak.gov.tr
More informationOnce upon a time... A first-order chosen-plaintext DPA attack on the third round of DES
A first-order chosen-plaintext DPA attack on the third round of DES Oscar Reparaz, Benedikt Gierlichs KU Leuven, imec - COSIC CARDIS 2017 Once upon a time... 14 November 2017 Benedikt Gierlichs - DPA on
More informationON PRACTICAL RESULTS OF THE DIFFERENTIAL POWER ANALYSIS
Journal of ELECTRICAL ENGINEERING, VOL. 63, NO. 2, 212, 125 129 COMMUNICATIONS ON PRACTICAL RESULTS OF THE DIFFERENTIAL POWER ANALYSIS Jakub Breier Marcel Kleja This paper describes practical differential
More informationA Power Attack Method Based on Clustering Ruo-nan ZHANG, Qi-ming ZHANG and Ji-hua CHEN
2017 International Conference on Computer, Electronics and Communication Engineering (CECE 2017) ISBN: 978-1-60595-476-9 A Power Attack Method Based on Clustering Ruo-nan ZHANG, Qi-ming ZHANG and Ji-hua
More informationSide-Channel Countermeasures for Hardware: is There a Light at the End of the Tunnel?
Side-Channel Countermeasures for Hardware: is There a Light at the End of the Tunnel? 11. Sep 2013 Ruhr University Bochum Outline Power Analysis Attack Masking Problems in hardware Possible approaches
More informationArea Optimization in Masked Advanced Encryption Standard
IOSR Journal of Engineering (IOSRJEN) ISSN (e): 2250-3021, ISSN (p): 2278-8719 Vol. 04, Issue 06 (June. 2014), V1 PP 25-29 www.iosrjen.org Area Optimization in Masked Advanced Encryption Standard R.Vijayabhasker,
More informationImplementation of Full -Parallelism AES Encryption and Decryption
Implementation of Full -Parallelism AES Encryption and Decryption M.Anto Merline M.E-Commuication Systems, ECE Department K.Ramakrishnan College of Engineering-Samayapuram, Trichy. Abstract-Advanced Encryption
More informationDesign of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures
Design of an Efficient Architecture for Advanced Encryption Standard Algorithm Using Systolic Structures 1 Suresh Sharma, 2 T S B Sudarshan 1 Student, Computer Science & Engineering, IIT, Khragpur 2 Assistant
More information@ 2014 SEMAR GROUPS TECHNICAL SOCIETY.
www.semargroup.org, www.ijsetr.com ISSN 2319-8885 Vol.03,Issue.02, February-2014, Pages:0350-0355 Performance Improvement in Fault Detection Schemes for the Advanced Encryption Standard Using Composite
More informationSuccessfully Attacking Masked AES Hardware Implementations
Successfully Attacking Masked AES Hardware Implementations Stefan Mangard, Norbert Pramstaller, and Elisabeth Oswald Institute for Applied Information Processing and Communications (IAIK) Graz University
More informationMinimum Area Cost for a 30 to 70 Gbits/s AES Processor
Minimum Area Cost for a 30 to 70 Gbits/s AE Processor Alireza Hodjat and Ingrid Verbauwhede Electrical Engineering Department University of California, Los Angeles {ahodjat, ingrid} @ ee.ucla.edu Abstract
More informationELECTRONICS DEPARTMENT
ELECTRONICS DEPARTMENT By Eng. 28 th Mar MUSTAFA 2012 M. Efficient SHIPLEImplementation of AES Algorithm Immune to DPA Attack Cryptography processing plaintext cipher text format Block Cipher Stream Cipher
More informationThe Davies-Murphy Power Attack. Sébastien Kunz-Jacques Frédéric Muller Frédéric Valette DCSSI Crypto Lab
The Davies-Murphy Power Attack Sébastien Kunz-Jacques Frédéric Muller Frédéric Valette DCSSI Crypto Lab Introduction Two approaches for attacking crypto devices traditional cryptanalysis Side Channel Attacks
More informationPower Analysis of MAC-Keccak: A Side Channel Attack. Advanced Cryptography Kyle McGlynn 4/12/18
Power Analysis of MAC-Keccak: A Side Channel Attack Advanced Cryptography Kyle McGlynn 4/12/18 Contents Side-Channel Attack Power Analysis Simple Power Analysis (SPA) Differential Power Analysis (DPA)
More informationPower-Analysis Attack on an ASIC AES implementation
Power-Analysis Attack on an ASIC AES implementation Sıddıka Berna Örs 1 Frank Gürkaynak 2 Elisabeth Oswald 3,4 Bart Preneel 1 1 Katholieke Universiteit Leuven, Dept. ESAT/SCD-COSIC, Kasteelpark Arenberg
More informationECRYPT II Workshop on Physical Attacks November 27 th, Graz, Austria. Stefan Mangard.
Building Secure Hardware ECRYPT II Workshop on Physical Attacks November 27 th, Graz, Austria Stefan Mangard Infineon Technologies, Munich, Germany Stefan.Mangard@infineon.com Outline Assets and Requirements
More informationA Design Methodology for Secured ICs Using Dynamic Current Mode Logic
A Design Methodology for Secured ICs Using Dynamic Current Mode Logic Mace F., Standaert F.-X., Quisquater J.-J., Legat J.-D. UCL Crypto Group Microelectronics Laboratory Universite Catholique de Louvain
More informationReliable Physical Unclonable Function based on Asynchronous Circuits
Reliable Physical Unclonable Function based on Asynchronous Circuits Kyung Ki Kim Department of Electronic Engineering, Daegu University, Gyeongbuk, 38453, South Korea. E-mail: kkkim@daegu.ac.kr Abstract
More informationSynthesis of Fault-Attack Countermeasures for Cryptographic Circuits
Synthesis of Fault-Attack Countermeasures for Cryptographic Circuits Hassan Eldib, Meng Wu, and Chao Wang CAV, July 23, 2016 Cryptographic Algorithm: an example Plaintext Chip Ciphertext 0110 1001 1011
More informationDr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010
CS 494/594 Computer and Network Security Dr. Jinyuan (Stella) Sun Dept. of Electrical Engineering and Computer Science University of Tennessee Fall 2010 1 Secret Key Cryptography Block cipher DES 3DES
More informationFDTC 2010 Fault Diagnosis and Tolerance in Cryptography. PACA on AES Passive and Active Combined Attacks
FDTC 21 Fault Diagnosis and Tolerance in Cryptography PACA on AES Passive and Active Combined Attacks Christophe Clavier Benoît Feix Georges Gagnerot Mylène Roussellet Limoges University Inside Contactless
More informationSecond-Order Power Analysis Attacks against Precomputation based Masking Countermeasure
, pp.259-270 http://dx.doi.org/10.14257/ijsh.2016.10.3.25 Second-Order Power Analysis Attacks against Precomputation based Masking Countermeasure Weijian Li 1 and Haibo Yi 2 1 School of Computer Science,
More informationHardware Security. Debdeep Mukhopadhyay
Hardware Security Debdeep Mukhopadhyay Secured Embedded Architecture Laboratory (SEAL) Department of Computer Science and Engineering Indian Institute of Technology Kharagpur Kharagpur, West Bengal, INDIA
More informationCorrelation-Enhanced Power Analysis Collision Attack
Correlation-Enhanced Power Analysis Collision Attack Amir Moradi 1, Oliver Mischke 1, and Thomas Eisenbarth 2 1 Horst Görtz Institute for IT Security Ruhr University Bochum, Germany {moradi, mischke}@crypto.rub.de
More informationCIS 3362 Final Exam 12/4/2013. Name:
CIS 3362 Final Exam 12/4/2013 Name: 1) (10 pts) Since the use of letter frequencies was known to aid in breaking substitution ciphers, code makers in the Renaissance added "twists" to the standard substitution
More informationA Design of Low Power NAND based Multiplexer Circuit in CMOS to DPL Converter for Smart card Security System Ms.S.NAGALAKSHMI #1, Ms.R.
A Design of Low Power NAND based Multiplexer Circuit in CMOS to DPL Converter for Smart card Security System Ms.S.NAGALAKSHMI #1, Ms.R.CHITRA #2 #1 P.G.Scholar,II M.E.VLSI Design, #2 Assistant Professor
More informationA PRACTICAL APPROACH TO POWER TRACE MEASUREMENT FOR DIFFERENTIAL POWER ANALYSIS BASED ATTACKS
Bulletin of the Transilvania University of Braşov Series I: Engineering Sciences Vol. 6 (55) No. 2-2013 A PRACTICAL APPROACH TO POWER TRACE MEASUREMENT FOR DIFFERENTIAL POWER ANALYSIS BASED ATTACKS C.L.
More informationHow Far Should Theory be from Practice?
How Far Should Theory be from Practice? Evaluation of a Countermeasure Amir Moradi and Oliver Mischke Horst Görtz Institute for IT Security, Ruhr University Bochum, Germany {moradi,mischke}@crypto.rub.de
More informationVLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH THE EFFICIENT MULTIPLICATIVE INVERSE UNIT
VLSI ARCHITECTURE FOR NANO WIRE BASED ADVANCED ENCRYPTION STANDARD (AES) WITH THE EFFICIENT MULTIPLICATIVE INVERSE UNIT K.Sandyarani 1 and P. Nirmal Kumar 2 1 Research Scholar, Department of ECE, Sathyabama
More informationOn-Line Self-Test of AES Hardware Implementations
On-Line Self-Test of AES Hardware Implementations G. Di Natale, M. L. Flottes, B. Rouzeyre Laboratoire d Informatique, de Robotique et de Microélectronique de Montpellier Université Montpellier II / CNRS
More informationBlind Differential Cryptanalysis for Enhanced Power Attacks
Blind Differential Cryptanalysis for Enhanced Power Attacks Bart Preneel COSIC K.U.Leuven - Belgium bart.preneel(at)esat.kuleuven.be Joint work with Helena Handschuh Concept Differential cryptanalysis
More informationTowards a Software Approach to Mitigate Correlation Power Analysis
Towards a Software Approach to Mitigate Correlation Power Analysis Ibraheem Frieslaar,2, Barry Irwin 2 Modelling and Digital Science, Council for Scientific and Industrial Research, Pretoria, South Africa.
More informationFundamentals of Cryptography
Fundamentals of Cryptography Topics in Quantum-Safe Cryptography June 23, 2016 Part III Data Encryption Standard The Feistel network design m m 0 m 1 f k 1 1 m m 1 2 f k 2 2 DES uses a Feistel network
More informationAn Improved DPA Attack on DES with Forth and Back Random Round Algorithm
International Journal of Network Security, Vol.19, No.2, PP.285-294, Mar. 2017 (DOI: 10.6633/IJNS.201703.19(2).13) 285 An Improved DPA Attack on with Forth and Back Random Round Algorithm Cai-Sen Chen
More informationPipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications
, Vol 7(4S), 34 39, April 204 ISSN (Print): 0974-6846 ISSN (Online) : 0974-5645 Pipelined Quadratic Equation based Novel Multiplication Method for Cryptographic Applications B. Vignesh *, K. P. Sridhar
More informationPRACTICAL DPA ATTACKS ON MDPL. Elke De Mulder, Benedikt Gierlichs, Bart Preneel, Ingrid Verbauwhede
PRACTICAL DPA ATTACKS ON MDPL Elke De Mulder, Benedikt Gierlichs, Bart Preneel, Ingrid Verbauwhede K.U. Leuven, ESAT/SCD-COSIC and IBBT Kasteelpark Arenberg 10, B-3001 Leuven-Heverlee, Belgium {elke.demulder,benedikt.gierlichs,bart.preneel,ingrid.verbauwhede}@esat.kuleuven.be
More informationSecret Key Cryptography
Secret Key Cryptography 1 Block Cipher Scheme Encrypt Plaintext block of length N Decrypt Secret key Cipher block of length N 2 Generic Block Encryption Convert a plaintext block into an encrypted block:
More informationSide Channel Analysis of an Automotive Microprocessor
ISSC 2008, Galway. June 18 19 Side Channel Analysis of an Automotive Microprocessor Mark D. Hamilton, Michael Tunstall,EmanuelM.Popovici, and William P. Marnane Dept. of Microelectronic Engineering, Dept.
More informationChosen-IV Correlation Power Analysis on KCipher-2 and a Countermeasure
Fourth International Workshop on Constructive Side-Channel Analysis and Secure Design (COSADE 2013) Chosen-IV Correlation Power Analysis on KCipher-2 and a Countermeasure Takafumi Hibiki*, Naofumi Homma*,
More informationFPGA Based Design of AES with Masked S-Box for Enhanced Security
International Journal of Engineering Science Invention ISSN (Online): 2319 6734, ISSN (Print): 2319 6726 Volume 3 Issue 5ǁ May 2014 ǁ PP.01-07 FPGA Based Design of AES with Masked S-Box for Enhanced Security
More informationSide-channel Power Analysis of Different Protection Schemes Against Fault Attacks on AES
Side-channel Power Analysis of Different Protection Schemes Against Fault Attacks on AES Pei Luo 1, Yunsi Fei 1, Liwei Zhang 2, and A. Adam Ding 2 1 Department of Electrical and Computer Engineering, Northeastern
More informationMicroelectronics and Control System (M.Tech), Electronics and Instrumentation Engineering, Dayananda
National conference on Engineering Innovations and Solutions (NCEIS 2018) International Journal of Scientific Research in Computer Science, Engineering and Information Technology 2018 IJSRCSEIT Volume
More informationSecurity against Timing Analysis Attack
International Journal of Electrical and Computer Engineering (IJECE) Vol. 5, No. 4, August 2015, pp. 759~764 ISSN: 2088-8708 759 Security against Timing Analysis Attack Deevi Radha Rani 1, S. Venkateswarlu
More informationBreaking Korea Transit Card with Side-Channel Attack
Breaking Korea Transit Card with Side-Channel Attack -Unauthorized Recharging- Black Hat Asia 2017 Tae Won Kim, Tae Hyun Kim, and Seokhie Hong Outline 1. Attack Goal & Scenario 2. Target Device Details
More informationComputer and Data Security. Lecture 3 Block cipher and DES
Computer and Data Security Lecture 3 Block cipher and DES Stream Ciphers l Encrypts a digital data stream one bit or one byte at a time l One time pad is example; but practical limitations l Typical approach
More informationPower Analysis Attacks against FPGA Implementations of the DES
Power Analysis Attacks against FPGA Implementations of the DES François-Xavier Standaert 1, Sıddıka Berna Örs2, Jean-Jacques Quisquater 1, Bart Preneel 2 1 UCL Crypto Group Laboratoire de Microélectronique
More informationAdvanced Encryption Standard and Modes of Operation. Foundations of Cryptography - AES pp. 1 / 50
Advanced Encryption Standard and Modes of Operation Foundations of Cryptography - AES pp. 1 / 50 AES Advanced Encryption Standard (AES) is a symmetric cryptographic algorithm AES has been originally requested
More informationInternational Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 3 Issue 3, March 2014
ENCRYPTION AND DECRYPTION IN COMPLEX PARALLELISM H.Anusuya Baby 1, Christo Ananth 2 1 (ECE, Francis Xavier Engineering College/ Anna University, India) 2 (ECE, Francis Xavier Engineering College/ Anna
More informationA Reliable Architecture for Substitution Boxes in Integrated Cryptographic Devices
Author manuscript, published in "DCIS'08: Conference on Design of Circuits and Integrated Systems, (2008)" A Reliable Architecture for Substitution Boxes in Integrated Cryptographic Devices G. Di Natale,
More informationChapter 2 Introduction to Side-Channel Attacks
Chapter 2 Introduction to Side-Channel Attacks François-Xavier Standaert 2.1 Introduction A cryptographic primitive can be considered from two points of view: on the one hand, it can be viewed as an abstract
More informationP V Sriniwas Shastry et al, Int.J.Computer Technology & Applications,Vol 5 (1),
On-The-Fly AES Key Expansion For All Key Sizes on ASIC P.V.Sriniwas Shastry 1, M. S. Sutaone 2, 1 Cummins College of Engineering for Women, Pune, 2 College of Engineering, Pune pvs.shastry@cumminscollege.in
More informationBreaking the Bitstream Decryption of FPGAs
Breaking the Bitstream Decryption of FPGAs 05. Sep. 2012 Amir Moradi Embedded Security Group, Ruhr University Bochum, Germany Acknowledgment Christof Paar Markus Kasper Timo Kasper Alessandro Barenghi
More informationNetwork Security Technology Project
Network Security Technology Project Shanghai Jiao Tong University Presented by Wei Zhang zhang-wei@sjtu.edu.cn!1 Part I Implement the textbook RSA algorithm. The textbook RSA is essentially RSA without
More informationCOSADE Conference Series
COSADE Conference Series Past, Present, and Future Sorin A. Huss 1 / 24 Initiators Werner Schindler Sorin Alexander Huss 2 / 24 Constructive Side-Channel Analysis and Secure Design Time Period 2010 to
More informationEfficient DPA Attacks on AES Hardware Implementations
I. J. Communications, Network and System Sciences. 008; : -03 Published Online February 008 in SciRes (http://www.srpublishing.org/journal/ijcns/). Efficient DPA Attacks on AES Hardware Implementations
More informationDesign and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays
Design and Implementation of Parallel AES Encryption Engines for Multi-Core Processor Arrays M.Sambasiva Reddy 1, P.James Vijay 2, B.Murali Krishna 3 Assistant Professor 1, Assistant Professor 2, Assistant
More informationENGI 8868/9877 Computer and Communications Security III. BLOCK CIPHERS. Symmetric Key Cryptography. insecure channel
(a) Introduction - recall symmetric key cipher: III. BLOCK CIPHERS k Symmetric Key Cryptography k x e k y yʹ d k xʹ insecure channel Symmetric Key Ciphers same key used for encryption and decryption two
More informationAn EDA-Friendly Protection Scheme against Side-Channel Attacks
An EDA-Friendly Protection Scheme against Side-Channel Attacks Ali Galip Bayrak, Nikola Velickovic, Francesco azzoni, David Novo, Philip Brisk and Paolo Ienne School of Computer and Communication Sciences
More informationFault Sensitivity Analysis
Fault Sensitivity Analysis Yang Li 1, Kazuo Sakiyama 1, Shigeto Gomisawa 1, Toshinori Fukunaga 2, Junko Takahashi 1,2, and Kazuo Ohta 1 1 Department of Informatics, The University of Electro-Communications
More informationEncryption / decryption system. Fig.1. Block diagram of Hummingbird
801 Lightweight VLSI Design of Hybrid Hummingbird Cryptographic Algorithm NIKITA ARORA 1, YOGITA GIGRAS 2 12 Department of Computer Science, ITM University, Gurgaon, INDIA 1 nikita.0012@gmail.com, 2 gigras.yogita@gmail.com
More informationDeKaRT: A New Paradigm for Key-Dependent Reversible Circuits
DeKaRT: A New Paradigm for Key-Dependent Reversible Circuits Jovan D. Golić System on Chip, Telecom Italia Lab Telecom Italia Via Guglielmo Reiss Romoli 274, I-00148 Turin, Italy jovan.golic@tilab.com
More informationDifferential Power Analysis in AES: A Crypto Anatomy
Jude Angelo Ambrose Naeill Aldon Aleksandar Ignjatovic Sri Parameswaran School of Computer Science and Engineering University of New South Wales, Sydney, Australia {ajangelo, naeill, ignjat, sridevan}@cse.unsw.edu.au
More informationFault injection attacks on cryptographic devices and countermeasures Part 1
Fault injection attacks on cryptographic devices and countermeasures Part 1 Israel Koren Department of Electrical and Computer Engineering University of Massachusetts Amherst, MA Outline Introduction -
More informationA High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm
A High-Performance VLSI Architecture for Advanced Encryption Standard (AES) Algorithm N. M. Kosaraju, M. Varanasi & Saraju P. Mohanty VLSI Design and CAD Laboratory Homepage: http://www.vdcl.cse.unt.edu
More informationEfficient Hardware Design and Implementation of AES Cryptosystem
Efficient Hardware Design and Implementation of AES Cryptosystem PRAVIN B. GHEWARI 1 MRS. JAYMALA K. PATIL 1 AMIT B. CHOUGULE 2 1 Department of Electronics & Telecommunication 2 Department of Computer
More informationAccelerating Correlation Power Analysis Using Graphics Processing Units (GPUs)
Accelerating Correlation Power Analysis Using Graphics Processing Units (GPUs) Hasindu Gamaarachchi, Roshan Ragel Department of Computer Engineering University of Peradeniya Peradeniya, Sri Lanka hasindu8@gmailcom,
More informationComputer Security. 08. Cryptography Part II. Paul Krzyzanowski. Rutgers University. Spring 2018
Computer Security 08. Cryptography Part II Paul Krzyzanowski Rutgers University Spring 2018 March 23, 2018 CS 419 2018 Paul Krzyzanowski 1 Block ciphers Block ciphers encrypt a block of plaintext at a
More informationIntroduction to Modern Symmetric-Key Ciphers
Introduction to Modern Symmetric-Key Ciphers 1 Objectives Review a short history of DES. Define the basic structure of DES. List DES alternatives. Introduce the basic structure of AES. 2 Data Encryption
More informationMasking as a Side-Channel Countermeasure in Hardware
Masking as a Side-Channel Countermeasure in Hardware 6. September 2016 Ruhr-Universität Bochum 1 Agenda Physical Attacks and Side Channel Analysis Attacks Measurement setup Power Analysis Attacks Countermeasures
More informationA Chaos-based Arithmetic Logic Unit and Implications for Logic Obfuscation
A Chaos-based Arithmetic Logic Unit and Implications for Logic Obfuscation Garrett S. Rose IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, Florida, July 2014. 2014 IEEE. Personal use of
More informationComputer Security 3/23/18
s s encrypt a block of plaintext at a time and produce ciphertext Computer Security 08. Cryptography Part II Paul Krzyzanowski DES & AES are two popular block ciphers DES: 64 bit blocks AES: 128 bit blocks
More informationBlock Ciphers and the Data Encryption Standard (DES) Modified by: Dr. Ramzi Saifan
Block Ciphers and the Data Encryption Standard (DES) Modified by: Dr. Ramzi Saifan Block ciphers Keyed, invertible Large key space, large block size A block of plaintext is treated as a whole and used
More informationA Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
IJCSNS International Journal of Computer Science and Network Security, VOL.9 No.9, September 2009 305 A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box Muhammad
More informationFault Sensitivity Analysis
Fault Sensitivity Analysis Yang Li 1, Kazuo Sakiyama 1, Shigeto Gomisawa 1, Toshinori Fukunaga 2, Junko Takahashi 1,2,andKazuoOhta 1 1 Department of Informatics, The University of Electro-Communications
More informationCSC 474/574 Information Systems Security
CSC 474/574 Information Systems Security Topic 2.2 Secret Key Cryptography CSC 474/574 Dr. Peng Ning 1 Agenda Generic block cipher Feistel cipher DES Modes of block ciphers Multiple encryptions Message
More informationFPGA Implementation of Cryptographic Algorithm in a Multiprocessing System
FPGA Implementation of Cryptographic Algorithm in a Multiprocessing System S.Priya, Swetha Abraham M.E (VLSI Design), Department of ECE, Karpaga Vinayaga College of Engineering and Technology, Madhuranthagam,
More information6T- SRAM for Low Power Consumption. Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1
6T- SRAM for Low Power Consumption Mrs. J.N.Ingole 1, Ms.P.A.Mirge 2 Professor, Dept. of ExTC, PRMIT &R, Badnera, Amravati, Maharashtra, India 1 PG Student [Digital Electronics], Dept. of ExTC, PRMIT&R,
More informationCountermeasures against EM Analysis
Countermeasures against EM Analysis Paolo Maistri 1, SebastienTiran 2, Amine Dehbaoui 3, Philippe Maurine 2, Jean-Max Dutertre 4 (1) (2) (3) (4) Context Side channel analysis is a major threat against
More informationSimplified Adaptive Multiplicative Masking for AES
Simplified Adaptive Multiplicative Masking for AES Elena Trichina, Domenico De Seta, and Lucia Germani Cryptographic Design Center, Gemplus Technology R& D Via Pio Emanuelli, 0043 Rome, Italy {elena.trichina,domenico.deseta,lucia.germani}@gemplus.com
More informationGated-Demultiplexer Tree Buffer for Low Power Using Clock Tree Based Gated Driver
Gated-Demultiplexer Tree Buffer for Low Power Using Clock Tree Based Gated Driver E.Kanniga 1, N. Imocha Singh 2,K.Selva Rama Rathnam 3 Professor Department of Electronics and Telecommunication, Bharath
More informationDietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures
Dietary Recommendations for Lightweight Block Ciphers: Power, Energy and Area Analysis of Recently Developed Architectures Lejla Batina, Amitabh Das, Barış Ege, Elif Bilge Kavun, Nele Mentens, Christof
More informationFault Sensitivity Analysis
Fault Sensitivity Analysis Yang Li, Kazuo Sakiyama, Shigeto Gomisawa, Kazuo Ohta The University of Electro-Communications liyang@ice.uec.ac.jp Toshinori Fukunaga, Junko Takahashi NTT Information Sharing
More informationDESIGNING OF STREAM CIPHER ARCHITECTURE USING THE CELLULAR AUTOMATA
DESIGNING OF STREAM CIPHER ARCHITECTURE USING THE CELLULAR AUTOMATA 1 Brundha K A MTech Email: 1 brundha1905@gmail.com Abstract Pseudo-random number generators (PRNGs) are a key component of stream ciphers
More informationData Encryption Standard
ECE 646 Lecture 7 Data Encryption Standard Required Reading W. Stallings, "Cryptography and Network-Security," 5th Edition, Chapter 3: Block Ciphers and the Data Encryption Standard Chapter 6.1: Multiple
More informationTowards a Software Approach to Mitigate Correlation Power Analysis
Towards a Software Approach to Mitigate Correlation Power Analysis Ibraheem Frieslaar,2, Barry Irwin 2 Modelling and Digital Science, Council for Scientific and Industrial Research, Pretoria, South Africa.
More informationCountermeasures against EM Analysis for a Secured FPGA-based AES Implementation
Countermeasures against EM Analysis for a Secured FPGA-based AES Implementation P. Maistri 1, S. Tiran 2, P. Maurine 2, I. Koren 3, R. Leveugle 1 1 Univ. Grenoble Alpes, TIMA Laboratory, F-38031 Grenoble
More information