1. state the priority of interrupts of Draw and explain MSW format of List salient features of

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Q.1) 1. state the priority of interrupts of 80286. Ans- 1. Instruction exceptions 2. Single step 3. NMI 4.

List salient features of 80286. 1. Advanced version of 8086 designed for multi-user and multitasking. 2.

1 Q.1) 1. state the priority of interrupts of Ans- 1. Instruction exceptions 2. Single step 3. NMI 4. Processor extension segment overrun 5. INTR 6. INT 2. Draw and explain MSW format of Ans- 3.List salient features of Advanced version of 8086 designed for multi-user and multitasking. 2. Six times faster 3. Hardware and software support for OS 4. On chip MMU 5. Used in IBM PC-AT 6.24 bit address bus 7.16 MB physical memory 8.1 GB virtual memory

2 4. List all general purpose registers. Ans- AX,BX,CX,DX,SI,DI,SP,BP Q.2 1 with neat diagram explain segment descriptor cache register. Ans Concept of caching minimize the time required for fetching the frequently required descriptor information from main memory. Maintaining most frequently required data for execution in a high speed memory called cache memory.6-byte Segment descriptor cache Register is assigned for each segment. These are not available for programming. A segment descriptor cache register is assigned to each of the four segment registers (CS, SS, DS, ES). Segment descriptors are automatically loaded (cached) into a segment descriptor cache register whenever the associated segment register is loaded with a selector. Only segment descriptors may be loaded into segment descriptor cache registers. Once loaded, all references to that segment of memory use the cached descriptor information instead of recessing the descriptor. The descriptor cache registers are not visible to programs. 2. state the function of following. 1.BUSY#- The busy input signal indicate the CPU that the coprocessor is busy with the allotted task. 2.LOCK# - The Lock# output pin enables the CPU to prevent the other bus masters (coprocessors) from gaining the control of the system bus. 3.COD/INTA- this output signal in combination with M/IO# and S1#-S0# distinguishes different memory I/O and INTA cycles. 4. HOLD- the bus hold input pin enables the other bus masters to gain control of the system bus if it is asserted. 5. Draw and explain flag register format.

3 IOPL- it indicates the privilege of the current IO operations. Or set if user add privileges to any segment or memory. NT- it set in nested task condition or task switching concept it is in set condition. 4. explain LDT and GDT Ans-

4 Descriptor table is an array of 8k descriptor. The upper 13 bit of selector field (index) points in particular entry in a descriptor table. Each descriptor is an 8-byte entry in the table. Thus descriptors table requires 8K X 8 = 64K memory. Each selector can address a segment of size 64k. There can be at most 8k local and 8k global descriptors per task. A GDT contain Global descriptor common to all the task. A LDT contains descriptor specific to particular task. All the task may have their private LDTs. The GDT may contain all the descriptor types except interrupt and trap descriptors. The LDT contain task gate and call gate descriptors. A segment cannot be accesses, if its descriptor does not exist in either LDT or GDT at that instant. Q.3 1. what is descriptor and explain code and data descriptor. Descriptor---descriptor carry all relevant information regarding a segment and it s access rights.

Note- write description from above table. 2. mention and explain blocks of 80286. Ans- 1. Address Unit 2.

5 Note- write description from above table. 2. mention and explain blocks of Ans- 1. Address Unit 2. Bus Unit Calculate the physical addresses of the instruction and data that the CPU want to access Address lines derived by this unit may be used to address different peripherals. Physical address computed by the address unit is handed over to the BUS unit. Transmit the physical address over address bus A0 A23.

6 3. Instruction Unit Instruction Pipelining. Prefetcher module in the bus unit performs this task of prefetching. Bus controller controls the prefetcher module. Fetched instructions are arranged in a 6 byte prefetch queue. Processor Extension Interface Module Take care of communication b/w CPU and a coprocessor. Receive arranged instructions from 6 byte prefetch queue. Instruction decoder decodes the instruction one by one and are latched onto a decoded instruction queue. O/p of the decoding circuit drives a control circuit in the Execution unit. 4. Execution unit Control unit is responsible for executing the instructions received from the decoded instruction queue. Contains Register Bank. ALU is the heart of execution unit. After execution ALU sends the result either over data bus or back to the register bank. 3. Explain the real addressing mode of

7 In real addressing mode of operation of it just act as a fast the instruction set is upwardly compatible with that of the addresses only 1 MB of physical memory using A0-A19 lines. The lines A20-A23 are not used. The 20 bit physical address is formed same way as that in The contents of segment registers are used as segment address. The other register depending upon the addressing mode contain the offset address. as in the physical memory is fixed with two areas such as system initialization and interrupt vector table. In the real mode the first 1KB of memory starting from address 00000Hto 003FFH is reserved for interrupt vector table. Also address from FFFF0H to FFFFFH are reserved for system initialization. the by default start in real address mode. 4. Explain IDT. Ans

8 Besides the local and global descriptor tables the has third type called interrupt descriptor table. these are used to store task gate, interrupt gate and trap gate. the IDT has a 24 bit base address and 16 bit limit address. Load interrupt descriptor table or LIDT instruction loads these internal registers data. The IDT of is able to handle up to 256 interrupt descriptor. The IDT entries can be referred to by using INT instruction or external interrupts or exceptions. Six byte are required for each interrupt in an interrupt descriptor table.

Architecture of 8086 Microprocessor

MCQ on Microprocessor and Interfacing Technique S.E.Compure (Sem-II) UNIT 1 Architecture of 8086 Microprocessor 1 marks Questions 1. Which is first microprocessor? (a) 8008 (b) 8085 (c) 8086 (d) 4004 2.